NCP51100ASNT1G

DATA SHEET www.onsemi.com Single 2 A High-Speed, Low-Side Gate Driver Product Preview NCP51100 SOT23−5 CASE 527AH Features • • • • • • • • • Industry−Standard Pinouts 11 V to 18 V Operating Range 3 A Peak Sink/Source at VDD = 12 V 2.5 A Sink / 1.8 A Source at VOUT = 6 V 14 ns / 7 ns Typical Rise/Fall Times (1 nF Load) Under 20 ns Typical Propagation Delay Time MillerDrivet Technology 5−Lead SOT23 Package Rated from –40°C to +125°C Ambient AAA AAA M = Specific Device Code = Month Code PIN CONNECTIONS IN 1 GND 2 OUT 3 5 VDD 4 OUT ORDERING INFORMATION Device Package Shipping† NCP51100ASNT1G SOT23−5L Tape & Reel 3000 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications • • • • • MARKING DIAGRAM M The NCP51100 2 A gate driver is designed to drive an N−Channel enhancement−mode MOSFET in low −side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with TTL input thresholds. Internal circuitry provides an under−voltage lockout function by holding the output LOW until the supply voltage is within the operating range. The NCP51100 delivers fast MOSFET switching performance, which helps maximize efficiency in high frequency power converter designs. NCP51100 drivers incorporate MillerDrivet architecture for the final output stage. This bipolar−MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn−on / turn−off process to minimize switching loss, while providing rail−to−rail voltage swing and reverse current capability. The NCP51100 is available in industry standard, 5−pin, SOT23. Switch−Mode Power Supplies High−Efficiency MOSFET Switching Synchronous Rectifier Circuits DC−to−DC Converters Motor Control This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2021 February, 2022 − Rev. P1 1 Publication Order Number: NCP51100/D NCP51100 5 VDD UVLO VDD_OK IN 1 3,4 100 kW 100 kW 2 OUT GND Figure 1. Internal Block Diagram PIN CONNECTIONS IN 1 GND 2 OUT 3 5 VDD 4 OUT Figure 2. Pin Assignments − 5−Lead SOT23 (Top View) PIN FUNCTION DESCRIPTION ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin Name Pin No. I/O/x Description IN 1 I Non−inverting Input GND 2 x Ground. Common ground reference for input and output circuits. OUT 3, 4 O Gate Drive Output. Held LOW unless required input(s) are present and VDD is above UVLO threshold. VDD 5 x Supply Voltage. Provides power to the IC. OUTPUT LOGIC NCP51100 IN OUT 0 0 1 1 No connection (Note 1) 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1. Default input signal if no external connection is made. www.onsemi.com 2 NCP51100 MAXIMUM RATINGS (Note 2) Parameter Symbol Min Max Unit −0.3 20.0 V VDD VDD to PGND VIN IN to GND GND − 0.3 VDD + 0.3 V OUT to GND GND − 0.3 VDD + 0.3 V VOUT TL Lead Soldering Temperature (10 Seconds) − +260 °C TJ Junction Temperature − +150 °C TSTG Storage Temperature −65 +150 °C Human Body Model − 3.5 kV Charge Device Model − 1 kV ESDHBM ESDCDM Electrostatic Discharge Capability (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. All voltage values are given with respect to GND pin. 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per JESD22−A114 ESD Charged Device Model tested per JESD22−C101 THERMAL CHARACTERISTICS Symbol Rating Value Unit θJA Thermal Characteristics, 5L−SOT23 (Note 4) Thermal Resistance Junction−Air (Note 5) 157 °C/W PD Power Dissipation (Note 5) 0.8 W 4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 5. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material). RECOMMENDED OPERATING CONDITIONS Symbol Parameter VDD Supply Voltage Range VIN Input Voltage VOUT OUT to GND TA Repetitive Pulse < 200 ns Operating Ambient Temperature Min Max Unit 11 18 V 0 VDD V −2.0 VDD + 0.3 V −40 +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 NCP51100 ELECTRICAL CHARACTERISTICS VCC = 12 V, for typical values TA = 25°C, for min/max values TA = −40°C to +125°C, unless otherwise specified. (Notes 7, 8) Symbol Parameter Test Conditions Min Typ Max Unit SUPPLY VDD Operating Range 11 − 18.0 V IDD Supply Current, Inputs Not Connected − 0.55 0.8 mA VON Turn−On Voltage 9 10 11 V VOFF Turn−Off Voltage 8 9 10 V VON and VOFF Hysteresis Voltage − 1 − V VDD ON Filter Debounce Time (Note 6) − 5 7 ms VHYS_ON, OFF tVDDON INPUTS VIL IN Logic LOW Threshold 0.8 1.2 − V VIH IN Logic HIGH Threshold − 1.6 2.0 V 0.2 0.4 0.8 V VIN−HYST IIN TTL Logic Hysteresis Voltage Non−Inverting Input Current IN from 0 to VDD −1 − 175 mA ISINK OUT Current, Mid−Voltage, Sinking (Note 6) OUT at VDD/2, CLOAD = 0.1 mF, f = 1 kHz − 2.5 − A ISOURCE OUT Current, Mid−Voltage, Sourcing (Note 6) OUT at VDD/2, CLOAD = 0.1 mF, f = 1 kHz − −1.8 − A IPK_SINK OUT Current, Peak, Sinking (Note 6) CLOAD = 0.1 mF, f = 1 kHz − 3 − A OUT Current, Peak, Sourcing (Note 6) CLOAD = 0.1 mF, f = 1 kHz − −3 − A tRISE Output Rise Time (Note 8) CLOAD = 1000 pF − 14 20 ns tFALL Output Fall Time (Note 8) CLOAD = 1000 pF − 7 17 ns tD1 Output Propagation Delay, TTL Inputs (Note 8) 0 to 5 VIN, 1 V/ns Slew Rate 9 10 30 ns 5 to 0 VIN, 1 V/ns Slew Rate 9 14 30 ns − 500 − mA OUTPUTS IPK_SOURCE tD2 IRVS Output Reverse Current Withstand (Note 6) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. This parameter, although guaranteed by design, is not tested in production. 7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. 8. See Timing Diagram of Figure 3. www.onsemi.com 4 NCP51100 TIMING DIAGRAMS INPUT VINH VINL tD1 tD2 tRISE 90% OUTPUT 10% Figure 3. Timing Diagram www.onsemi.com 5 tFALL NCP51100 TYPICAL PERFORMANCE CHARACTERISTICS (Typical characteristic are provide at 25°C and VDD = 12 V unless otherwise noted.) Figure 4. IDD (Static) vs. Voltage Figure 5. IDD (Static) vs. Temperature Figure 6. IDD (No Load) vs. Frequency Figure 7. IDD (1 nF Load) vs. Frequency Figure 8. Input Threshold vs. Supply Voltage Figure 9. Input Thresholds vs. Temperature www.onsemi.com 6 NCP51100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristic are provide at 25°C and VDD = 12 V unless otherwise noted.) Figure 10. UVLO Threshold vs. Temperature Figure 11. UVLO Hysterisis vs. Temperature Figure 12. Propagation Delay vs. Supply Voltage Figure 13. Propagation Delay vs. Temperature Figure 15. Rise Time vs. Supply Voltage Figure 14. Fall Time vs. Supply Voltage www.onsemi.com 7 NCP51100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristic are provide at 25°C and VDD = 12 V unless otherwise noted.) Figure 16. Rise and Fall Time vs. Temperature Figure 18. Rise / Fall Waveforms with 10 nF Load Figure 17. Rise / Fall Waveforms with 1 nF Load Figure 20. Quasi−Static Sink Current with VDD = 12 V Figure 19. Quasi−Static Source Current with VDD = 12 V www.onsemi.com 8 NCP51100 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristic are provide at 25°C and VDD = 12 V unless otherwise noted.) Figure 22. Quasi−Static Sink Current with VDD = 10 V Figure 21. Quasi−Static Source Current with VDD = 10 V VDD 4.7 mF ceramic Al. El. Current Probe LECROY AP015 IOUT IN 1 kHz 1 mF ceramic VOUT CLOAD 0.1 mF Figure 23. IDD (1 nF Load) vs. Frequency www.onsemi.com 9 NCP51100 APPLICATION INFORMATION VDD Input Thresholds The NCP51100 offers TTL input thresholds which meet industry−standard TTL logic thresholds, independent of the VDD voltage and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6 V/ms or faster, so a rise time from 0 V to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. Input stage VOUT Figure 24. MillerDrivet Output Architecture Under−Voltage Lockout The NCP51100 start−up logic is optimized to drive ground referenced N−channel MOSFETs with a under−voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 10 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 1 V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high−side P−channel MOSFETs because the low output voltage of the driver would turn the P−channel MOSFET on with VDD below 10 V. Static Supply Current In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. In the IDD (static) typical performance characteristics shown in Figure 4 and Figure 5, each curve is produced with both inputs floating and both outputs LOW to indicate the lowest static IDD current. For other states, additional current flows through the 100 kW resistors on the inputs and outputs shown in the block diagram of each part (see Figure 1). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDrivet Gate Drive Technology NCP51100 drivers incorporate the MillerDrive architecture shown in Figure 24 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive architecture is to speed up switching by providing the highest current during the Miller plateau region when the gate−drain capacitance of the MOSFET is being charged or discharged as part of the turn−on / turn−off process. For applications that have zero voltage switching during the MOSFET turn−on or turn−off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slower rise or fall time at the MOSFET gate is needed, a series resistor can be added. VDD Bypass Capacitor Guidelines To enable this IC to turn a power device on quickly, a local, high−frequency, bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 mF to 47 mF often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply ≤5%. Often this is achieved with a value ≥20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. Ceramic capacitors of 0.1 mF to 1 mF or larger are common choices, as are dielectrics, such as X5R and X7R, which have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50−100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1−10 nF, mounted closest to the VDD and GND pins to carry the higher−frequency components of the current pulses. www.onsemi.com 10 NCP51100 Layout and Connection Guidelines VDD The NCP51100 incorporates fast−reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10 ns to over 100 ns. The following layout and connection guidelines are strongly recommended: • Keep high−current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical when dealing with TTL−level logic thresholds. • Keep the driver as close to the load as possible to minimize the length of high−current traces. This reduces the series inductance to improve high−speed switching, while reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry. • Many high−speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output re−triggering. These effects can be especially obvious if the circuit is tested in breadboard or non−optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. • The turn−on and turn−off current paths should be minimized as discussed in the following sections. Figure 25 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driver−MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD VDS CBYP NCP51100 PWM Figure 26. Current Path for MOSFET Turn−Off Operational Waveforms At power up, the driver output remains LOW until the VDD voltage reaches the turn−on threshold. The magnitude of the OUT pulses rises with VDD until steady−state VDD is reached. The non−inverting operation illustrated in Figure 27 shows that the output remains LOW until the UVLO threshold is reached, then the output is in−phase with the input. VDD Turn−on threshold IN OUT Figure 27. Start−Up Waveforms VDS Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of three components; PGATE, PQUIESCENT, and PDYNAMIC: CBYP NCP51100 PWM Figure 25. Current Path for MOSFET Turn−On P total + P gate ) P Dynamic (eq. 1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gate−source voltage, VGS, with Figure 26 shows the current path when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn−off times, the resistance and inductance in this path should be minimized. www.onsemi.com 11 NCP51100 gate charge, QG, at switching frequency, fSW, is determined by: P GATE + Q G @ V GS @ f SW The power dissipated in a gate−drive circuit is independent of the drive−circuit resistance and is split proportionately among the resistances present in the driver, any discrete series resistor present, and the gate resistance internal to the power switching MOSFET. Power dissipated in the driver may be estimated using the following equation: (eq. 2) Dynamic Pre−drive / Shoot−through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull−up / pull−down resistors, can be obtained using the graphs in Figure 6 and Figure 7 in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: P DYNAMIC + I DYNAMIC @ V DD P PKG + P TOTAL where TJ qJL TL R OUT, Driver R OUT, DRIVER ) R EXT ) R GATE, FET Ǔ (eq. 5) where PPKG (eq. 3) Once the power dissipated in the driver is determined, the driver junction temperature rise with respect to the device lead can be evaluated using thermal equation: T J + P TOTAL Q JL ) T C ǒ = power dissipated in the driver package; ROUT, DRIVER = estimated driver impedance derived from IOUT vs. VOUT waveforms; REXT = external series resistance connected between the driver output and the gate of the MOSFET; and RGATE, FET = resistance internal to the load MOSFET gate and source connections (eq. 4) = driver junction temperature; = thermal resistance from junction to lead; and = lead temperature of device in application www.onsemi.com 12 NCP51100 TYPICAL APPLICATION DIAGRAMS NCP51100 NCP51100 Figure 28. PFC Boost Circuit Utilizing Distributed Drivers for Parallel Power Switches Q1A and Q1B NCP51100 Figure 29. Driver for Forward Converter Low−Side Switch NCP51100 Figure 30. Driver for Two−Transistor, Forward−Converter Gate Transformer www.onsemi.com 13 NCP51100 PACKAGE DIMENSIONS SOT−23, 5 Lead CASE 527AH−01 ISSUE O D E1 SYMBOL MIN A 0.90 1.45 A1 0.00 0.15 A2 0.90 b 0.30 0.50 c 0.08 0.22 E 1.15 D 2.90 BSC E 2.80 BSC E1 1.60 BSC e 0.95 BSC e L PIN #1 IDENTIFICATION NOM 0.45 0.30 L1 0.60 REF L2 0.25 REF MAX 1.30 0.60 θ 0° 4° 8° θ1 5° 10° 15° θ2 5° 10° 15° TOP VIEW θ1 A2 A θ b θ2 L1 A1 SIDE VIEW L2 L c END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. 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