NCP5359
Gate Driver for Notebook
Power Systems
The NCP5359 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Each of the drivers can
drive up to 3 nF load with a 25 ns propagation delay and 20 ns
transition time.
Adaptive nonoverlap and power saving operation circuit can
provide a low switching loss and high efficiency solution for notebook
and desktop systems.
A high floating top driver design can accommodate VBST voltage
as high as 35 V, with transient voltages as high as 35 V. Bidirectional
EN pin can provide a fault signal to controller when the gate driver
fault detect under OVP, UVLO occur. Also, an undervoltage lockout
function guarantees the outputs are low when supply voltage is low,
and a thermal shutdown function provides the IC with
overtemperature protection.
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
Faster Rise and Fall Times
Thermal Shutdown Protection
Adaptive Nonoverlap Circuit
Floating Top Driver Accommodates Boost Voltages of up to 35 V
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 11.1 Specifications
Undervoltage Lockout
Power Saving Operation Under Light Load Conditions
Thermally Enhanced Package
These are Pb−Free Devices
Typical Applications
N5359
ALYW
G
DFN−10
MN SUFFIX
CASE 485C
Features
•
•
•
•
•
•
•
•
•
•
1
A
L
Y
W
G
N5359
ALYW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
BST
1
8
DRVH
PWM
EN
SW
GND
VCC
DRVL
• Power Solutions for Desktop and Notebook Systems
1
10
BST
PWM
DRVH
SW
EN
VCC
VCC
GND
GND
DRVL
(Top View)
ORDERING INFORMATION
Package
Shipping†
NCP5359DR2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
NCP5359MNR2G
DFN−10
(Pb−Free)
3000 Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. 3
1
Publication Order Number:
NCP5359/D
NCP5359
BST
VCC
ChipEN
DRVH
Level Shift
and
Driver
Falling Edge Delay
DRVH Comparator
PWM > 2.2 V = 1, Else = 0
PWM
+
−
Fault
EN
+
1.0 V
UVLO
Fault
SW
ChipEN
Thermal Shutdown
FPWM Comparator
0.8 V < PWM < 2.2 V = 1,
Else 0
+
−
SW
1 mV
GND
+
EN
Pre −Over voltage
Pre−OV
2 V/1 V
R
S
Q
Q
l
GND
+
+
−
Falling Edge Delay
l
l
ChipEN
VCC
DRVL
Driver
Pre−OV
Figure 1. Internal Block Diagram
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2
NCP5359
4 V to 15 V
*Option
DRVH
BST
PWM
EN
10 V to 13.2 V
VOUT
SW
PWM
EN
GND
VCC
GND
VCC
DRVL
Figure 2. Typical Application
PIN DESCRIPTION
SOIC−8
DFN10
Symbol
Description
1
1
BST
Upper MOSFET Floating Bootstrap Supply Pin
2
2
PWM
PWM Input Pin
When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0
When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0
When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1
When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0
3
3
EN
Enable Pin
When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low
4
4, 5
VCC
Connect to Input Power Supply 10 V to 13.2 V
5
6
DRVL
Low Side Gate Drive Output
6
7, 8
GND
Ground Pin
7
9
SW
8
10
DRVH
Switch Node Pin
High Side Gate Drive Output
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3
NCP5359
MAXIMUM RATINGS
Rating
Symbol
Thermal Characteristics, Plastic Package
Thermal Resistance Junction−to−Air
SOIC−8
DFN10
Value
RqJA
Unit
°C/W
178
45
Operating Junction Temperature Range
TJ
0 to +150
°C
Operating Ambient Temperature Range
TA
0 to +85
°C
Tstg
− 55 to +150
°C
MSL
3
1
−
Storage Temperature Range
Moisture Sensitivity Level
SOIC−8
DFN10
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
MAXIMUM RATINGS
Pin Symbol
Pin Name
VMAX
VMIN
Vcc
Main Supply Voltage Input
15 V
−0.3 V
BST
Bootstrap Supply voltage
35 V wrt / GND
40 V ≤ 50 ns wrt / GND
15V wrt / SW
−0.3 V
SW
Switching Node
(Bootstrap Supply Return)
35 V wrt / GND
40 V ≤ 50 ns wrt / GND
−1 VDC
−10 V (200 ns) (Note 4)
DRVH
High Side Driver Output
BST + 0.3 V
35 V ≤ 50 ns wrt / GND
15V wrt / SW
−0.3 V
−2 V (200 ns)
DRVL
Low Side Driver Output
Vcc + 0.3 V
−0.3 V
−5 V (200 ns)
PWM
DRVH and DRVL Control Input
6V
−0.3 V
EN
Enable Pin
6V
−0.3 V
GND
Ground
0V
0V
1. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78.
2. Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J−STD−020A.
3. The maximum package power dissipation limit must not be exceeded.
PD +
TJ(max) * TA
RqJA
4. Switching node negative voltage is −5 V ( 200 ns) at PSI mode.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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4
NCP5359
ELECTRICAL CHARACTERISTICS (VCC = 12 V, TA = 0°C to +85°C, VEN = 5 V unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Units
13.2
V
Supply Voltage
VCC Operating Voltage
VCC
Power ON Reset threshold
VPOR
10
2.8
V
Supply Current
VCC Quiescent Supply Current in
Normal Operation
VCC Standby Current
BST Quiescent Supply Current in
Normal Operation
BST Standby Current
IVCC_NORM
EN = 5 V, PWM = OSC, FSW = 100 k
CLOAD = 0 p
2.0
5.0
mA
EN = GND; No switching
0.5
1.0
mA
IBST1_normal
PWM = +5 V, SW = 0 V
1.0
1.8
mA
IBST2_normal
PWM = GND, SW = 0 V
1.0
1.8
IBST1_SD
PWM = +5 V
0.25
IBST2_SD
PWM = GND
0.25
IVCC_SBC
mA
Undervoltage Lockout
VCC Start Threshold
VCCTH
VCC UVLO Hysteresis
VCCHYS
Output Overvoltage Trip Threshold at
Startup
OVPSU
8.2
8.7
9.5
1.0
Power Startup time, VCC > 9 V.
(Without trimming)
1.8
V
V
2.0
V
EN Input
Input Voltage High
VEN_HI
Input Voltage Low
VEN_LOW
Hysteresis (Note 5)
VEN_HYS
Enable Pin Sink Current
IEN_SINK
Propagation Delay Time (Note 5)
2.0
V
1.0
500
VCC = 5.5 V
V
mV
5.0
mA
tpdhEN
20
60
ns
tpdlEN
20
60
ns
PWM Input
DRVH Comparator Drop Threshold
PWM Input Self Bias Voltage
DRVL Comparator Rise Threshold
Input Current
VTH_DRVH
2.2
VPWM
1.4
V
1.5
VTH_DRVL
IPWM
1.6
0.8
PWM = 0 V, EN = GND
30
V
V
mA
High Side Driver
Output Resistance, Sourcing
RH_TG
VBST – VSW = 12 V
2.0
3.5
Output Resistance, Sinking
RL_TG
VBST – VSW = 12 V
1.0
2.5
W
Transition Time (Note 7)
trDRVH
CLOAD = 3 nF, VBST – VSW = 12 V
16
25
ns
tfDRVH
CLOAD = 3 nF, VBST – VSW = 12 V
11
15
Propagation Delay (Notes 5 & 6)
tpdhDRVH
Driving High, CLOAD = 3 nF
10
35
tpdlDRVH
Driving Low, CLOAD = 3 nF
8.0
30
W
ns
Low Side Driver
Output Resistance, Sourcing
RH_BG
SW = GND
2.0
3.5
Output Resistance, Sinking
RL_BG
SW = VCC
1.0
2.5
W
Transition Time (Note 7)
trDRVL
CLOAD = 3 nF
16
25
ns
tfDRVL
CLOAD = 3 nF
11
15
Propagation Delay (Notes 5 & 6)
Negative Current Detector Threshold
tpdhDRVL
Driving High, CLOAD = 3 nF
10
35
tpdlDRVL
Driving Low, CLOAD = 3 nF
8.0
30
VNCDT
(Note 7)
Tsd
(Note 7)
Tsdhys
(Note 7)
W
ns
−1.0
mV
170
°C
20
°C
Thermal Shutdown
Thermal Shutdown
Thermal Shutdown Hysteresis
150
5. Guaranteed by design; not tested in production .
6. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low.
7. Design guaranteed.
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5
NCP5359
Table 1. DECODER TRUTH TABLE
PWM Input
ZCD
Greater than 2.2 V
DRVL
DRVH
X
Low
High
Greater than 0.8 V, but less than 2.2 V
High (current through MOSFET is greater than 0)
High
Low
Greater than 0.8 V, but less than 2.2 V
Low (current through MOSFET is less than 0)
Low
Low
X
High
Low
Less than 0.8 V
IN
tpdlDRVL
DRVL
tfDRVL
90%
90%
2V
10%
10%
tpdhDRVH
DRVH−SW
tpdlDRVH
trDRVH
90%
10%
trDRVL
tfDRVH
90%
2V
10%
tpdhDRVL
SW
Figure 3.
PWM
DRVH−SW
DRVL
IL
Figure 4. Timing Diagram
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6
NCP5359
APPLICATION INFORMATION
Power ON reset
The NCP5359 gate driver is a single phase MOSFET
driver designed for driving two N−channel MOSFETs in a
synchronous buck converter topology. This driver is
compatible with the NCP3418B gate drive. This gate drives
operation is similar with the NCP3418B, but has two
additional new features: Bidirection fault detection and
multilevel PWM input. When the gate driver works with
ON Semiconductor’s NCP5392 controller, it can provide a
difference output logic status through multi−level PWM
input. For this new feature, higher efficiency can be
provided. For the bidirection fault detection function, it is
used to provide a driver state information to other gate
drivers and controller in a multiphase buck converter. e.g
overvoltage protection (OVP) function at startup, thermal
shutdown and undervoltage lockout (UVLO). This feature
can provide an additional protection function for the
multi−phase system when the fault condition occurs in one
channel. With this additional feature, converter overall
system will be more reliable and safe.
Power on reset feature is used to protect a gate driver avoid
abnormal status driving the startup condition. When the
initial soft−start voltage is higher than 3.2 V, the gate driver
will monitor the switching node SW pin. If SW pin high than
1.9 V, bottom gate will be force to high for discharge the
output capacitor. The fault mode will be latch and EN pin
will force to be low, unless the driver is recycle. When input
voltage is higher than 9 V, the gate driver will normal
operation, top gate driver DRVH and bottom gate driver will
follow the PWM signal decode to a status.
Adaptive Nonoverlap
The nonoverlap dead time control is used to avoid the
shoot through damage the power MOSFETs. When the
PWM signal pull high, DRVL will go low after a
propagation delay, the controller will monitors the switching
node (SWN) pin voltage and the gate voltage of the
MOSFET to know the status of the MOSFET. When the low
side MOSFET status is off an internal timer will delay turn
on of the high–side MOSFET. When the PWM pull low, gate
DRVH will go low after the propagation delay (tpd DRVH).
The time to turn off the high side MOSFET is depending on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high side MOSFET is turn off to delay
the turn on the low−side MOSFET.
Enable Pin
The bidirection enable pin is connected with an open drain
MOSFET. This pin is controlled by internal or external
signal. There are three conditions will be triggered:
1. The voltage at SWN pin is higher than preset
voltage at power startup.
2. The controller hits the UVLO at VCC pin.
3. The controller hits the thermal shutdown.
When the internal fault has been detected, EN pin will be
pull low. In this case, the drive output DRVH and DRVL will
be forced low, until the fault mode remove then restart
automatic.
Layout Guidelines
Layout is very important thing for design a DC−DC
converter. Bootstrap capacitor and VCC capacitor are most
critical items, it should be placed as close as to the driver IC.
Another item is using a GND plane. Ground plane can
provide a good return path for gate drives for reducing the
ground noise. Therefore GND pin should be directly
connected to the ground plane and close to the low−side
MOSFET source pin. Also, the gate drive trace should be
considered. The gate drives has a high di/dt when switching,
therefore a minimized gate drives trace can reduce the di/dv,
raise and fall time for reduce the switching loss.
Undervoltage Lockout
The DRVH and DRVL are held low until VCC reaches 9 V
during startup. The PWM signals will control the gate status
when VCC threshold is exceeded. If VCC decreases to 3.2 V
below the threshold, the output gate will be forced low until
input voltage VCC rises above the startup threshold.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE F
SCALE 2:1
DATE 16 DEC 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
*This information is generic. Please refer to
Y
= Year
device data sheet for actual part marking.
W
= Work Week
Pb−Free indicator, “G” or microdot “G”, may
G
= Pb−Free Package
or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03161D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN10, 3X3 MM, 0.5 MM PITCH
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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