NCP5604A

NCP5604A, NCP5604B High Efficiency White LED Driver The NCP5604A and NCP5604B products are multiple output LED drivers dedicated to the display back light. The NCP5604A drives up to 4 LEDs, the NCP5604B version being dedicated to the three LED applications. The two parts share a common built−in DC/DC converter, based on a charge pump structure, including the new 1.33X mode of operation, improving the efficiency over the full input battery supply voltage span over 90%. Features http://onsemi.com MARKING DIAGRAM C3N C2N C3P Typical Applications • Portable Back Light • Digital Cellular Phone Camera Photo Flash • LCD and Key Board Simultaneously Drive 16 Vbat 1 EN 2 IREF 3 AGND 4 5 LED4/NC* 15 14 13 12 VOUT 11 C1P 10 C1N 9 PGND 6 LED3 7 LED2 * Pin 5 in not connected in the NCP5604B (Top View) ORDERING INFORMATION Device NCP5604AMTR2G Package Shipping† WQFN16 3000/T ape & Reel (Pb−Free) WQFN16 3000/T ape & Reel (Pb−Free) NCP5604BMTR2G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 1 March, 2006 − Rev. 0 Publication Order Number: NCP5604/D LED1 C2P • • • • • • • • • • • 2.7 to 5.5 V Input Voltage Range Consistent 85% Efficiency 1.0 mA Quiescent Supply Current All Pins are Fully ESD Protected Built−in Short Circuit Protection Provides Four Independent LED Drives 200 kHz Digital Dimming Function Unloaded LED Protection Short Circuit Current Proof Tight 0.5% LED Current Matching These are Pb−Free Devices 1 WQFN16 (3x3) MT SUFFIX CASE 488AK NCPx5604 = Specific Device Code x = A or B A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS ÇÇ ÇÇ 1 8 16 NCPx 5604 ALYWG G NCP5604A, NCP5604B Vbat 220 nF/10 V C3 16 15 C4 GND 4.7 mF/6.3 V 1 VBAT C3N C3P CONTROL R1 100 k GND 2 3 EN IREF C2P C1N U1 NCP5604A C1P 13 11 C1 10 12 LWY87S D4 D3 D2 D1 LWY87S LWY87S LWY87S GND Figure 1. Typical Multiple White LED Driver http://onsemi.com 2 1 mF/10 V LED4 LED3 LED2 LED1 4 AGND 9 PGND VOUT 220 nF/10 V 220 nF/10 V C2N 14 C2 5 6 7 8 C5 NCP5604A, NCP5604B C3 220 nF 16 15 14 C2 220 nF 13 11 C1 220 nF 10 C5 GND 1 mF/10 V Vbat C4 GND 4.7 mF/10 V 1 CHARGE PUMP DC−DC CONVERTER 12 Vout LWY87S LWY87S LWY87S OVERVOLTAGE EN 2 DIGITAL CONTROL Vbat D1 D2 D3 D4 Q1 8 GND 100 k AGND 3 ANALOG CONTROL 4 CURRENT CONTROL R1 Q2 7 Q3 6 Q4 OVERTEMPERATURE 5 9 PGND Figure 2. NCP5604A Simplified Block Diagram http://onsemi.com 3 LWY87S NCP5604A, NCP5604B C3 220 nF 16 15 14 C2 220 nF 13 11 C1 220 nF 10 C5 GND 1 mF/10 V Vbat C4 GND 4.7 mF/10 V 1 CHARGE PUMP DC−DC CONVERTER 12 Vout LWY87S LWY87S OVERVOLTAGE EN 2 DIGITAL CONTROL Vbat D1 D2 D3 Q1 8 GND 100 k AGND 3 ANALOG CONTROL 4 CURRENT CONTROL R1 Q2 7 Q3 6 OVERTEMPERATURE NC 5 9 PGND Figure 3. NCP5604B Simplified Block Diagram (Pin 5 disconnected) http://onsemi.com 4 LWY87S NCP5604A, NCP5604B PIN FUNCTION DESCRIPTION Pin 1 2 Symbol VBAT EN Type INPUT, POWER INPUT, DIGITAL Description Input Battery voltage to supply the analog and digital blocks. The pin must be decoupled to ground by a 1.0 mF ceramic capacitor. This pin carries the Enable function to control the DC−DC converter. It can be used to digitally dim the LED by using a PWM technique. EN = Low ³ shutdown mode, the DC−DC is disconnected from the load. EN = High ³ operating mode, the DC−DC is activated. The digital PWM dimming can operate over the 100 Hz − 200 kHz frequency, depending upon the application requirements. This pin provides the reference current, based on the internal bandgap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED. In no case shall the voltage at pin 3 be forced either higher or lower than the 600 mV provided by the internal reference. 4 5 AGND LED4 POWER INPUT, POWER This pin is the GROUND signal for the analog and digital blocks and must be connected to the system ground. NCP5604A: This pin sinks to ground and monitors the current flowing into the fourth LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). NCP5604B: This pin is not connected. This pin sinks to ground and monitors the current flowing into the third LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). This pin sinks to ground and monitors the current flowing into the second LED, intended to be used in backlight application. The current is limited to 25mA maximum (Note 2). This pin sinks to ground and monitors the current flowing into the first LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). This pin is the GROUND reference for the DC−DC converter and the output current control. The pin must be connected to the system ground, a ground plane being strongly recommended. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N, pin 11 (Note 1). One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P, pin 10 (Note 1). This pin provides the output voltage supplied by the DC−DC converter. The Vout pin must be bypassed by 1.0 mF ceramic capacitor located as close as possible to the pin to properly bypass the output voltage to ground. The circuit shall not operate without such bypass capacitor properly connected to the Vout pin. The output voltage is internally clamped to 5.5 V in the event of no load situation. On the other hand, the output current is limited to 100 mA in the event of a short circuit to ground. 13 14 15 16 C2P C2N C3P C3N POWER POWER POWER POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2N, pin 14 (Note 1). One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P, pin 13 (Note 1). One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C3N, pin 16 (Note 1). One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C3P, pin 15 (Note 1). 3 IREF INPUT, ANALOG 6 7 8 9 LED3 LED2 LED1 PGND INPUT, POWER INPUT, POWER INPUT, POWER POWER 10 11 12 C1P C1N VOUT POWER POWER OUTPUT, POWER 1. Using low ESR 1.0 mF ceramic capacitor is mandatory to optimize the Charge Pump efficiency. The DC Bias effect must be taken into account when selecting the ceramic capacitor. Smallest foot print packages (size 0602 and lower) are prone to strong DC bias effect, reducing the real capacitance significantly. 2. Total DC−DC output current is limited to 100 mA. 3. The exposed flag shall be connected to ground. http://onsemi.com 5 NCP5604A, NCP5604B MAXIMUM RATINGS Rating Power Supply Output Power Supply Digital Input Voltage Digital Input Current Human Body Model: R = 1500 W, C = 100 pF (Note 4) Machine Model QFN16 Package Power Dissipation @ TA = +85°C (Note 5) Thermal Resistance, Junction−to−Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Moisture Sensitivity Level (Note 7) Symbol VBAT Vout EN ESD Value 7.0 7.0 −0.3 < V < VBAT 1.0 2 200 320 125 −40 to +85 −40 to +125 +150 −65 to +150 1 Unit V V V mA kV V mW °C/W °C °C °C °C PD RqJA TA TJ TJmax Tstg MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM): JESD22−A114. Machine Model (MM): JESD22−A115. 5. The maximum package power dissipation limit must not be exceeded. 6. Latchup current maximum rating: " 100 mA per JEDEC standard: JESD78. 7. Moisture Sensitivity Level (MSL): per IPC/JEDEC standard: J−STD−020A. http://onsemi.com 6 NCP5604A, NCP5604B POWER SUPPLY SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Pin 1 12 12 12 12 1 Symbol Vbat Iout Isch Vout Tstart Istdb Power Supply Continuous DC Current in the Load (Note 8) @ Vf = 3.2 V, 3.3 V < Vbat < 5.5 V (Total Iout = 4*LED) Continuous Output Short Circuit Current Output Voltage Compliance (OVP) DC−DC Start Time (Cout = 1.0 mF) − from Vout = 0 V to full load operation, @ Vbat = nominal Standby Current, @ Iout = 0 mA, EN = GND Vbat = 3.6 V Vbat = 4.2 V Operating Current, @Iout = 0 mA, EN = H 2.85 V < Vbat < 5.5 V Vbat = 3.6 V Output LED to LED Current Matching, @ Vbat = 3.6 V, ILED = 20 mA, LED1 to LED4 are identical (Note 9) Output Current Tolerance (Note 9) @ 3.2 V < Vbat < 4.2 V, ILED = 20 mA Charge Pump Operating Frequency −25°C < TA < 85°C Thermal Shutdown Protection Thermal Shutdown Protection Hysteresis Efficiency (Note 9) LED1 to LED4 = 5.0 mA, Vf = 2.95 V (Total = 20 mA), Vbat = 3.2 V LED1 to LED4 = 25 mA, Vf = 3.3 V (Total = 100 mA), Vbat = 3.8 V Rating Min 2.7 100 − 4.8 − − − − − −2.0 −5.0 0.85 − − − − Typ − − 40 − 100 0.3 0.4 1.0 − "0.2 "1.0 1.0 160 30 87 85 Max 5.5 − 150 6.0 − 3.0 5.0 mA − 1.5 % +2.0 % +5.0 1.15 − − − − MHz °C °C % Unit V mA mA V ms mA 1 Iop 5, 6, 7, 8 5, 6, 7, 8 − − − − IMAT ITOL Fpwr TSD TSDH EPWR 8. The total output current is evenly distributed across the external LED. 9. LED4 is not connected in the NCP5604B version. 10. The NCP5604B controls 75 mA in total in the three current mirrors, the extra 25 mA available current from the DC−DC converter being available for external purpose. http://onsemi.com 7 NCP5604A, NCP5604B ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Pin 3 3 − Symbol IREF VREF ILEDR Rating Reference Current @ Vref = 600 mV (Note 11) Reference Voltage (Note 12) Reference Current (IREF) to Output LED Current Ratio Min 1.0 −2% − Typ − 600 260 Max 100 +2% − Unit mA mV − 11. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. 12. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified. DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Note: Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT. Pin 2 2 2 Symbol FPWM VIH VIL Input Enable PWM Positive Going Input High Voltage Threshold, EN Signal Negative Going Input High Voltage Threshold, EN Signal Rating Min 0.1 1.3 0 Typ − − − Max 200 VBAT 0.4 Unit kHz V V APPLICATIONS INFORMATION DC−DC OPERATION The converter is based on a charge pump technique to generate a DC voltage capable to supply the White LED load The system regulates the current flowing into each LED by means of internal current mirrors associated with the white diodes. Consequently, the output voltage will be equal to the Vf of the LED, plus the 300 mV (typical) developed across the internal NMOS mirror. Typically, assuming a standard white LED forward biased at 10 mA, the output voltage will be 3.8 V. The third external capacitor makes possible the 1.33X extra mode of operation, with a significant efficiency improvement of the converter over the normal battery voltage span. The threshold levels have been defined to optimize this range of operating voltage, assuming a high efficiency is not relevant when the system is connected to a battery charger ( i.e. Vbat > 4.5 V). The built−in OVP circuit continuously monitor each output and stops the converter when the voltage is above 5.0 V. The converter resumes to normal operation when the voltage drops below 5.0 V (no latch−up mechanism). Consequently, the chip can operate with no load during any test procedures, but in the case of special applications, it is recommended to connect the non used LED driver either to a LED, or to the Vbat supply to minimize the internal losses (see LOAD CONNECTION paragraph). LOAD CURRENT CALCULATION The load current is derived from the 600 mV reference voltage provided by the internal Band Gap associated to the external resistor connected across IREF pin and Ground (see Figure 4). In any case, no voltage shall be forced at IREF pin, either downward or upward. The reference current is multiplied by the constant k = 260 to yield the output load current. Since the reference voltage is based on a temperature compensated Band Gap structure, a tight tolerance resistor will provide a very accurate load current. The resistor is calculated from the Ohm’s law (Rbias = Vref/I REF) and a more practical equation can be arranged to define the resistor value for a given output current: Rbias + (Vref * k) Iout Rbias + (0.6 * 260) Iout Rbias + 156 Iout (eq. 1) (eq. 2) Consequently, the resistor value will range between Rbias = 156/25 mA = 6240 W and Rbias = 156/0.5 mA = 312 kW. Obviously, the tolerance of such a resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. VBandGap LED Return + − IREF Pin 3 GND Note: The IREF pin must never be biased to voltage higher than 600 mV. 600mV Pin 5 to 8 GND Figure 4. Basic Reference Current Source http://onsemi.com 8 NCP5604A, NCP5604B Iout drift versus Vbat 5 4 3 Iout drift (%) 2 1 0 Iout = 28mA Iout = 80mA LOAD CONNECTION The NCP5604A chip is capable of driving the four LED simultaneously, as depicted in Figure 1, but the load can be arranged to accommodate one or two LED if necessary in the application (see Figure 8). The four current mirror can be connected in parallel to drive a single powerful LED, thus yielding 100 mA current capability in a single LED. −1 −2 −3 LWY87S −4 NCP5604 −5 2.5 3.0 3.5 4.0 Vbat(V) 4.5 5.0 5.5 D1 1 mF/6.3 V C5 12 Figure 5. Typical IOUT Tolerance as a Function of the VBAT Supply Iref = 5 mA 8 7 GND 3 Iout Current Matching (%) 6 5 −405C 2 255C 855C 12 LWY87S D1 NCP5604 0 2.5 8 7 6 5 GND 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Figure 6. Typical LED to LED Current Matching at Low IREF Iref = 100 mA −405C 255C 2 855C 3 Iout Current Matching (%) Figure 8. Typical Single and Double LED Connections The applications using three LED shall use the NCP5604B version to make profit of the highest efficiency (see Figure 9). In this case, LED4 is not connected and pin 5 is internally unconnected. 1 0 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Figure 7. Typical LED to LED Current Matching at IREF Maximum http://onsemi.com 9 D2 C5 1 LWY87S 1 mF/6.3 V NCP5604A, NCP5604B Vbat C4 GND 4.7uF/6.3V CONTROL 220 nF/10 V 16 15 Input PWM Signal Frequency: 100 Hz to 200 kHz C1P C1N LED3 LED2 LED1 1 VBAT C2P C3 VBAT EN C3N C3P 1 2 C2N 14 R1 100k 3 4 9 GND LED3 LED2 LED1 PGND NC C1N VOUT 10 12 1uF/10V 6.8 k U1 C2P IREF NCP5604B C1P AGND 13 11 C2 220 nF/10 V PWM 2 3 R1 EN IREF C2N C3P C1 220 nF/10 V C3N GND VOUT 4 9 AGND PGND LED4 D1 C5 D2 D3 LWY87S 5 6 7 8 LWY87S GND GND LWY87S Figure 9. Using the NCP5604B to Drive a Three LED Layout Figure 11. Basic Digital PWM Dimming Control Finally, an external network can be connected across Vout and ground, but the current through such network will not be regulated by the NCP5604A chip (see Figure 10). On top of that, the total current out of the Vout pin shall be limited to 100 mA. GND C5 1 mF/6.3 V LWY87S LWY87S LWY87S LWY87S 5 mA LWY87S 5 mA LWY87S The PWM frequency can be up to 200 kHz once the circuit has been properly started. On the other hand, with a 1% to 99% span, the circuit supports a large Duty Cycle to accommodate any range of dimming. The waveforms given in Figure 12 illustrate the NCP5604A behavior during the 50 kHz PWM operation. The same mechanism applies for the NCP5604B version. 12 NCP5604 D1 D2 D3 D4 D5 8 220R R2 GND 7 6 5 220R R1 Figure 10. Extra Load Connected to Vout D6 DIMMING The dimming can be achieved by two means: • Use a digital PWM signal to control the EN pin • Use an analog signal to control the reference current IREF pin. The digital PWM is straightforward, yielding a zero to 100% duty cycle, but the output current is pulsed since the system is continuously switched ON/OFF. There is no need for extra passive component, the clock being provided by an I/O port from the MCU (see Figure 11). Figure 12. PWM Modulation Span: 1% to 99% Besides the popular PWM mode, a simple analog technique can be built with two extra components (one resistor + one NMOS), the net advantage being a continuous output current once the operating point has been stabilized (see Figure 13). The absolute output current tolerance depends upon the precision of the two external resistors, the RDS(on) of the NMOS being negligible in front of the resistor value. The example given, Figure 13 yields a 1.0 mA output current when Q1 is OFF, http://onsemi.com 10 NCP5604A, NCP5604B and 23 mA when Q1 is ON. The concept can use either a DC drive or a pulsed mode to dynamically dim the light out of the LED. A different analog approach, but more complex solution, can be derived from either a DC or a pulsed voltage associated with a current mirror built with low cost discrete devices (see Figure 14). The associated filter (R2/R3/C1) provides a continuous voltage to the current mirror, thus a digitally controlled continuous output current. Generally speaking, the PWM frequency could be either in the low end 20 Hz to 200 Hz band, or above the audio band (25 kHz and beyond) to make sure the dimming can be adjusted from zero to 100% without any audible noise. As a matter of fact, the NCP5604A has been designed to guarantee 200 kHz PWM at the ENABLE pin. The current mirror can be largely improved by using an external operational amplifier to get a very stable and temperature independent current, but such a solution could turn out to be too expensive and, generally speaking, the basic structure given, Figure 13, gives good results since the current depends mostly upon the quality of resistor R2. C1P C1N LED3 LED2 7 8 LED1 1 VBAT C2P ENABLE 2 3 EN IREF C2N C3P 150 k 6.8 k R2 R1 C3N VOUT 4 9 AGND PGND LED4 Q1 High Out 5 GND C1P C1N 1 VBAT C2P 2 3 EN IREF C2N C3P C3N VOUT 4 9 AGND LED4 LED3 LED2 PGND LED1 GND 5 6 7 8 Figure 13. Basic Analog Dimming Control ENABLE V = 3.3 V R1 PWM 12 k 10 nF C1 R2 BC846BDW 15 k Q1A Q1B GND GND Figure 14. Basic Analog PWM Dimming Control http://onsemi.com 11 6 NCP5604A, NCP5604B Figure 15. Startup Operation Figure 17. Input Current Short Circuit Operation EFFPLED (%) SHORT CIRCUIT OPERATION The circuit is designed to support a short circuit across Vout and Ground without damage. When a short occurs, the pulsed output current increases to the maximum peak value until the output voltage drops below 1 V. At this point, the pulsed current is limited to 40 mA average (typical), until the short is removed. The waveforms given in Figure 16 illustrate the functional operation. Similarly, the input current is limited 300 mA peak (typical) as depicted in Figure 17. Iout=100 mA 90 85 80 75 70 65 60 55 50 4.2 Iout=80 mA Iout=60 mA Iout=40 mA Iout=20 mA 4.0 3.8 Vbat(V) 3.6 3.4 3.2 Figure 18. Typical Efficiency Figure 16. Output Short Circuit Operation http://onsemi.com 12 NCP5604A, NCP5604B TP2 LWY87S VOUT LWY87S 220 nF/10 V 14 13 C2 220 nF/10 V 10 12 C1 C4 GND 4.7 mF/10 V D4 LWY87S D2 D1 11 220 nF/10 V VOUT C3P U1 NCP5604 C3N AGND VBAT IREF EN LED2 LED3 LED4 PGND 6 5 C3 16 D3 15 LED1 8 7 LWY87S GND C2P C2N C1N C1P GND Z3 GND GROUND 100 nF 10 C8 1 2 3 4 9 TP1 VREF GND R1 GND 330 k BSS138 GND Q1 GND VCC R2 S2 ENABLE GND 6.8 k VCC 6 U3A MC14538B Q Q 7 U3B MC14538B 4.7 mF/6.3 V GND S1 POWER C7 GND 2.2 mF/6.3 V 10 k 10 k R6 C9 100 nF R5 GND 1 NL27WZ14 2*1.5 V + + PK1 − 2 GND C6 22 nF 4 VCC 1.5 k PWM GND D5 + 3 4 P1 100 kA Adjust PWM U2B 3 R4 6 100 k VCC NL27WZ14 CNT/PWM S1 VCC U2A R3 100 k 1 Figure 19. Demo Board Schematic Diagram http://onsemi.com 13 R7 12 A 11 B 13 CLR VCC RC GND CLR RC C5 C A B Q 2 1 4 5 3 14 15 C Q 9 NCP5604A, NCP5604B Figure 20. Silk View Top Layer Figure 21. Demo Board Printed Circuit Layout http://onsemi.com 14 NCP5604A, NCP5604B PACKAGE DIMENSIONS WQFN16 MT SUFFIX CASE 488AK−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM SPACING BETWEEN LEAD TIP AND FLAG. MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 8 NOTE 5 4 16X K 1 12 16X 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. ÇÇÇ ÇÇÇ (A3) D2 e 9 16 13 E A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L EXPOSED PAD E2 b BOTTOM VIEW http://onsemi.com 15 NCP5604/D