NCP59748MN1ADJTBG

DATA SHEET www.onsemi.com Linear Regulator Dual-Rail, Very Low‐Dropout, Programmable Soft‐Start QFN20 CASE 485DB 1.5 A PIN CONNECTIONS IN NC NC NC OUT NCP59748 The NCP59748 is dual−rail very low dropout voltage regulator, capable of providing an output current in excess of 1.5 A with a dropout voltage of 60 mV typ. at full load current. The devices are stable with ceramic and any other type of output capacitor ≥ 2.2 mF. This series contains adjustable output voltage version with output voltage down to 0.8 V. Internal protection features consist of built-in thermal shutdown and output current limiting protection. User-programmable Soft-Start and Power-Good pins are available on both QFN and DFN versions. The NCP59748 is offered in DFN10 3×3 and QFN20 5×5 packages. Output Current in Excess of 1.5 A VIN Range: 0.8 V to 5.5 V VBIAS Range: 2.7 V to 5.5 V Output Voltage Range: 0.8 V to 3.6 V Dropout Voltage: 60 mV at 1.5 A Programmable Soft-Start Open Drain Power Good Output Fast Transient Response Stable with Any Type of Output Capacitor ≥ 2.2 mF Current Limit and Thermal Shutdown Protection These are Pb−Free Devices 5 4 3 2 1 6 20 7 19 GND 8 18 9 17 10 16 11 12 13 14 15 OUT OUT OUT NC FB EN GND NC NC SS IN IN IN PG BIAS QFN20−5y5−0.65P Features • • • • • • • • • • • DFN10 CASE 485C IN 1 10 OUT IN 2 9 PG BIAS EN 3 OUT FB SS GND Thermal Pad 4 8 7 6 5 DFN10−3y3−0.5P MARKING DIAGRAMS 1 NCP59748 AWLYYWWG G Applications • Consumer and Industrial Equipment Point of Load Regulation • FPGA, DSP and Logic Power Supplies • Switching Power Supply Post Regulation NCP59748 QFN20 A WL YY, Y WW, W G 1 NCP 59748 AYWG G DFN10 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information on page 4 of this data sheet. Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2016 January, 2022 − Rev. 4 1 Publication Order Number: NCP59748/D NCP59748 Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Name QFN20 DFN10 Description IN 5−8 1, 2 EN 11 5 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. SS 15 7 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 200 ms. BIAS 10 4 Bias input voltage for error amplifier, reference, and internal control circuits. PG 9 3 Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kW to 1 MW should be connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. FB 16 8 This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. OUT 1, 18−20 9, 10 Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 mF, ceramic) is needed from this pin to ground to assure stability. NC 2−4, 13, 14, 17 N/A No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. GND 12 6 PAD/TAB Unregulated input to the device. Ground Should be soldered to the ground plane for increased thermal performance. www.onsemi.com 2 NCP59748 Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Input Voltage Range VIN −0.3 to +6 V Input Voltage Range VBIAS −0.3 to +6 V Enable Voltage Range VEN −0.3 to +6 V Power−Good Voltage Range VPG −0.3 to +6 V PG Sink Current IPG 0 to +1.5 mA SS Pin Voltage Range VSS −0.3 to +6 V Feedback Pin Voltage Range VFB −0.3 to +6 V Output Voltage Range VOUT −0.3 to (VIN + 0.3) ≤ 6 V Maximum Output Current IOUT Internally Limited PD See Thermal Characteristics Table and Formula Output Short Circuit Duration Indefinite Continuous Total Power Dissipation Maximum Junction Temperature TJMAX +150 °C Storage Junction Temperature Range TSTG −55 to +150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22−A114 ESD Machine Model tested per EIA/JESD22−A115 Latch-up Current Maximum Rating tested per JEDEC standard: JESD78. Table 3. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Resistance, Junction−to−Ambient (Note 5) RqJA 30.5 °C/W Thermal Resistance, Junction−to−Case (bottom) (Note 6) RqJC 4.1 °C/W Thermal Resistance, Junction−to−Ambient (Note 5) RqJA 41.5 °C/W Thermal Resistance, Junction−to−Case (bottom) (Note 6) RqJC 6.6 °C/W Thermal Characteristics, QFN20, 5x5, 0.65P package Thermal Characteristics, DFN10, 3x3, 0.5P package 3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following assumptions are used in the simulations: This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the JEDEC51.7 guidelines. − QFN20: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated. − QFN20: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. − DFN10: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. Vias are 0.3 mm diameter, plated. − DFN10: Each of top and bottom copper layers are assumed to have thermal conductivity representing 20% copper coverage. 5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7 guidelines with assumptions as above, in an environment described in JESD51−2a. 6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can be found in the ANSI SEMI standard G30−88. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7) Symbol Min Max Unit Input Voltage VIN VOUT + VDO 5.5 V Bias Voltage VBIAS 2.7 5.5 V TJ −40 125 °C Rating Junction Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 3 NCP59748 Table 5. ELECTRICAL CHARACTERISTICS (At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 mF, CSS = 1 nF, CIN = COUT = 10 mF, IOUT = 50 mA, VBIAS = 5.0 V, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C.) Symbol VIN Parameter Test Conditions Input Voltage Range Min Typ Max Unit VOUT + VDO − 5.5 V 2.7 − 5.5 V − − 1.6 0.4 − − V V VBIAS Bias Pin Voltage Range UVLO Undervoltage Lock-out VBIAS Rising Hysteresis VREF Internal Reference (Adj.) TJ = +25°C 0.796 0.8 0.804 VOUT Output Voltage Range VIN = 5 V, IOUT = 1.5 A VREF − 3.6 V Accuracy (Note 1) 2.97 V < VBIAS < 5.5 V, 50 mA < IOUT < 1.5 A −2 ±0.5 +2 % VOUT/VIN Line Regulation VOUT (NOM) + 0.3 < VIN < 5.5 V − 0.03 − %/V VOUT/IOUT Load Regulation 50 mA < IOUT < 1.5 A − 0.09 − %/A VIN Dropout Voltage (Note 2) IOUT = 1.5 A, VBIAS − VOUT (NOM) ≥ 3.25 V (Note 3) − 60 165 mV VBIAS Dropout Voltage (Note 2) IOUT = 1.5 A, VIN = VBIAS − 1.31 1.6 V Current Limit VOUT = 80% × VOUT (NOM) 2.0 − 5.5 A − 1 2 mA − 1 50 mA −1 0.15 1 mA dB VDO ICL IBIAS Bias Pin Current ISHDN Shutdown Supply Current (IGND) IFB PSRR VEN ≤ 0.4 V Feedback Pin Current Power-Supply Rejection (VIN to VOUT) Power-Supply Rejection (VBIAS to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V − 60 − 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V − 30 − 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V − 50 − 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V − 30 − dB Noise Output Noise Voltage 100 Hz to 100 kHz, IOUT = 1.5 A − 25 × VOUT − tSTRT Minimum Startup Time RLOAD for IOUT = 1.0 A, CSS = open − 200 − ms Soft-Start Charging Current VSS = 0.4 V − 0.44 − mA ISS mVrms VEN, HI Enable Input High Level 1.1 − 5.5 V VEN, LO Enable Input Low Level 0 − 0.4 V VEN, HYS Enable Pin Hysteresis − 50 − mV VEN, DG Enable Pin Deglitch Time − 20 − ms IEN Enable Pin Current VEN = 5 V − 0.1 1 mA VIT PG Trip Threshold VOUT Decreasing 85 90 94 %VOUT VHYS PG Trip Hysteresis − 3 − %VOUT − 0.3 V VPG, LO PG Output Low Voltage IPG = 1 mA (Sinking), VOUT < VIT − IPG, LKG PG Leakage Current VPG = 5.25 V, VOUT > VIT − 0.1 1 mA Thermal Shutdown Temperature Shutdown, Temperature Increasing Reset, Temperature Decreasing − − +165 +140 − − °C TSD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Adjustable devices tested at VREF; external resistor tolerance is not taken into account. 2. Dropout is defined as the voltage from the input to VOUT when VOUT is 3% below nominal. 3. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8. Table 6. ORDERING INFORMATION Output Current Output Voltage Junction Temperature Range NCP59748MN1ADJTBG 1.5 A ADJ NCP59748MN2ADJTBG 1.5 A ADJ Device Package Shipping† −40°C to +125°C DFN10 3000 / Tape & Reel −40°C to +125°C QFN20 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4 NCP59748 TYPICAL CHARACTERISTICS 0.20 0.5 0.15 0.4 0.10 −40°C +125°C 0.05 0 CHANGE IN VOUT (%) CHANGE IN VOUT (%) At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. +25°C −0.05 −0.10 −0.15 −0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 −0.1 −0.3 0.5 1.0 1.5 2.0 2.5 3.0 VBIAS − VOUT (V) Figure 3. VIN Line Regulation Figure 4. VBIAS Line Regulation 3.5 4.0 0.5 0.3 0.2 CHANGE IN VOUT (%) 0.4 0.3 +125°C 0.1 +25°C 0 −0.1 −0.2 −0.3 −40°C 0 10 20 30 40 50 0.1 +25°C 0 −0.1 −0.2 −0.3 −40°C 0 0.5 1.0 1.5 IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (A) Figure 5. Load Regulation Figure 6. Load Regulation 50 +125°C 40 +25°C 30 −40°C 20 10 0 +125°C 0.2 −0.4 −0.5 60 0 +25°C −0.2 0.4 −0.4 −0.5 +125°C −40°C 0.1 VIN − VOUT (V) VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) CHANGE IN VOUT (%) 0.2 −0.4 −0.5 0.5 VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) 0.3 0.5 1.0 1.5 200 180 IOUT = 1.5 A 160 140 120 100 80 +125°C 60 +25°C 40 −40°C 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IOUT, OUTPUT CURRENT (A) VBIAS − VOUT (V) Figure 7. VIN Dropout Voltage vs. IOUT and Temperature TJ Figure 8. VIN Dropout Voltage vs. (VBIAS − VOUT) and Temperature TJ www.onsemi.com 5 4.5 NCP59748 TYPICAL CHARACTERISTICS VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV) VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. 200 1200 180 IOUT = 0.5 A 160 140 −40°C 120 +25°C 100 +125°C 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS − VOUT (V) 1100 −40°C 1000 +25°C 900 +125°C 800 700 600 0 2000 2000 1800 −40°C 1000 800 −40°C 1000 800 600 400 400 200 200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOUT, OUTPUT CURRENT (A) VBIAS (V) Figure 11. BIAS Pin Current vs. IOUT and Temperature TJ Figure 12. BIAS Pin Current vs. VBIAS and Temperature TJ 0.500 5.5 VPG,LO, L−LEVEL PG VOLTAGE (V) 1.0 0.475 0.450 ISS (mA) +125°C 1200 600 0 +25°C 1400 IBIAS (mA) 1200 IBIAS (mA) 1600 +25°C +125°C 1.5 Figure 10. VBIAS Dropout Voltage vs. IOUT and Temperature TJ 1800 1400 1.0 IOUT, OUTPUT CURRENT (A) Figure 9. VIN Dropout Voltage vs. (VBIAS − VOUT) and Temperature TJ 1600 0.5 0.425 0.400 0.375 0.350 0.325 0.300 −50 −25 0 25 50 75 100 125 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 TJ, JUNCTION TEMPERATURE (°C) IPG, PG PIN CURRENT (mA) Figure 13. Soft Start Charging Current ISS vs. Temperature TJ Figure 14. L−level PG Voltage vs. Current www.onsemi.com 6 12 NCP59748 TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. 4.5 −40°C ICL, CURRENT LIMIT (A) 4.0 3.5 +25°C +125°C 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VBIAS − VOUT (V) Figure 15. Current Limit vs. (VBIAS − VOUT) Figure 16. Start by Enable @ CSS = 0 nF 90 80 PSRR (dB) 70 60 IOUT = 100 mA IOUT = 1.5 A 50 40 30 VIN = 1.8 V + 100 mVPP Modulation VBIAS = 5 V, VOUTNOM = 1.2 V CBIAS = 4.7 mF, COUT = 10 mF Resistive Load 20 10 0 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) Figure 17. Start by Enable @ CSS = 1 nF Figure 18. VIN PSRR NOISE SPECTRAL DENSITY (nV/√Hz) 90 80 PSRR (dB) 70 IOUT = 100 mA IOUT = 0.5 A IOUT = 1.5 A 60 50 40 30 20 VBIAS = 5 V + 100 mVPP Modulation, VIN = 1.8 V, VOUTNOM = 1.2 V CIN = 0.1 mF + 1 mF + 10 mF COUT = 10 mF, Resistive Load 10 100 1K 10K 100K 1M 10M 350 CSS = 0 CSS = 1 nF CSS = 10 nF 300 VIN = 1.5 V VBIAS = 5 V VOUTNOM = 1.2 V ILOAD = 100 mA CBIAS = 4.7 mF CIN = COUT = 10 mF Resistive Load 250 200 150 100 50 100 1K 10K FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. VBIAS PSRR Figure 20. Noise Density vs. CSS www.onsemi.com 7 100K NCP59748 APPLICATIONS INFORMATION greater. Ceramic or other low ESR capacitors are recommended. For the best performance all the capacitors should be connected to the NCP59748 respective pins directly in the device PCB copper layer, not through vias having not negligible impedance. The NCP59748 dual−rail very low dropout voltage regulator is using NMOS pass transistor for output voltage regulation from VIN voltage. All the low current internal controll circuitry is powered from the VBIAS voltage. The use of an NMOS pass transistor offers several advantages in applications. Unlike a PMOS topology devices, the output capacitor has reduced impact on loop stability. Vin to Vout operating voltage difference can be very low compared with standard PMOS regulators in very low Vin applications. The NCP59748 offers programmable smooth monotonic start-up. The controlled voltage rising limits the inrush current what is advantageous in applications with large capacitive loads. The Voltage Controlled Soft−Start timing is programmable by external Css capacitor value. The Enable (EN) input is equipped with internal hysteresis and deglitch filter. Open Drain type Power Good (PG) output is available for Vout monitoring and sequencing of other devices. NCP58748 is a Adjustable linear regulator. The required Output voltage can be adjusted by two external resistors. Typical application schematics is shown in Figure 21. Enable Operation The enable pin will turn the regulator on or off. The threshold limits are covered in the electrical characteristics table in this data sheet. If the enable function is not to be used then the pin should be connected to VIN or VBIAS. The NCP59748 device is equipped with Output Active Discharge transistor that is pulling the output to GND through an 1.2 kW (typ.) resistor when the device is disabled. To get the full functionality of Soft−Start, it is recommended to turn on the VIN and VBIAS supply voltages first and activate the Enable pin no sooner than VIN and VBIAS are on their nominal levels. Output Noise When the NCP59748 device reaches the end of the Soft−Start cycle, the Soft Start capacitor is switched to serve as a Noise filtering capacitor. Output Voltage Adjust The output voltage can be adjusted from 0.8 V to 3.6 V using resistors divider between the output and the FB input. Recommended resistor values for frequently used voltages can be found in the Table 7. Programmable Soft−Start V OUT + 0.8 ǒ1 ) R 1ńR 2Ǔ Figure 21. Typical Application Schematics The Soft-Start ramp time depends on the Soft−Start charging current ISS, Soft-Start capacitor value CSS and internal reference voltage VREF. The Soft–Start time can be calculated using following equations: tss = CSS x (VREF / ISS) [s, F,V,A] or in more practical units tSS = CSS x 0.8V / 0.44 = CSS x 1.82 where tss = Soft−Start time in miliseconds CSS = Soft−Start capacitor value in nano Farads Capacitor values for frequently used Soft-Start times can be found in the Table 8. The maximal recommended value of CSS capacitor is 15 nF. For higher CSS values the capacitor full discharging before new Soft-Start cycle is not guaranteed. Dropout Voltage Because of two power supply inputs VIN and VBIAS and one VOUT regulator output, there are two Dropout voltages specified. The first, the VIN Dropout voltage is the voltage difference (VIN – VOUT) when VOUT starts to decrease by percents specified in the Electrical Characteristics table. VBIAS is high enough, specific value is published in the Electrical Characteristics table. The second, VBIAS dropout voltage is the voltage difference (VBIAS – VOUT) when VIN and VBIAS pins are joined together and VOUT starts to decrease. Input and Output Capacitors The device is designed to be stable for all available types and values of output capacitors ≥ 2.2 mF. The device is also stable with multiple capacitors in parallel, which can be of any type or value. In applications where no low input supplies impedance available (PCB inductance in VIN and/or VBIAS inputs as example), the recommended CIN and CBIAS value is 1 mF or Power Good Power−Good (PG) is an open−drain, active−high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high−impedance state. When VOUT is below this threshold the pin is driven to a low−impedance state. A pull−up resistor from 10 kW to www.onsemi.com 8 NCP59748 1 MW should be connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. Table 8. CAPACITOR VALUES FOR PROGRAMMING THE SOFT−START TIME Soft−Start Time CSS 0.2 ms Open 0.5 ms 270 pF 1 ms 560 pF 5 ms 2.7 nF 10 ms 5.6 nF 18 ms 10 nF Current Limitation The internal Current Limitation circuitry allows the device to supply the full nominal current and surges but protects the device against Current Overload or Short. The response time of this protection is in the range of microseconds. Thermal Protection Internal thermal shutdown (TSD) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When TSD activated , the regulator output turns off. When cooling down under the low temperature threshold, device output is activated again. This TSD feature is provided to prevent failures from accidental overheating. Table 7. RESISTOR VALUES FOR PROGRAMMING THE OUTPUT VOLTAGE VOUT (V) R1 (kW) R2 (kW) 0.8 Short Open 0.9 0.619 4.99 1.0 1.13 4.53 1.05 1.37 4.33 1.1 1.87 4.99 1.2 2.49 4.99 1.5 4.12 4.75 1.8 3.57 2.87 2.5 3.57 1.69 3.3 3.57 1.15 NOTE: VOUT = 0.8 x (1 + R1/R2) Resistors in the table are standard 1% types www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE F SCALE 2:1 DATE 16 DEC 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot *This information is generic. Please refer to Y = Year device data sheet for actual part marking. W = Work Week Pb−Free indicator, “G” or microdot “G”, may G = Pb−Free Package or may not be present. Some products may (Note: Microdot may be in either location) not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON03161D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN20 5x5, 0.65P CASE 485DB ISSUE O 1 20 SCALE 2:1 PIN ONE REFERENCE ÉÉ ÉÉ A B D L L1 E DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS 0.15 C 0.15 C L NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. OPTIONAL FEATURES. DIM A A1 A3 b D D2 E E2 e L L1 TOP VIEW A (A3) DETAIL B 0.10 C DATE 02 APR 2013 DETAIL B 0.08 C A1 NOTE 5 NOTE 4 ALTERNATE CONSTRUCTION C SIDE VIEW 0.10 DETAIL A 6 D2 SEATING PLANE GENERIC MARKING DIAGRAM* C A B 20X L M 1 0.10 M XXXXXXXX XXXXXXXX AWLYYWWG G C A B 11 E2 1 16 20X e BOTTOM VIEW b 0.10 M C A B 0.05 M C XXXXX A WL YY WW G NOTE 3 PACKAGE OUTLINE *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 20X 0.78 3.30 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) RECOMMENDED SOLDERING FOOTPRINT* 5.30 3.30 MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.25 0.35 5.00 BSC 3.05 3.25 5.00 BSC 3.05 3.25 0.65 BSC 0.45 0.65 −−− 0.15 5.30 20X 0.65 PITCH 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON88183E QFN20 5x5, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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