NCP81022
Dual Output 4 Phase Plus 1
Phase Digital Controller
with SVI2 Interface for
Desktop and Notebook CPU
Applications
The NCP81022 dual output four plus one phase buck solution is
optimized for AMD® SVI2 CPUs. The controller combines true
differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for both desktop and notebook
applications.
The control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing an ultra fast
initial response to dynamic load events and reduced system cost. The
NCP81022 provides the mechanism to shed to single phase during
light load operation and can auto frequency scale in light load
conditions while maintaining excellent transient performance.
Dual high performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
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MARKING
DIAGRAM
1 52
QFN52
CASE 485BE
A
WL
YY
WW
G
NCP81022
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 40 of
this data sheet.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Meets AMD’S SVI2 Specifications
Four phase CPU Voltage Regulator
One phase North Bridge Voltage Regulator
Current Mode Dual Edge Modulation for Fast Initial Response to
Transient Loading
Dual High Performance Operational Error Amplifier
One Digital Soft Start Ramp for Both Rails
• Startup into Pre−Charged Loads while avoiding False
OVP
Dynamic Reference Injection
•
Power Saving Phase Shedding
Accurate Total Summing Current Amplifier
• Vin Feed Forward Ramp Slope
DAC with Droop Feed−forward Injection
• Pin Programming for Internal SVI2 Parameters
Dual High Impedance Differential Voltage and Total
• Over Voltage Protection (OVP) and Under Voltage
Current Sense Amplifiers
Protection (UVP)
Phase−to−Phase Dynamic Current Balancing
• Over Current Protection (OCP)
“Lossless” DCR Current Sensing for Current Balancing
• Dual Power Good Output with Internal Delays
Summed Compensated Inductor Current Sensing for
• These Devices are Pb−Free and Halogen Free
Droop
True Differential Current Balancing Sense Amplifiers
Applications
for Each Phase
• Desktop and Notebook Processors
Adaptive Voltage Positioning (AVP)
• Gaming
Switching Frequency Range of 240 kHz – 1.0 MHz
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 7
1
Publication Order Number:
NCP81022/D
NCP81022
SCL
SDA
ENABLE_NB
ENABLE
VSS_SENSE
VDDNB_SENSE
NB_DAC
DIGITAL
EN
INTERFACE
GND
UV LO & EN
VDDNB_PWRGD
VDDNB_PWRGD
COMPARATOR
ENABLE
Digital Config and
VCC
ENABLE
value registers
VSS_SENSE
VDD_SENSE
DAC
DROOP
NORTH BRIDGE OVP_NB
VDD_SENSE
PROTECTION
DAC
ENABLE
SVD
SVI2
INTERFACE
SVC
OVP
OVP
VDDNB_SENSE
ENABLE_NB
ADC
MUX
SVT
VDDIO
VBOOT
VDD_PWRGD
OVP
VSS_SENSE
OVER CURRENT
OCP_L
VDD_PWRGD
COMPARATOR
VDDNB − VSS_SENSE
VDD −VSS_SENSE
IMAX
IMAXNB
SR
SRNB
DIFFAMP
VDD
VSS
GND
CSREF
DROOP
DAC
DAC
DIFF
NB_DAC
DAC
VSS
VDDNB
DAC
DIFFAMP
NORTH
BRIDGE
GND
CSREF
CSSUM
CS
AMP
ILIM
IOUT
CSREF
CSCOMP
DROOPNB
ILIM
IOUT
DIFFNB
FB
TRBST
CONTROL
FBNB
ERROR
AMP_NB
ERROR
AMP
NORTH
BRIDGE
TRANSIENT
CONTROL
COMPNB
COMP
ENABLENB
TRBST
COMPNNB
TRBSTNB
OVPNB
CSN 1NB
CS
AMP
IOUTNB
CSP2
ENABLE
NORTH
BRIDGE
MAINRAIL
CSCOMPNB
ILIMNB
CSP1
ENABLE_NB
CSN1
CSSUMNB
ILIM
IOUT
NORTH BRIDGE
RMPNB
RAMP
GENERATORS
CSN2
CURRENT
BALANCE
CSP3
CSN3
PHASE
GENERATOR
CSP4
CSN4
ENABLE
COMP
CSP1NB
CURRENT
BALANCE
OVP
PWM1
RAMP1
RAMP2
NCP81022
RAMP3
VRMP
D RON
RAMP4
PWM1NB
CSN1NB
Figure 1. Block Diagram
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2
PWM2
PWM
GENERATOR
PWM3
PWM4
52
51
50
49
48
47
46
45
44
43
42
41
40
VSS
VDD
DIFF
TRBST
FB
COMP
ILIM
DROOP
CSCOMP
CSSUM
IOUT
CSREF
CSP4
NCP81022
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
NCP81022
Pin Package
(PIN 53 AGND)
CSN4
CSN2
CSP2
CSN3
CSP3
CSN1
CSP1
DRON
PWM1/SR
PWM3/IMAX
PWM2/IMAXNB
PWM4/ADD
PWM1NB/SRNB
OCP_L
VDDNB
FBNB
DIFFNB
TRBSTNB
COMPNB
ILIMNB
DROOPNB
CSCOMPNB
IOUTNB
CSSUMNB
CSP1NB
CSN1NB
14
15
16
17
18
19
20
21
22
23
24
25
26
PWROK
SVD
SVT
SVC
VDDIO
SCL
SDA
VDDNB_PWRGD
VDD_PWRGD
EN
VCC
ROSC
VRMP
Figure 2. NCP81022 Pinout
QFN52 PIN LIST DESCRIPTION
Pin No.
Symbol
Description
1
PWROK
2
SVD
Serial VID data line
3
SVT
Serial VID telemetry line
4
SVC
Serial VID clock line
5
VDDIO
6
SCL
serial clock line, Open drain, requires pullup resistor
7
SDA
Bi directional serial data line. Open drain, requires pullup resistor.
8
VDDNB_PWRGD
9
VDD_PWRGD
10
EN
Logic input. Logic high enables Main and North Bridge Rail output and logic low disables main rail
output.
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground.
Active high system wide power ok signal
VDDIO is an interface power rail that serves as a reference for SVI2 interface
Open drain output. High output on this pin indicates that the North Bridge Rail output is regulating.
Open drain output. High output on this pin indicates that the Main Rail output is regulating.
11
VCC
12
ROSC
A resistor to ground on this pin will set the oscillator frequency
13
VRMP
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to
control of the ramp of PWM slope
14
OCP_L
Open drain output. Signals an over current event has occurred
15
VDDNB
Non−inverting input to the North Bridge Rail differential remote sense amplifier.
16
FBNB
17
DIFFNB
Output of the North Bridge Rail differential remote sense amplifier.
18
TRBSTNB
Compensation pin for the load transient boost for North Bridge Rail
19
COMPNB
Output of the error amplifier and the inverting inputs of the PWM comparators for the North Bridge
Rail output.
Error amplifier voltage feedback for North Bridge Rail output
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3
NCP81022
QFN52 PIN LIST DESCRIPTION
Pin No.
Symbol
Description
20
ILIMNB
21
DROOPNB
22
CSCOMPNB
23
IOUTNB
24
CSSUMNB
25
CSP1NB
Non−inverting input to current balance sense amplifier for phase 1NB
26
CSN1NB
Inverting input to current balance sense amplifier for phase1NB
27
PWM1NB/SRNB
28
PWM4/ADD
29
PWM2/IMAXNB
30
PWM3/IMAX
31
PWM1/SR
32
DRON
Bidirectional gate driver enable for external drivers for both Main and North Bridge Rails. It should be
left floating if unused.
33
CSP1
Non−inverting input to current balance sense amplifier for Main Rail phase 1
34
CSN1
Non−inverting input to current balance sense amplifier for Main Rail phase 1
35
CSP3
Non−inverting input to current balance sense amplifier for Main Rail phase 3
36
CSN3
Inverting input to current balance sense amplifier for Main Rail phase3
37
CSP2
Non−inverting input to current balance sense amplifier for Main Rail phase 2
38
CSN2
Inverting input to current balance sense amplifier for Main Rail phase2
39
CSN4
Inverting input to current balance sense amplifier for Main Rail phase4
40
CSP4
Non−inverting input to current balance sense amplifier for Main Rail phase 4
41
CSREF
42
IOUT
43
CSSUM
44
CSCOMP
45
DROOP
46
ILM
47
COMP
48
FB
49
TRBST
Compensation pin for the load transient boost for Main Rail
50
DIFF
Output of the Main Rail differential remote sense amplifier.
51
VDD
Non−inverting input to the Main Rail differential remote sense amplifier
52
VSS
Inverting input to the Main Rail differential remote sense amplifier.
53
AGND
Over current shutdown threshold setting for North Bridge Rail output. Resistor to CSCOMP to set
threshold.
Used to program DACFF function for North Bridge Rail output. It’s connected to the resistor divider
placed between CSCOMPNB and CSREFNB summing node.
Output of total current sense amplifier for North Bridge Rail output.
Total output current monitor for North Bridge Rail.
Inverting input of total current sense amplifier for North Bridge Rail output.
North Bridge Phase1 PWM output. A resistor from this pin to ground programs SR North Bridge rail
Main Rail Phase 4PWM output. A resistor from this pin to ground programs the SMBus address.
Main Rail Phase 2PWM output. During start up it is used to program ICC_MAX for the North Bridge
Rail with a resistor to ground
Main Rail Phase 3PWM output. During start up it is used to program ICC_MAX for the Main Rail with
a resistor to ground
Main Rail Phase 1PWM output. A resistor to ground on this pin programs SR Main rail.
Total output current sense amplifier reference voltage input for Main Rail and inverting input to Main
Rail current balance sense amplifier for phase 1 and 2
Total output current monitor for Main Rail.
Inverting input of total current sense amplifier for Main Rail output
Output of total current sense amplifier for Main Rail output
Used to program DACFF function for Main Rail output. It’s connected to the resistor divider placed
between CSCOMP and CSREF.
Over current shutdown threshold setting for Main Rail output. Resistor to CSCOMP to set threshold.
Output of the Main Rail error amplifier and the inverting input of the PWM comparator for Main Rail
output
Error amplifier voltage feedback for Main Rail output
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4
NCP81022
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
COMP, COMPNB
VCC + 0.3 V
−0.3 V
2 mA
2 mA
CSCOMP, CSCOMPNB
VCC + 0.3 V
−0.3 V
2 mA
2 mA
VSS,
GND + 300 mV
GND – 300 mV
1 mA
1 mA
VDD_PWRGD,
VDDNB_PWRGD
VCC + 0.3 V
−0.3 V
N/A
2 mA
VCC
6.5 V
−0.3 V
N/A
N/A
VRMP
+25 V
−0.3 V
All Other Pins
VCC + 0.3 V
−0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Symbol
Typ
Unit
Thermal Characteristic − QFN Package (Note 1)
RJA
68
°C/W
Operating Junction Temperature Range (Note 2)
TJ
−10 to 125
°C
−10 to 100
°C
°C
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
−40 to +150
Moisture Sensitivity Level − QFN Package
MSL
1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
NCP81022 (4+1) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
MIN
TYP
MAX
Unit
400
nA
ERROR AMPLIFIER
−400
Input Bias Current
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 KW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
55
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
DC Load = 10k to GND
20
mV/ms
Slew Rate
Maximum Output Voltage
ISOURCE = 2.0 mA
3.5
−
−
V
Minimum Output Voltage
ISINK = 2.0 mA
−
−
1
V
Input Bias Current
−400
−
400
nA
VDD Input Voltage Range
−0.3
−
3.0
V
VSS Input Voltage Range
−0.3
−
0.3
V
DIFFERENTIAL SUMMING AMPLIFIER
−3dB Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
12
MHz
Closed Loop DC gain VS to DIFF
VS+ to VS− = 0.5 to 1.3 V
1.0
V/V
Droop Accuracy
CSREF−DROOP = 80 mV
DAC = 0.8 V to 1.2 V
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5
−1.5
+1.5
mV
NCP81022
NCP81022 (4+1) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
MIN
TYP
MAX
Unit
Maximum Output Voltage
ISOURCE = 2 mA
3.0
−
−
V
Minimum Output Voltage
ISINK = 2 mA
−
−
0.5
V
1.2 V
−300
300
mV
CSSUM = CSREF= 0.5 − 1.5 V
−1
1
mA
DIFFERENTIAL SUMMING AMPLIFIER
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
Input Bias Current
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
10
MHz
Maximum CSCOMP (NB) Output Voltage
Isource = 2mA
3.5
−
−
V
Minimum CSCOMP(NB) Output Voltage
Isink = 500uA
−
−
0.15
V
CSP1−4NB = CSN1−4NB = 1.2 V
CSP = CSN = 1.2 V
−200
CSPx = CSREF
0
−
2.0
V
CSNx = 1.2 V
−100
−
100
mV
Closed loop Input Offset Voltage Matching
CSPx = CSNx =1.2 V,
Measured from the average
−1.5
−
1.5
mV
Current Sense Amplifier Gain
0V < CSPx−CSNx < 0.1 V,
5.7
6.0
6.3
V/V
CSN = CSP = 10 mV to 30 mV
−3.8
3.8
%
CURRENT BALANCE AMPLIFIER
Input Bias Current
Common Mode Input Voltage Range
Differential Mode Input Voltage Range
Multiphase Current Sense Gain Matching
−3dB Bandwidth
−
200
8
nA
MHz
BIAS SUPPLY
4.75
Supply Voltage Range
5.25
VCC Quiescent Current
VCC rising
UVLO Threshold
VCC falling
48
mA
4.5
V
3.9
VCC UVLO Hysteresis
V
200
mV
VRMP
4.5
Supply range
UVLO Threshold
VCC rising
20
4.2
V
VCC falling
3
Hysteresis
V
V
800
mV
2.5
mv/ms
Slew Rate Slow
5
mv/ms
Slew Rate Fast
20
mv/ms
NORTH BRIDGE Soft Start Slew Rate
2.5
mv/ms
NORTH BRIDGE Slew Rate Slow
2.5
mv/ms
NORTH BRIDGE Slew Rate Fast
10
mv/ms
DAC SLEW RATE
Soft Start Slew Rate
ENABLE INPUT
Enable High Input Leakage Current
External 1k pull−up to 3.3 V
−
VUPPER
2
Upper Threshold
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6
1.0
mA
V
NCP81022
NCP81022 (4+1) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
MIN
TYP
MAX
Unit
ENABLE INPUT
Lower Threshold
VLOWER
0.8
V
Enable delay time
Measure time from Enable
transitioning HI , VBOOT is not 0 V
15
ms
DRON
Output High Voltage
Sourcing 500 mA
3.0
−
−
V
Output Low Voltage
Sinking 500 mA
−
−
0.1
V
Pull Up Resistances
Rise/Fall Time
Internal Pull Down Resistance
2.0
kW
CL (PCB) = 20 pF,
DVo = 10% to 90%
160
ns
EN = Low
70
kW
IOUT OUTPUT /IOUTNB
Input Referred Offset Voltage
Output current max
Current Gain
Ilimit to CSREF
−3
+3
mV
Ilim Sink current 80 mA
−
−
800
mA
(IOUTCURRENT) / (ILIMITCURRENT),
RLIM = 20k, RIOUT = 5.0k,
DAC = 0.8 V, 1.25 V, 1.52 V
9.5
10
10.5
240
−
1000
kHz
−10
−
10
%
360
400
440
kHz
270
325
380
mV
OSCILLATOR
Switching Frequency Range
Switching Frequency Accuracy
200 kHz < Fsw < 1 MHz
4 Phase Operation
OUTPUT OVER VOLTAGE AND UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During Soft−Start
Over Voltage Delay
VDD rising
VDD rising to PWMx low
Under Voltage Threshold Below DAC−DROOP
VDD falling
Under−voltage Hysteresis
VDD rising
50
170
Under−voltage Delay
325
ns
380
mV
25
mV
5
ms
SVI2 DAC
1.2 V ≤ DAC < 1.55 V
0.8 V< DAC < 1.2 V
0.0 V DAC < 0.800 V
−2
−10
−2
Feed−Forward Current
Measure on DROOP, DROOPNB
pin
59
Droop Falling current
Measure on DROOP, DROOPNB
pin
23
System Voltage Accuracy
Droop Feed−Forward Pulse On−Time
66
2
10
2
LSB
mV
LSB
71
mA
29
mA
ms
0.16
OVERCURRENT PROTECTION
ILIM Threshold Current (OCP shutdown after
50 ms delay)
Main Rail, RLIM = 20 kW
8
10
11.0
mA
ILIM Threshold Current (immediate OCP shutdown)
Main Rail, RLIM = 20 kW
13
15
16.5
mA
ILIM Threshold Current (OCP shutdown after
50 ms delay)
Main Rail, (PSI0, PSI1)
RLIM = 20 kW
10
mA
ILIM Threshold Current (immediate OCP shutdown)
Main Rail, (PSI0, PSI1)
RLIM = 20 kW
15
mA
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NCP81022
NCP81022 (4+1) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
MIN
TYP
MAX
Unit
ILIM Threshold Current (OCP shutdown after
50 ms delay)
North Bridge Rail, RLIM = 20 kW
8
10
11.0
mA
ILIM Threshold Current (immediate OCP shutdown)
North Bridge Rail, RLIM = 20 kW
13
15
16.5
mA
ILIM Threshold Current (OCP shutdown after
50 ms delay)
North Bridge Rail RLIM = 20 kW
10
mA
ILIM Threshold Current (immediate OCP shutdown)
North Bridge Rail, RLIM = 20 kW
15
mA
Fsw = 360 kHz
60
ns
COMP voltage when the PWM
outputs remain LO
1.3
−
V
2.5
−
V
OVERCURRENT PROTECTION
MODULATORS (PWM COMPARATORS) FOR MAIN RAIL AND NORTH BRIDGE
Minimum Pulse Width
0% Duty Cycle
100% Duty Cycle
COMP voltage when the PWM
outputs remain HI VRMP = 12.0 V
PWM Ramp Duty Cycle Matching
COMP = 2 V, PWM Ton matching
1
%
Between adjacent phases
±5
Deg
PWM Phase Angle Error
Ramp Feed−forward Voltage range
−
5
22
V
TRBST#
Output Low Voltage
ISink = 500 mA
100
mV
OCP_L#
0.3
V
1.0
mA
0
2
V
−1.25
1.25
%
1
LSB
Output Low Voltage
Output Leakage Current
High Impedance State
−1.0
−
ADC
Voltage Range
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
8−bit, No Missing codes
Power Supply Sensitivity
±1
%
Conversion Time
30
ms
Round Robin
90
ms
VDD_PWRGD, VDDNB_PWRGD OUTPUT
IVDD(NB)_PWRGD= 4 mA,
−
−
Rise Time
External pull−up of 1 kW to 3.3 V,
CTOT = 45 pF, DVo = 10% to 90%
−
100
ns
Fall Time
External pull−up of 1 kW to 3.3V,
CTOT = 45 pF, DVo = 90% to 10%
10
ns
Output Voltage at Power−up
VDD_PWRGD, VDDNB_PWRGD
pulled up to 5V via 2 kW
−
−
1.2
V
VDD_ PWRGD& VDDNB_PWRGD
= 5.0 V
−1.0
−
1.0
mA
Output Low Saturation Voltage
Output Leakage Current When High
0.3
V
ms
VDD_PWRGD Delay (rising)
DAC=TARGET to VDD_PWRGD
5
VDD_PWRGD Delay (falling)
From OCP or OVP
−
5
−
ms
Sourcing 500 mA
VCC –
0.2
−
−
V
PWM, PWMNB OUTPUTS
Output High Voltage
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NCP81022
NCP81022 (4+1) ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
MIN
TYP
MAX
Unit
Output Mid Voltage
No Load
1.9
2.0
2.1
V
Output Low Voltage
Sinking 500 mA
−
−
0.7
V
Rise and Fall Time
CL (PCB) = 50 pF,
DVo = GND to VCC
−
10
Gx = 2.0 V, x = 1−4, EN = Low
−1.0
−
PWM, PWMNB OUTPUTS
Tri−State Output Leakage
ns
1.0
mA
2/3/4 PHASE DETECTION FOR MAIN BRIDGE
4.7
CSN2, CSN3, CSN4 Pin Threshold Voltage
Phase Detect Timer
V
2.3
ms
SVC, SVD, SVT, PWROK
VDDIO
VIL
VDDIO Current
Nominal Bus voltage
1.14
Input Low Voltage
VDDIO = 1.95
1.95
V
35
%
100
mA
VIH
Input High Voltage
70
%
VHYS
Hysteresis Voltage
10
%
VOH
Output High Voltage
VDDIO
− 0.2
VDDIO
V
VOL
Output Low Voltage
0
0.2
V
−100
100
mA
4.0
pF
Leakage Current
Pad Capacitance
clock to data delay (Tco)
4
8.3
ns
Setup time (Tsu)
5
10
ns
Hold time (Thold)
5
10
ns
SMBus INTERFACE, SDA, SCL
Logic High Input Voltage
VIH(SDA, SCL)
Logic Low Input Voltage
VIL(SDA, SCL)
2.1
0.8
Hysteresis
SDA Output low voltage, VOL
V
500
ISDA = −6 mA
Input Current
−1
Input Capacitance
V
mV
0.4
V
1
mA
5.0
pF
Clock Frequency
400
kHz
SCL Falling Edge to SDA Valid Time
1.0
ms
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9
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
0
0
0
0
0
0
0
0
1.55000
00
0
0
0
0
0
0
0
1
1.54375
01
0
0
0
0
0
0
1
0
1.53750
02
0
0
0
0
0
0
1
1
1.53125
03
0
0
0
0
0
1
0
0
1.52500
04
0
0
0
0
0
1
0
1
1.51875
05
0
0
0
0
0
1
1
0
1.51250
06
0
0
0
0
0
1
1
1
1.50625
07
0
0
0
0
1
0
0
0
1.50000
08
0
0
0
0
1
0
0
1
1.49375
09
0
0
0
0
1
0
1
0
1.48750
0A
0
0
0
0
1
0
1
1
1.48125
0B
0
0
0
0
1
1
0
0
1.47500
0C
0
0
0
0
1
1
0
1
1.46875
0D
0
0
0
0
1
1
1
0
1.46250
0E
0
0
0
0
1
1
1
1
1.45625
0F
0
0
0
1
0
0
0
0
1.45000
10
0
0
0
1
0
0
0
1
1.44375
11
0
0
0
1
0
0
1
0
1.43750
12
0
0
0
1
0
0
1
1
1.43125
13
0
0
0
1
0
1
0
0
1.42500
14
0
0
0
1
0
1
0
1
1.41875
15
0
0
0
1
0
1
1
0
1.41250
16
0
0
0
1
0
1
1
1
1.40625
17
0
0
0
1
1
0
0
0
1.40000
18
0
0
0
1
1
0
0
1
1.39375
19
0
0
0
1
1
0
1
0
1.38750
1A
0
0
0
1
1
0
1
1
1.38125
1B
0
0
0
1
1
1
0
0
1.37500
1C
0
0
0
1
1
1
0
1
1.36875
1D
0
0
0
1
1
1
1
0
1.36250
1E
0
0
0
1
1
1
1
1
1.35625
1F
0
0
1
0
0
0
0
0
1.35000
20
0
0
1
0
0
0
0
1
1.34375
21
0
0
1
0
0
0
1
0
1.33750
22
0
0
1
0
0
0
1
1
1.33125
23
0
0
1
0
0
1
0
0
1.32500
24
0
0
1
0
0
1
0
1
1.31875
25
0
0
1
0
0
1
1
0
1.31250
26
0
0
1
0
0
1
1
1
1.30625
27
0
0
1
0
1
0
0
0
1.30000
28
0
0
1
0
1
0
0
1
1.29375
29
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10
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
0
0
1
0
1
0
1
0
1.28750
2A
0
0
1
0
1
0
1
1
1.28125
2B
0
0
1
0
1
1
0
0
1.27500
2C
0
0
1
0
1
1
0
1
1.26875
2D
0
0
1
0
1
1
1
0
1.26250
2E
0
0
1
0
1
1
1
1
1.25625
2F
0
0
1
1
0
0
0
0
1.25000
30
0
0
1
1
0
0
0
1
1.24375
31
0
0
1
1
0
0
1
0
1.23750
32
0
0
1
1
0
0
1
1
1.23125
33
0
0
1
1
0
1
0
0
1.22500
34
0
0
1
1
0
1
0
1
1.21875
35
0
0
1
1
0
1
1
0
1.21250
36
0
0
1
1
0
1
1
1
1.20625
37
0
0
1
1
1
0
0
0
1.20000
38
0
0
1
1
1
0
0
1
1.19375
39
0
0
1
1
1
0
1
0
1.18750
3A
0
0
1
1
1
0
1
1
1.18125
3B
0
0
1
1
1
1
0
0
1.17500
3C
0
0
1
1
1
1
0
1
1.16875
3D
0
0
1
1
1
1
1
0
1.16250
3E
0
0
1
1
1
1
1
1
1.15625
3F
0
1
0
0
0
0
0
0
1.15000
40
0
1
0
0
0
0
0
1
1.14375
41
0
1
0
0
0
0
1
0
1.13750
42
0
1
0
0
0
0
1
1
1.13125
43
0
1
0
0
0
1
0
0
1.12500
44
0
1
0
0
0
1
0
1
1.11875
45
0
1
0
0
0
1
1
0
1.11250
46
0
1
0
0
0
1
1
1
1.10625
47
0
1
0
0
1
0
0
0
1.10000
48
0
1
0
0
1
0
0
1
1.09375
49
0
1
0
0
1
0
1
0
1.08750
4A
0
1
0
0
1
0
1
1
1.08125
4B
0
1
0
0
1
1
0
0
1.07500
4C
0
1
0
0
1
1
0
1
1.06875
4D
0
1
0
0
1
1
1
0
1.06250
4E
0
1
0
0
1
1
1
1
1.05625
4F
0
1
0
1
0
0
0
0
1.05000
50
0
1
0
1
0
0
0
1
1.04375
51
0
1
0
1
0
0
1
0
1.03750
52
0
1
0
1
0
0
1
1
1.03125
53
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11
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
0
1
0
1
0
1
0
0
1.02500
54
0
1
0
1
0
1
0
1
1.01875
55
0
1
0
1
0
1
1
0
1.01250
56
0
1
0
1
0
1
1
1
1.00625
57
0
1
0
1
1
0
0
0
1.00000
58
0
1
0
1
1
0
0
1
0.99375
59
0
1
0
1
1
0
1
0
0.98750
5A
0
1
0
1
1
0
1
1
0.98125
5B
0
1
0
1
1
1
0
0
0.97500
5C
0
1
0
1
1
1
0
1
0.96875
5D
0
1
0
1
1
1
1
0
0.96250
5E
0
1
0
1
1
1
1
1
0.95625
5F
0
1
1
0
0
0
0
0
0.95000
60
0
1
1
0
0
0
0
1
0.94375
61
0
1
1
0
0
0
1
0
0.93750
62
0
1
1
0
0
0
1
1
0.93125
63
0
1
1
0
0
1
0
0
0.92500
64
0
1
1
0
0
1
0
1
0.91875
65
0
1
1
0
0
1
1
0
0.91250
66
0
1
1
0
0
1
1
1
0.90625
67
0
1
1
0
1
0
0
0
0.90000
68
0
1
1
0
1
0
0
1
0.89375
69
0
1
1
0
1
0
1
0
0.88750
6A
0
1
1
0
1
0
1
1
0.88125
6B
0
1
1
0
1
1
0
0
0.87500
6C
0
1
1
0
1
1
0
1
0.86875
6D
0
1
1
0
1
1
1
0
0.86250
6E
0
1
1
0
1
1
1
1
0.85625
6F
0
1
1
1
0
0
0
0
0.85000
70
0
1
1
1
0
0
0
1
0.84375
71
0
1
1
1
0
0
1
0
0.83750
72
0
1
1
1
0
0
1
1
0.83125
73
0
1
1
1
0
1
0
0
0.82500
74
0
1
1
1
0
1
0
1
0.81875
75
0
1
1
1
0
1
1
0
0.81250
76
0
1
1
1
0
1
1
1
0.80625
77
0
1
1
1
1
0
0
0
0.80000
78
0
1
1
1
1
0
0
1
0.79375
79
0
1
1
1
1
0
1
0
0.78750
7A
0
1
1
1
1
0
1
1
0.78125
7B
0
1
1
1
1
1
0
0
0.77500
7C
0
1
1
1
1
1
0
1
0.76875
7D
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12
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
0
1
1
1
1
1
1
0
0.76250
7E
0
1
1
1
1
1
1
1
0.75625
7F
1
0
0
0
0
0
0
0
0.75000
80
1
0
0
0
0
0
0
1
0.74375
81
1
0
0
0
0
0
1
0
0.73750
82
1
0
0
0
0
0
1
1
0.73125
83
1
0
0
0
0
1
0
0
0.72500
84
1
0
0
0
0
1
0
1
0.71875
85
1
0
0
0
0
1
1
0
0.71250
86
1
0
0
0
0
1
1
1
0.70625
87
1
0
0
0
1
0
0
0
0.70000
88
1
0
0
0
1
0
0
1
0.69375
89
1
0
0
0
1
0
1
0
0.68750
8A
1
0
0
0
1
0
1
1
0.68125
8B
1
0
0
0
1
1
0
0
0.67500
8C
1
0
0
0
1
1
0
1
0.66875
8D
1
0
0
0
1
1
1
0
0.66250
8E
1
0
0
0
1
1
1
1
0.65625
8F
1
0
0
1
0
0
0
0
0.65000
90
1
0
0
1
0
0
0
1
0.64375
91
1
0
0
1
0
0
1
0
0.63750
92
1
0
0
1
0
0
1
1
0.63125
93
1
0
0
1
0
1
0
0
0.62500
94
1
0
0
1
0
1
0
1
0.61875
95
1
0
0
1
0
1
1
0
0.61250
96
1
0
0
1
0
1
1
1
0.60625
97
1
0
0
1
1
0
0
0
0.60000
98
1
0
0
1
1
0
0
1
0.59375
99
1
0
0
1
1
0
1
0
0.58750
9A
1
0
0
1
1
0
1
1
0.58125
9B
1
0
0
1
1
1
0
0
0.57500
9C
1
0
0
1
1
1
0
1
0.56875
9D
1
0
0
1
1
1
1
0
0.56250
9E
1
0
0
1
1
1
1
1
0.55625
9F
1
0
1
0
0
0
0
0
0.55000
A0
1
0
1
0
0
0
0
1
0.54375
A1
1
0
1
0
0
0
1
0
0.53750
A2
1
0
1
0
0
0
1
1
0.53125
A3
1
0
1
0
0
1
0
0
0.52500
A4
1
0
1
0
0
1
0
1
0.51875
A5
1
0
1
0
0
1
1
0
0.51250
A6
1
0
1
0
0
1
1
1
0.50625
A7
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13
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
1
0
1
0
1
0
0
0
0.50000
A8
1
0
1
0
1
0
0
1
0.49375
A9
1
0
1
0
1
0
1
0
0.48750
AA
1
0
1
0
1
0
1
1
0.48125
AB
1
0
1
0
1
1
0
0
0.47500
AC
1
0
1
0
1
1
0
1
0.46875
AD
1
0
1
0
1
1
1
0
0.46250
AE
1
0
1
0
1
1
1
1
0.45625
AF
1
0
1
1
0
0
0
0
0.45000
B0
1
0
1
1
0
0
0
1
0.44375
B1
1
0
1
1
0
0
1
0
0.43750
B2
1
0
1
1
0
0
1
1
0.43125
B3
1
0
1
1
0
1
0
0
0.42500
B4
1
0
1
1
0
1
0
1
0.41875
B5
1
0
1
1
0
1
1
0
0.41250
B6
1
0
1
1
0
1
1
1
0.40625
B7
1
0
1
1
1
0
0
0
0.40000
B8
1
0
1
1
1
0
0
1
0.39375
B9
1
0
1
1
1
0
1
0
0.38750
BA
1
0
1
1
1
0
1
1
0.38125
BB
1
0
1
1
1
1
0
0
0.37500
BC
1
0
1
1
1
1
0
1
0.36875
BD
1
0
1
1
1
1
1
0
0.36250
BE
1
0
1
1
1
1
1
1
0.35625
BF
1
1
0
0
0
0
0
0
0.35000
C0
1
1
0
0
0
0
0
1
0.34375
C1
1
1
0
0
0
0
1
0
0.33750
C2
1
1
0
0
0
0
1
1
0.33125
C3
1
1
0
0
0
1
0
0
0.32500
C4
1
1
0
0
0
1
0
1
0.312875
C5
1
1
0
0
0
1
1
0
0.31250
C6
1
1
0
0
0
1
1
1
0.30625
C7
1
1
0
0
1
0
0
0
0.30000
C8
1
1
0
0
1
0
0
1
0.29375
C9
1
1
0
0
1
0
1
0
0.28750
CA
1
1
0
0
1
0
1
1
0.28125
CB
1
1
0
0
1
1
0
0
0.27500
CC
1
1
0
0
1
1
0
1
0.26875
CD
1
1
0
0
1
1
1
0
0.26250
CE
1
1
0
0
1
1
1
1
0.25625
CF
1
1
0
1
0
0
0
0
0.25000
D0
1
1
0
1
0
0
0
1
0.24375
D1
www.onsemi.com
14
NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
1
1
0
1
0
0
1
0
0.23750
D2
1
1
0
1
0
0
1
1
0.23125
D3
1
1
0
1
0
1
0
0
0.22500
D4
1
1
0
1
0
1
0
1
0.21875
D5
1
1
0
1
0
1
1
0
0.21250
D6
1
1
0
1
0
1
1
1
0.20625
D7
1
1
0
1
1
0
0
0
0.20000
D8
1
1
0
1
1
0
0
1
0.19375
D9
1
1
0
1
1
0
1
0
0.18750
DA
1
1
0
1
1
0
1
1
0.18125
DB
1
1
0
1
1
1
0
0
0.17500
DC
1
1
0
1
1
1
0
1
0.16875
DD
1
1
0
1
1
1
1
0
0.16250
DE
1
1
0
1
1
1
1
1
0.15625
DF
1
1
1
0
0
0
0
0
0.15000
E0
1
1
1
0
0
0
0
1
0.14375
E1
1
1
1
0
0
0
1
0
0.13750
E2
1
1
1
0
0
0
1
1
0.13125
E3
1
1
1
0
0
1
0
0
0.12500
E4
1
1
1
0
0
1
0
1
0.11875
E5
1
1
1
0
0
1
1
0
0.11250
E6
1
1
1
0
0
1
1
1
0.10625
E7
1
1
1
0
1
0
0
0
0.10000
E8
1
1
1
0
1
0
0
1
0.09375
E9
1
1
1
0
1
0
1
0
0.08750
EA
1
1
1
0
1
0
1
1
0.08125
EB
1
1
1
0
1
1
0
0
0.07500
EC
1
1
1
0
1
1
0
1
0.06875
ED
1
1
1
0
1
1
1
0
0.06250
EE
1
1
1
0
1
1
1
1
0.05625
EF
1
1
1
1
0
0
0
0
0.05000
F0
1
1
1
1
0
0
0
1
0.04375
F1
1
1
1
1
0
0
1
0
0.03750
F2
1
1
1
1
0
0
1
1
0.03125
F3
1
1
1
1
0
1
0
0
0.02500
F4
1
1
1
1
0
1
0
1
0.01875
F5
1
1
1
1
0
1
1
0
0.01250
F6
1
1
1
1
0
1
1
1
0.00625
F7
1
1
1
1
1
0
0
0
OFF
F8
1
1
1
1
1
0
0
1
OFF
F9
1
1
1
1
1
0
1
0
OFF
FA
1
1
1
1
1
0
1
1
OFF
FB
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NCP81022
Table 1. SVI2 VID CODES
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage (V)
HEX
1
1
1
1
1
1
0
0
OFF
FC
1
1
1
1
1
1
0
1
OFF
FD
1
1
1
1
1
1
1
0
OFF
FE
1
1
1
1
1
1
1
1
OFF
FF
1
2
3
4
5
6
7
8
State
DC_IN
Boot_VID
VDDIO
SVC
SVD
SVT
VOTF
Telemetry Telemetry
COMPLETE
ENABLE
VDD & VDDNB
VDD_PWGD
VDDNB_PWRGD
9
RESET_L
10
PWROK
Figure 3. Start Up Timing Diagram
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NCP81022
SVI2 INTERFACE
SVD SERIAL PACKET BIT DESCRIPTION
Bit
Default
Description
1:5
11000
6
1
VDD domain selector bit, if set then the following two data bytes contain the VID for VDD,
the PSI state for VDD and the loadline slope trim and offset
7
0
VDDNB domain selector bit, if set then the following two data bytes contain the VID for
VDD, the PSI state for VDDNB and the loadline slope trim and offset
8
0
9
0
ACK
10
0
PSI0 power state indicator level 0. when this signal is asserted the NCP81022 is in a lower
power state, and phase shedding is initialized.
11:17
XXXXXXX
Start code
VID code [7:1] see table 2
18
0
ACK
19
X
VID code LSB [0] see table 2
20
PSI1, when this bit is asserted the NCP81022 is in a low power state and operated in diode
mode emulation mode
21
1
TFN, this is an active high signal that allows the processor to control the telemetry functionality of the NCP81022.
22:24
011
Loadline slope Trim [2:0]
25:26
10
Offset Trim [1:0]
27
0
ACK
1
10
9
SVC
SVD
1
1
0
0
START SEQUENCE
0
DOMAIN
SELECTION
0+
ACK
VID CODE BIT 7:1
PSI0
18
ACK
27
VID
CODE
BIT 0
PSI1
TFN
LOADLINE
SLOPE TRIM
OFFSET
TRIM
STOP
ACK
Figure 4. SVD Packet Structure
SVI2 Interface
The NCP81022 is design to accept commands over AMD’s SVI2 bus. The communication is accomplished using three lines,
a data line SVD, a clock line SVC and a telemetry line SVT. The SVD line can be used not only to set the voltage level of the
Main rail and North bridge rail, but can also set the load line slope, programmed offset and also the PSI (power state indicator
bits). The SVT line from the NCP81022 communicates voltage, current and status updates back to the processor.
Power State Indicator (PSI)
The SVI2 protocol defines two PSI levels, PSI0 and PSI1. These are active low signals which indicate when the NCP81022
can enter low power states to improve system efficiency and performance. Increasing levels of PSI state indicates low current
consumption of the processor.
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NCP81022
It is possible for the processor to assert PSI0 and PSI1 out of order i.e. to enter PSI1 prior to PSI0 however; PSI0 always
takes priority over PSI1.
With increasing load current demand the number of active phases increase instantaneous. The NCP81022 can potentially
change from single−phase to user−configured multiphase operation in a single step, depending on PSI state.
PSI0 is activated once the system power is in the region of 20−30 A, in this mode the NCP81022 controller reduces the
number of phases in operation thus reducing switching losses of the system. If the current continues to drop to 1−3 A PSI1 is
asserted and the NCP81022 enters diode emulation mode, operating in single phase mode. See below table for PSI mode
operation.
PSI0#
PSI1#
Phase
0
0
1−Phase DCM
0
1
1−Phase CCM
1
0
Full phase mode
1
1
Full phase mode
Telemetry
The TFN bit along with the VDD and VDDNB domain selectors are used to change the functionality of the telemetry. See
table below for description.
TFN = 1
VDD
VDDNB
0
1
Telemetry is in voltage and current mode. V&I is sent back for both VDD and VDDNB rails
0
0
Telemetry is in voltage only mode. Voltage information is sent back for both VDD and VDDNB rails
1
0
Telemetry is disabled
1
1
Reserved for future use
Description
Loadline Slope
Within the SVI2 protocol the NCP81022 controller has the ability to manipulate the loadline slope of both the VDD and
VDDNB rails independently of each other, when Enable and PWROK are asserted. Loadline slope trim information is
transmitted in 3 bits , 22:24, over the SVD packet. Please see table below for description.
Loadline Slope
Trim [0:2]
Description
000
Remove all LL droop from output
001
LL slope 12.9%
010
LL slope 25.8%
011
LL slope (Default 38.7%)
100
LL slope 51.6%
101
LL slope 64.8%
110
LL slope 77.4%
111
LL slope 90.2%
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NCP81022
Offset Trim
Within the SVI2 protocol the NCP81022 controller has the ability to manipulate the offset of both the VDD and VDDNB
rails independently of each other, when Enable and PWROK are asserted. Descriptions of offset codes are described below.
Offset Trim [1:0]
Description
00
0 offset
01
Initial offset −25 mV
10
Use initial offset (default)
11
Initial offset +25 mV
SVT Serial Packet
The NCP81022 has the ability to sample and report voltage and current for both the VDD and VDDNB domain. This
information is reported serially over the SVT line which is clocked using the processor driven SVC line. When the PWROK
is deasserted, the NCP81022 is not collecting or reporting telemetry information. When PWROK is asserted, the telemetry
information reported back is as described below. If the NCP81022 is configured in voltage only telemetry then the sampled
voltage for VDD and the sampled voltage for the VDDNB are sent together in every SVT telemetry packet.
Parameter
Value
Unit
9
Bits
Maximum reporting Voltage
3.15
V
Minimum reported Voltage
0.00
V
Voltage resolution
6.25
mV
Voltage accuracy from 1.2 V to 800 mV
±1
LSB
Voltage accuracy for voltages greater than 1.2 V and less than 800 mV
±2
LSB
Recommended voltage moving average window size
50
ms
Minimum voltage only telemetry reporting rate
20
kHz
Number of voltage Bits
Number of bits in current data
Max reported current (FFh = OCP)
Max reported current (00h)
8
Bits
100
% of IDD spike _ocp
0
% of IDD spike _ocp
If the NCP81022 is configured in voltage and current mode then the samples voltage and current information for VDD is
sent out in one SVT telemetry packet while the voltage and current information for the VDDNB domain is sent out in the next
SVT telemetry packet. The telemetry report rate while the NCP81022 is in current and voltage mode, is double that which is
observed in voltage only mode. The reported voltage and current are moving average representations.
Bit
Description
0
SVT0
1
SVT1
2
Bit
See table below for
description
10
Voltage Bit 0
11
Voltage Bit 8 ‘0’ in V and I mode
Voltage Bit 8
12
Voltage or current Bit 7
3
Voltage Bit 7
13
Voltage or current Bit 6
4
Voltage Bit 6
14
Voltage or current Bit 5
5
Voltage Bit 5
15
Voltage or current Bit 4
6
Voltage Bit 4
16
Voltage or current Bit 3
7
Voltage Bit 3
17
Voltage or current Bit 2
8
Voltage Bit 2
18
Voltage or current Bit 1
9
Voltage Bit 1
19
Voltage or current Bit 0
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NCP81022
Description
SVT0, SVT1
0,0
Telemetry packet belongs to the VDD domain and in V&I mode.
0,1
Telemetry packet belongs to the VDDNB domain and in V&I mode.
1,0
VOTF Complete, a stop immediately follows these two bits during the next SVC high period. Telemetry data does
not follow this bit configuration
1,1
Telemetry package in voltage representation only. (default)
SVI2 VR to Processor Data Communication
As described previously the NCP81022 has the ability to send digitally encoded voltage and current values for the VDD and
VDDNB domains to the processor, it also has the capability to send VID On The Fly (VOTF) complete mechanism. The
processor uses this information as an indicator for when the VDD, VDDNB are independently, or collectively, at the requested
stepped−up VID voltage. The VOTF complete mechanism is not used for VID changes to lower or for repeated VID codes.
VOTF Complete is transmitted as an SVT packet. Since a VOTF request could apply to one or two voltage domains, rules
are suggested below to handle these cases.
VID Change
Offset Change
Loadline Change
VOFT Timing
Force or Decay Change
UP
Unchanged
Unchanged
After slewing
Force voltage change
Down
Unchanged
Unchanged
NO VOTF
Voltage Decay
X
UP
Unchanged
After slewing
Force voltage change
X
Down
Unchanged
After slewing
Force voltage change
X
Unchanged
Up
After slewing
Force voltage change
X
Unchanged
Down
After slewing
Force voltage change
SVC
STOP
SVD
SVT
VID − RLL * IOUT +−OFFSET − TOB
VDD or
VDDNB
Tsc
Slew Rate Measured here
Figure 5. Slew Rate Timing
*Max Tsc =5 ms
•
•
•
•
•
Telemetry takes priority over VOTF Complete signals
VOTF complete can be sent if the net voltage change is 0 or negative
VOTF Complete is only used to indicate that a rail(s) has finish slewing to a higher voltage.
If a VOTF request for a higher voltage is sent for both VDD and VDDNB rails, but only domain will go up in voltage
then the returned VOTF Complete will indicate that the increasing domain has finished slewing
If the processor starts a VOTF request but the VOTF is incomplete then the NCP81022 will not sent the VOTF
Complete sequence until after the new VOTF request.
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NCP81022
• If the processor is sending a SVD packet when the NCP81022 is sending telemetry packet to send, then the NCP81022
•
waits to send the telemetry until after the SVD packet has stopped transmitting.
If the processor stops sending the SVD packet while the NCP81022 is sending telemetry then no action has to be taken,
the NCP81022 shifts in the new SVD packet and finishes sending the telemetry while the processor is sending the SVD
packet.
SVT packets are not sent while PWROK is deasserted
•
• The NCP81022 will not collect or send telemetry data when telemetry functionality is disabled by the TFN bits
The following timing diagrams cover the SVC, SVD and SVT timing when PWROK is asserted and data is being transmitted,
the table that follows defines the min and max value for each timing specification.
SVC
SVD
HiZ
TSTART
TLow
THigh
HiZ
THold TQuiet TSetup TStop
TQuiet TSetup
TPeriod
THold
TZack
SVC
SVD
TSetup
THold
Figure 6. SDV SVC Timing
SVC
SVT
Tsetup
Tstop
Figure 7. SVT Stop Timing
SVC
SVD/SVT
TReStart
Figure 8. SVD or SVT Re−Start Timing
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NCP81022
SVC
SVD
SVT
TRISING EDGE SVCto SVD−START
TSVD−STOPto SVT−START
Figure 9. SVT start and Stop timing
Table 2. SVI2 BUS TIMING PARAMETERS FOR 3.33 MHz OR 20 MHz OPERATION
Parameter
TPERIOD
SVC Frequency
Min
Max
Unit
50
TDC
ns
TDC
20
MHz
THIGH SVC High Time
20
ns
TLow SVC Low Time
30
ns
Tsetup (SVD, SVT Setup time to SVC rise edge)
5
10
ns
THold ( SVD, SVT Hold time from SVC falling edge)
5
10
ns
T Quiet (Time neither processor nor VR is driving the SVD line)
10
ns
TZACK ( total time processor tristates SVD)
50
ns
TSTART
20
ns
TSTOP
10
ns
T ReSTART (Time Between Stop and Start on SVD)
50
ns
T ReSTART (Time Between Stop and Start on SVD)
50
ns
T SVD−STOP to SVT−START (Time Between SVD stop and SVT Start)
80
ns
TRising Edge SVC to SVTD−Start (Time between Rising Edge of SVC after last SVT bit to SVD
start)
20
ns
SVC, SVD, SVT Fall Time VOH_DC to VOL_DC
1
ns
SVC, SVD, SVT Rise Time VOH_DC to VOL_DC
1
ns
T Skew−SVC−SVD The skew between SVC, SVD as seen at the NCP81022; dictated by layout
and tested by simulation
1
ns
T Skew−SVC−SVD The skew between SVC, SVD as seen at the Processor; dictated by layout
and tested by measurement
2
ns
T Propagation The propagation delay of SVC, SVD, SVT; measured from the transmitter to the
receiver
2
ns
5
ns
SVC glitches filter width. NCP81022’s glitch filter will reject any SVC transition that persists for
shorter periods than this
3
Slew Rate
Slew rate is programmable on power up; a resistor from the SR pin to ground sets the slew rate. Each rail can be programmed
independently between 10 mV/ms, see table below for resistor values.
Slew Rate
Resistance (W)
10 mv/ms
10k
20 mv/ms
25k
30 mv/ms
45k
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NCP81022
BOOT VOLTAGE PROGRAMMING
The NCP81022 has a VBOOT voltage register that can be externally programmed for both Main Rail and North Bridge
boot−up output voltage. The VBOOT voltage can be programmed when PWROK is deasserted, through the logic levels present
on SVC and SVD. The table below defines the Boot−VID codes
BOOT VOLTAGE TABLE:
SVC
SVD
Boot Voltage
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
ADDRESSING PROGRAMMING
The NCP81102 supports eight possible SMBus Addresses. Pin 28 (PWM4) is used to set the SMBus Address. On power up
a 10 mA current is sourced from this pin through a resistor connected to this pin and the resulting voltage is measured. The Table
below provides the resistor values for each corresponding SMBus Address. The address value is latched at startup.
Table 3. SMBus ADDRESS
Resistor Value
SMBus (Hex)
10k
20
25k
21
45k
22
70k
23
95k
24
125k
25
165k
26
220k
27
Programming the ICC_Max
A resistor to ground on the IMAX pin program the ICC_Max value at the time the NCP81022 in enabled. 10 mA is sourced
from this pin to generate a voltage on the program resistor. The resistor value should be no less than 10k.
R ICC_MAX +
(2 * ICC_MAX)
(10m * 256)
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to:
V DIFF + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ ) ǒV DROOP * V CSREFǓ
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high bandwidth transient performance. A standard type 3 compensation
circuit is normally used to compensate the system.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense that phase current for current balance and per phase OCP protection
during soft−start. The inputs to the CSREF and CSPx pins are high impedance inputs. It is recommended that any external filter
resistor RCSN not exceed 10 kW to avoid offset issues with leakage current. It is also recommended that the voltage sense
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NCP81022
R CSN +
CSREF
RCSN
CSPx
element be no less than 0.5 mW for accurate current balance, user care should be taken in board design if lower DCR inductor
are used as this may affect the current balance in light load conditions. Fine tuning of this time constant is generally not required.
CCSN
L PHASE
VOUT
C CSN * DCR
DCR
LPHASE
1
2
Figure 10. Differential Current Feedback
The individual phase current is summed into to the PWM comparator feedback in this way current is balanced is via a current
mode control approach.
Total Current Sense Amplifier
The NCP81022 uses a patented approach to sum the phase currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP
and CSREF. The Ref (n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground.
The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the
inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter
time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature.
Figure 11. Current Sense Amplifier
The DC gain equation for the current sensing:
Rcs1*Rth
V CSCOMP−CSREF + −
Rcs2 ) Rcs1)Rth
Rph
* ǒIout Total * DCRǓ
Set the gain by adjusting the value of the Rph resistors. The DC gain should set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100mV then it is recommended to increase the gain of the CSCOMP amp and add a
resister divider to the Droop pin filter. This is required to provide a good current signal to offset voltage ratio for the ILIM pin.
When no droop is needed, the gain of the amplifier should be set to provide ~100 mV across the current limit programming
resistor at full load. The values of Rcs1 and Rcs2 are set based on the 220k NTC and the temperature effect of the inductor and
should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set
with the droop filter divider.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
FZ +
FP +
DCR@25° C
2 * PI * L Phase
1
2 * PI * ǒRcs2 )
Rcs1*Rth@25° C
Rcs1)Rth@25° C
Ǔ * (Ccs1 ) Ccs2)
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NCP81022
Programming the Current Limit
The current−limit thresholds are programmed with a resistor between the ILIM and CSCOMP pins. The ILIM pin mirrors
the voltage at the CSREF pin and the current limit comparators. Set the value of the current limit through CSREF− CSCOMP
voltage at IoutLIMIT condition as shown below:
Rcs1*Rth
Rcs1)Rth
Rph
Rcs2)
R ILIM +
* ǒIout LIMIT * DCRǓ
10 mA
or R ILIM +
V CSREF−CSCOMP@ILIMIT
10 mA
Programming DROOP and DAC feedforward
Programming Rdroop sets the gain of the DAC feed−forward and Cdroop provides the time constant to cancel the time
constant of the system per the equations below. Cout_total is the total output capacitance of the system design.
Cdroop
Rdroop
Rdroop = (Cout_total)*loadline*453.6*106
Cdroop = (loadline*(Cout_total))/Rdroop
Figure 12. Droop RC
Programming IOUT
The IOUT pin sources a current equal to the ILIM sink current gained by the IOUT Current Gain. The voltage on the IOUT
pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal
to ICCMAX generates a 2 V signal on IOUT. A pull−up resistor from 5 V VCC can be used to offset the IOUT signal positive
if needed.
2.0 V * R LIMIT
R IOUT +
Rcs1*Rth
Rcs1)Rth
Rph
Rcs2)
10 *
* ǒIout ICC_MAX * DCRǓ
Precision Oscillator
A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit.
This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator can also be programmed over the SMBus
interface through register 0xF7. The oscillator frequency range is between 200 kHz/phase to 1 MHz/phase in 32 steps. The
ROSC pin provides approximately 2 V out and the source current is mirrored into the internal ramp oscillator.
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NCP81022
Figure 13. NCP81022 Operating Frequency vs. Rosc
Figure 14. PWM vs. Register Code
The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input
voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other and the signal phase
rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current.
Programming the Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is a high impedance input
when the controller is disabled.
The PWM ramp time is changed according to the following,
V RAMPpk+pkPP + 0.1 * V VRMP
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NCP81022
Vin
Vramp_pp
Comp−IL
Duty
Figure 15. Ramp Feedforward
Programming TRBST#
The TRBST# pin provides a signal to offset the output after load release overshoot. This network should be fine tuned during
the board tuning process and is only necessary in systems with significant load release overshoot. The TRBST# network allows
maximum boost for low frequency load release events to minimize load release ringing back undershoot. The network time
constants are set up to provide a TRBST# roll of at higher frequencies where it is not needed. Cboost1*Rbst1 controls the time
constant of the load release boost. This should be set to counter the under shoot after load release. Rbst1+ Rbst2 controls the
maximum amount of boost during rapid step loading. Rbst2 is generally much larger then Rbst1. The Cboost2*Rbst2 time
constant controls the roll off frequency of the TRBST# function.
Cboost2
Rbst1
Rbst3
Rbst2
FB
TRBST
Cboost1
Figure 16. TRBST Circuit
PWM Comparators
During steady state operation, the duty cycle is centered on the valley of the triangle ramp waveform and both edges of the
PWM signal are modulated. During a transient event the duty will increase rapidly and proportionally turning on all phases
as the error amp signal increases with respect to the ramps to provide a highly linear and proportional response to the step load.
Phase Detection Sequence for Main Rail
During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry
monitoring the CSN Pins. Normally, NCP81022 main rail operates as a 4−phase PWM controller. Connecting CSN4 pin to
VCC programs 3−phase operation, connecting CSN2 and CSN4 pin to VCC programs 2−phase operation, connecting CSN2,
CSN3 and CSN4 pin to VCC programs 1−phase operation. Prior to soft start, while ENABLE is high, CSN4 to CSN2 pins sink
approximately 50 mA. An internal comparator checks the voltage of each pin versus a threshold of 4.5V. If the pin is tied to
VCC, its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold.
PWM1 is low during the phase detection interval, which takes 30us. After this time, if the remaining CSN outputs are not pulled
to VCC, the 50 mA current sink is removed, and NCP81022 main rail functions as normal 4 phase controller. If the CSNs
are pulled to VCC, the 50 mA current source is removed, and the outputs are driven into a high impedance state.
The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP5901 and
NCP5911. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition,
more than one PWM output can be on at the same time to allow overlapping phases.
PHASE DETECTION
Number of
phases
Programming pin CSNX
Unused pins
4+1
All CSN pin connected normally.
No unused pins
3+1
Connect CSN4 to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4
Ground CSP4
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NCP81022
PHASE DETECTION
Number of
phases
Programming pin CSNX
Unused pins
2+1
Connect CSN2 and CSN4 to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4 and PWM2
Ground CSP4, and CSP2
1+1
Connect CSN2, CSN3 and CSN4 to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4, PWM3 and PWM2
Ground CSP4, CSP3 and CSP2
4+0
CSN1NB pulled to VCC through 2k resistor.
Float PWM1NB,Ilim NB, Diffout NB, Comp NB, TRBSTNB and CScompNB
Ground IoutNB, DroopNB, FBNB, CSSUMNB,CSPNB and VDDNB
All other CSN pins connected normally.
3+0
Connect CSN4 and CSN1NB to VCC through a 2k resistor.
All other CSN pins connected normally.
Float PWM4 PWM1NB,Ilim NB, Diffout NB, Comp
NB, TRBSTNB and CScompNB
Ground CSP4, IoutNB, DroopNB, FBNB, CSSUMNB,CSPNB and VDDNB
2+0
Connect CSN2, CSN4 and CSN1NB to VCC through a 2k
resistor.
All other CSN pins connected normally.
Float PWM4, PWM2, PWM1NB,Ilim NB, Diffout NB,
Comp NB, TRBSTNB and CScompNB
Ground CSP4, CSP2 IoutNB, DroopNB, FBNB,
CSSUMNB,CSPNB and VDDNB
1+0
Connect CSN2, CSN3, CSN4 and CSN1NB to VCC through
a 2k resistor.
CSN1 pin connected normally.
Float PWM4, PWM3, PWM2, PWM1NB,Ilim NB,
Diffout NB, Comp NB, TRBSTNB and CScompNB
Ground CSP4, CSP3, CSP2 IoutNB, DroopNB, FBNB, CSSUMNB,CSPNB and VDDNB
Protection Features
Output voltage out of regulation is defined as either a UVP or OVP event. The protection mechanism in case of either type
of fault is described in this section.
Gate Driver UVLO Protection
The NCP811022 monitors Vcc and DRON signals during UVLO restart, as shown in Figure 17.
VCC
If DRON is pulled low the
controller will hold off its
startup
DAC
UVLO
Gate Driver Pulls DRON
Low during driver UVLO
and Calibration
DRON
Figure 17. Gate Driver UVLO Restart
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined slew rate programmed on startup. The controller enables and sets the PWM signal to the 2.0 V MID state to
indicate that the drivers should be in diode mode. The COMP pin released to begin soft−start. The DAC will ramp from Zero
to the target DAC codes and the PWM outputs will begin to fire. Each phase will move out of the MID state when the first PWM
pulse is produced preventing the discharge of a pre−charged output.
www.onsemi.com
28
NCP81022
Figure 18. Soft−Start Sequence
Over Current Latch− Off Protection
The NCP81022 support IDDSPIKE, an amount of current drawn by the processor that exceeds the sustained design current
limit, TDC, for a thermally significant period of time
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