NCP81141
Single-Phase Controller
with SVID Interface for
Desktop and Notebook CPU
Applications
The NCP81141 Single−Phase buck solution is optimized for Intel
VR12.6 compatible CPUs. The controller combines true differential
voltage sensing, differential inductor DCR current sensing, input
voltage feed−forward, and adaptive voltage positioning to provide
accurately regulated power for both Desktop and Notebook
applications. The single phase controller uses DCR current sensing
providing the fastest initial response to dynamic load events at reduced
system cost.
The NCP81141 incorporates an internal MOSFET driver for
improved system efficiency. High performance operational error
amplifiers are provided to simplify compensation of the system.
Patented Dynamic Reference Injection further simplifies loop
compensation by eliminating the need to compromise between
closed−loop transient response and Dynamic VID performance.
Patented Total Current Summing provides highly accurate digital
current monitoring.
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MARKING
DIAGRAM
1
QFN28
CASE 485AR
A
L
Y
W
G
NCP
81141
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Meets Intel™ VR12.6 Specifications
High Performance Operational Error Amplifier
Digital Soft Start Ramp
Dynamic Reference Injection
“Lossless” DCR Current Sensing
Adaptive Voltage Positioning (AVP)
Switching Frequency Range of 250 kHz – 1 MHz
VIN Range 4.5 V − 25 V
Startup into Pre−Charged Load While Avoiding False OVP
Vin Feed Forward Ramp Slope
Over Voltage Protection (OVP) and Under Voltage Protection (UVP)
Over Current Protection (OCP)
VR−RDY Output with Internal Delays
These Devices are Pb−Free and are RoHS Compliant
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Applications
• Desktop and Notebook Processors
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 2
1
Publication Order Number:
NCP81141/D
NCP81141
NCP81141
Figure 1. Block Diagram for NCP81141
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2
C94
0.1uF
J29
J27
2
100
R48
place close to L1
R32
8.25K
TSENSE
2
0.0
1
R3
1
2PIN
2
1
0.0
2
R2
1
J13
100
2
R34
1
2
2
2
ILIM
J8
J23
1
1
D NP
1
R 158
2
R156 54.9
1
D NP
1
R 159
2
R155 64.9
1
{4}
75
R157
1
D NP
1
1
R18
13.7K
J42
C155
1.5nF
2.1K
2
VSP {4}
C 51
1nF
R 68
{4}
7
1
220K
R T130
R131
75.0K
1
1
place close to L1
C 156
560pF
J45
{4} VR_RD Y
{4} ENABLE
J47
U16A
N L37W Z07
510pF
C67
VSN
SER_EN
R187
390
+5V_IN
SDIO {5}
SCLK {5}
ALERT# {5}
V _1P05_V CCP
J1
5PIN
1
2
SER_VR _RD Y
2
1
8
4
2
1
J26
J61
J63
J62
1
V5S
1
1
1
1
2
1
CSSUM
R140
1
BST1
H G1
SW1
LG1
105K
2
C79
1uF
R71 2
2
2
26.1K
2
C61 0.1uF
J56
1
R 38
1
VR_HOT
SDIO
ALERT#
SC LK
VR_RDY
{4} VR_HOT
R132
165K
C86
1uF
1
2
SER_EN
VSENSE
R125
0.0
JP5
ETCH
RT126
100K
VCC U
{5} VCC _SEN SE
{5} VSS_SEN SE
1
1
3
5
7
9
11
13
15
17
19
1
2
2
1
1
2
R 160
2
2
1
J19
SW1
LG1
BST1
VSP
VSN
IOU T
ROSC
COMP
FB
DIFFOUT
CSCOMP
ILIM
1
1
2
3
4
5
6
7
29
28
27
26
25
24
23
22
SW N1
CSP1
CSREF
H G1
EN ABLE
VR HOT
SD IO
ALER T
SC LK
VR _R DY
VR MP
U6
NCP81141
{3}
1
J11
R4
10nF
C 82
VRMP
VBOOT
R184
30.1K
ILIM
IOUT
C SC OMP
CSSUM
CSR EF
IMAX
PVCC
EPAD
VCC
VSP
VSN
DIFF OUT
FB
C OMP
R OSC
2
4
6
8
10
12
14
16
18
20
1
2
0.0
VD C
1
R40
1.0K
15
16
17
18
19
20
21
2
C SN 1 {3}
VCC3
V5S
CSREF
CSSUM
J28
4.7uF
C31
R 189
100k
1
2
1 TSENSE
J32
R154
50k
J39
1 DIFFOUT
1
2
V_1P05_V CCP
1
2
C56
1nF
1.00K
2 1
ROSC
R37
1
R 50 49.9
J40
2
1 FB
J59
20PIN 2R OW
1
1
2
2
1
1
1
2
C SC OMP
2
BST
HG
SW
PGN D
LG
T SENSE
VBOOT
8
9
10
11
12
13
14
1
2
Figure 2. Controller Application Schematic
1
3
1
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2
J2
5PIN
2
R 43 3.01K
1
C 57
1
2
10pF
1
J41
NCP81141
C OMP
LG1
SW1
HG1
0.0
2
1
2
C185
22uF
C212
22uF
C42
22uF
LG1
SW1
HG1
4
C186
22uF
C213
22uF
C43
22uF
Q4
NTMFS4852N
4
DRVL1
TP17
TP14
DRVH1
C4
0.22uF
1
R164
1
C187
22uF
C226
22uF
C210
22uF
3
2
1
BST1
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
C188
22uF
C227
22uF
C45
22uF
C189
22uF
C176
22uF
C46
22uF
C190
22uF
C177
22uF
C47
22uF
1
C191
22uF
C183
22uF
C50
22uF
SW1
TP8
C101
1nF
1
1
C2
10uF
C192
22uF
C184
22uF
C222
22uF
C193
22uF
L1
560nH
MCP1040LR56C
1
2
C1
10uF
1
2
1
5
6
7
8
3
2
1
5
6
7
8
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
C194
22uF
C3
10uF
1
2
VCCU
dnp
+ C218
ETCH
2
JP14
1
VCCU
ETCH
2
C201
10uF
JP13
1
VDC
1
2
1
2
1
2
1
2
1
2
dnp
+ C219
SWN1 {2}
CSN1 {2}
1
2
2
1
2
1
2
1
2
1
2
2
1
2
Figure 3. Power Stage Typical Schematic
2
dnp
+ C220
1
2
4
dnp
+ C223
1
2
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dnp
+ C211
1
2
Q2
NTMFS4821N
DNP
+ C208
NCP81141
VCC
VSP
VSN
DIFFOUT
FB
COMP
ROSC
NCP81141
28
27
26
25
24
23
22
ENABLE
1
21
ILIM
VR_HOT
2
20
IOUT
SDIO
3
19
CSCOMP
18
CSSUM
NCP81141
ALERT
4
TAB: GROUND
IMAX
VRMP
7
15
PVCC
8
9
10
11
12
13
14
VBOOT
16
TSENSE
6
LG
VR_RDY
PGND
CSREF
SW
17
HG
5
BST
SCLK
Figure 4. NCP81141 Pin Configurations
NCP81141 SINGLE ROW PIN DESCRIPTIONS
Pin No.
Symbol
1
ENABLE
2
VR_HOT#
3
SDIO
4
ALERT#
Description
Logic input. Logic high enables both outputs and logic low disables both outputs
Thermal logic output for over temperature
Serial VID data interface
Serial VID ALERT#
5
SCLK
6
VR_RDY
Serial VID clock
7
VRMP
8
BST
High−Side bootstrap supply for phase 1
9
HG
High side gate driver output for phase 1
10
SW
Current return for high side gate driver 1
11
PGND
12
LG
13
TSENSE
Temp Sense input for the single phase converter
14
VBOOT
An input pin to adjust the boot−up voltage. During start up it is used to program VBOOT with a
resistor to ground
15
PVCC
Power Supply for gate driver, recommended decoupling 2.2 mF
16
IMAX
Imax Input Pin. During start up it is used to program IMAX with a resistor to ground
17
CSREF
Total output current sense amplifier reference voltage input
18
CSSUM
Inverting input of total current sense amplifier
19
CSCOMP
20
IOUT
Total output current monitor
21
ILIM
Over current shutdown threshold setting. Resistor to CSCOMP to set threshold
Open drain output. High indicates that the output is regulating
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used
to control the ramp of PWM slope
Power Ground for gate driver
Low−Side gate driver output for phase 1
Output of total current sense amplifier
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5
NCP81141
NCP81141 SINGLE ROW PIN DESCRIPTIONS
Pin No.
Symbol
Description
22
ROSC
A resistance from this pin to ground programs the oscillator frequency
23
COMP
Output of the error amplifier and the inverting input of the PWM comparator
24
FB
25
DIFFOUT
26
VSN
Inverting input to differential remote sense amplifier
27
VSP
Non−inverting input to the differential remote sense amplifier
28
VCC
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
29
FLAG/GND
Error amplifier voltage feedback
Output of the differential remote sense amplifier
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6
NCP81141
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
VMAX
VMIN
COMP
VCC + 0.3 V
−0.3 V
CSCOMP
VCC + 0.3 V
−0.3 V
VSN
GND + 300 mV
GND – 300 mV
DIFFOUT
VCC + 0.3 V
−0.3 V
VR_RDY
VCC + 0.3 V
−0.3 V
VCC
6.5 V
−0.3 V
ROSC
VCC + 0.3 V
−0.3 V
IOUT
2.0 V
−0.3 V
VRMP
+25 V
−0.3 V
SW
35 V
40 V ≤ 50 ns
−5 V
−10 V ≤ 200 ns
BST
35 V wrt/ GND 40 V ≤ 50 ns
wrt/GND
6.5 V wrt/ SW
−0.3 V wrt/SW
LG
VCC + 0.3 V
−0.3 V
−5 V ≤ 200 ns
HG
BST + 0.3 V
−0.3 V wrt/ SW
−2 V ≤ 200 ns wrt/SW
All Other Pins
VCC + 0.3 V
−0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Thermal Characteristic
QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Symbol
Typ
Unit
RqJA
68
°C/W
TJ
−40 to +125
°C
−40 to +100
°C
°C
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
−40 to +150
Moisture Sensitivity Level
QFN Package
MSL
1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
@ 1.3 V
−21
Typ
Max
Unit
21
mA
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
20
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
DC Load = 10k to GND
25
V/ms
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
ISOURCE = 2.0 mA
3.5
V
ISINK = 2.0 mA
1
V
−12
12
mA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
−3dB Bandwidth
Closed Loop DC gain
VSP, CSREF = 1.3 V
CL = 20 pF to GND,
RL = 10 kW to GND
VS+ to VS− = 0.5 to 1.3 V
10
MHz
1.0
V/V
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos), (Note 3)
Input Bias Current
CSSUM = CSREF = 1 V
−300
300
mV
−7.5
7.5
nA
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
10
MHz
INPUT SUPPLY
5.25
V
EN = high, PS0, PS1 Mode
4.75
15
18
mA
EN = high, PS3 Mode
8.0
12
mA
200
mA
Supply Voltage Range
VCC Quiescent Current
EN = high, PS4 Mode (@ 25°C)
EN = low
VCC rising
UVLO Threshold
VCC falling
4.5
4.0
VCC UVLO Hysteresis
VRMP falling
V
V
160
VRMP rising
UVLO Threshold
mA
50
mV
4.1
3.0
V
V
DAC SLEW RATE
Soft Start Slew Rate
Fast_SR/4
mV/ms
Slew Rate Slow
Fast_SR/2
Fast_SR/4
Fast_SR/8
Fast_SR/16
mV/ms
Slew Rate Fast
48
mV/ms
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
1.0
mA
ENABLE INPUT
Enable High Input Leakage Current
Upper Threshold
External 1k pull−up to 3.3 V
VUPPER
Lower Threshold
VLOWER
Total Hysteresis
VUPPER – VLOWER
0.8
V
0.3
90
V
mV
IOUT OUTPUT
Input Referred Offset Voltage
Output Source Current
Current Gain
Ilimit to CSREF
−5.5
Ilimit sink current = 80 mA
(IOUTCURRENT ) / (ILIMITCURRENT),
RILIM = 20k, RIOUT = 5.0k , DAC =
0.8 V, 1.25 V, 1.52 V
9.75
10
5.5
mV
850
mA
10.25
OSCILLATOR
250
Switching Frequency Range
1200
kHz
ZERO CURRENT DETECT (ZCD)
ZCD threshold, DCM detection
SW wrt PGND
−0.5
mV
2.9
V
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold During Soft
Start
CSREF
Over Voltage Threshold Above DAC
VSP rising
Over Voltage Delay
VSP rising
Under Voltage Protection
VCC rising
250
300
350
mV
VCC falling
255
300
325
mV
Under Voltage Delay
350
400
440
50
Ckt in development
mV
ns
ms
5
OVERCURRENT PROTECTION
ILIM Threshold Current (OCP shutdown after
50 ms delay)
(PS0) Rlim = 20k
9.0
10
11.0
mA
ILIM Threshold Current (immediate OCP
shutdown)
(PS0) Rlim = 20k
13.5
15
16.5
mA
ILIM Threshold Current (OCP shutdown after
50 ms delay)
ILIM Threshold Current (immediate OCP
shutdown)
(PS1, PS2, PS3) Rlim = 20k
10
mA
(PS1, PS2, PS3) Rlim = 20k, PS0
mode
15
mA
VR_HOT#
Output Low Voltage
Output Leakage Current
I_VRHOT = −4 mA
High Impedance State
−1.0
0.3
V
1.0
mA
TSENSE
Alert# Assert Threshold
491
mV
Alert# De−assert Threshold
513
mV
VRHOT Assert Threshold
472
mV
VRHOT Rising Threshold
494
mV
TSENSE Bias Current
115
120
125
mA
2
V
ADC
0
Voltage Range
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
1.25
%
1
LSB
ADC
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
−1.25
8−bit, no missing codes
Power Supply Sensitivity
±1
%
Conversion Time
30
ms
Round Robin
90
ms
VR_RDY,(Power Good) Output
Output Low Saturation Voltage
IVR_RDY = 4 mA
0.3
V
Rise Time
External pull−up of 1 kW to 3.3 V,
CTOT = 45 pF, DVo = 10% to 90%
100
ns
Fall Time
External pull−up of 1KW to 3.3V,
CTOT = 45 pF, DVo = 90% to 10%
10
ns
Output Voltage at Power−up
VR_RDY pulled up to 5 V via 2 kW
Output Leakage Current When High
VR_RDY = 5.0 V
−1.0
1.2
V
1.0
mA
VR_RDY Delay (rising)
DAC = TARGET to VR_RDY
50
ms
VR_RDY Delay (falling)
From OCP or OVP
5
ms
Pull−up Resistance, Sourcing Current
BST = PVCC
1.2
High Side Driver Sourcing Current
BST = PVCC
4.17
Pull−down Resistance, Sinking Current
BST = PVCC
0.8
High Side Driver Sinking Current
BST = PVCC
6.25
HIGH−SIDE MOSFET DRIVER
2.9
W
A
2.2
W
A
HG Rise Time
VCC = 5 V, 3 nF load, BST−SW =
5V
6.0
16
30
ns
HG Fall Time
VCC = 5 V, 3 nF load, BST−SW =
5V
6.0
11
30
ns
DRVH Turn−Off Propagation Delay tpdhDRVH
CLOAD = 3 nF
4.0
30
ns
HG Turn on Propagation Delay tpdlDRVH
CLOAD = 3 nF
15
40
ns
SW Pull−Down Resistance
SW to PGND
1.9
kW
LG Pull−Down Resistance
HG to SWBST−SW = 0 V
1.9
kW
30
LOW−SIDE MOSFET DRIVER
Pull−up Resistance, Sourcing Current
0.9
Low Side Driver Sourcing Current
5.56
Pull−down Resistance, Sinking Current
0.8
Low Side Driver Sinking Current
12.5
LG Rise Time
LG Fall Time
3.0
W
A
2.0
W
A
3 nF load
6.0
16
30
ns
3 nF load
6.0
11
30
ns
LG Turn−On Propagation
Delay tpdhDRVL
CLOAD = 3 nF
11
30
ns
LG Pull−Down Resistance
LG to PGND, VCC = 5 V
1.9
kW
PVCC Quiescent Current
EN = L (Shutdown)
EN = H, no switching
1.0
490
mA
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
EN_L or EN = H with DRVL = H
5.0
9.0
22
W
BOOTSTRAP RECTIFIER SWITCH
On Resistance
3. Guaranteed by design or characterization data, not in production test.
tfDRVL
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH−SW
trDRVH
VTH
VTH
tpdhDRVL
SW
1V
Figure 5. Driver Timing Diagram
NOTE:
Timing is referenced to the 90% and the 10% points, unless otherwise stated.
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NCP81141
STATE TRUTH TABLE
STATE
VR_RDY Pin
Error AMP Comp Pin
OVP & UVP
POR
0 < VCC < UVLO
N/A
N/A
N/A
Disabled
EN < threshold
UVLO >threshold
Low
Low
Disabled
Start up Delay &
Calibration
EN> threshold
UVLO>threshold
Low
Low
Disabled
Soft Start
EN > threshold
UVLO >threshold
Low
Operational
Active /
No latch
Normal Operation
EN > threshold
UVLO >threshold
High
Operational
Active /
Latching
Over Voltage
Low
N/A
DAC + 150 mV
Over Current
Low
Operational
Last DAC Code
VOUT = 0 V
Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1;
Clamped at 0.9 V
Disabled
Method of Reset
N/A
General
The NCP81141 is a single phase PWM controller with integrated driver, designed to meet the Intel VR12.6 specifications
with a serial SVID control interface. It is designed to work in notebook and desktop applications.
The NCP81141 has one internal Driver: DRV1. Internally, there is a single PWM signal: PWM1. DRV1 is driven by PWM1.
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12
NCP81141
Serial VID interface (SVID)
For SVID Interface communication details please contact Intel Inc.
BOOT VOLTAGE PROGRAMMING
The NCP81141 has a Vboot voltage that can be externally programmed. The Boot voltage for the NCP81141 is set using
VBOOT pin on power up. A 10uA current is sourced from the VBoot pin and the resulting voltage is measured. This is
compared with the thresholds in table below. This value is programmed on power up and cannot be changed after the initial
power up sequence is complete.
BOOT VOLTAGE TABLE
R
Vboot
30.1k
0V
49.9k
1.65 V
69.8k
1.70 V
90.9k
1.75 V
REMOTE SENSE AMPLIFIER
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to
V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ ) ǒV DROOP * V CSREFǓ
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
REMOTE SENSE AMPLIFIER
The differential current-sense circuit diagram is shown in figure below. An internally-used signal Vcs, representing the
inductor current level, is the voltage difference between CSREF and CSCOMP. The output side of the inductor is used to create
a low impedance virtual ground. The current-sense amplifier actively filters and gains up the voltage applied across the inductor
to recover the voltage drop across the inductor’s DC resistance(DCR). RCS_NTC is placed close to the inductor and
compensate for the change in the DCR with temperature.
The DC gain in the current sending loop is
(VCSREF * VSCOMP)
GCS + VCS +
+ RCS
(Iout DCR)
VDCR
RCS3
RCS + RCS2 )
(RCS1 RCS_NTC)
(RCS1 ) RCS_NTC)
Figure 6. Differential Current−Sense Circuit diagram
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13
NCP81141
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high bandwidth transient performance. A standard type 3 compensation
circuit is normally used to compensate the system.
Current Sense Amplifier
The output current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and
CSREF. The output side of the inductor is used to create a low impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductor to recover the voltage drop across the inductor series resistance (DCR). Rth
is placed near the inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function
of the Rth NTC resistor and compensate for the change in the DCR with temperature.
Figure 7. Current Sense Amplifier
The DC gain equation for the current sensing:
Rcs1*Rth
V CSCOMP−CSREF + −
Rcs2 ) Rcs1)Rth
Rph
* ǒIout Total * DCRǓ
Set the gain by adjusting the value of the Rph resistor. The DC gain should be set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp.
This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain
of the amplifier should be set to provide ~100 mV across the current limit programming resistor at full load. The values of Rcs1
and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The
NTC should be placed close to the inductor.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
Fz +
DCR@25° C
2 * PI * L Phase
PROGRAMMING CURRENT LIMIT
The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors
the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the
current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current
limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on
the CSCOMP−CSREF voltage as shown below. Note the loadline is set at 50% of cscomp/csref differential.
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14
NCP81141
ǒ
2*
Rcs)
Rcs1*Rth
Rcs1)Rth
Rph
R LIMIT +
* ǒIout LIMIT * DCRǓ
Ǔ
or R LIMIT +
10m
ǒ2 * VCSCOMP−CSREF@ILIMITǓ
10m
PROGRAMMING IOUT
The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates
a 2 V signal on IOUT. A pull−up resistor from 5 V VCC can be used to offset the IOUT signal positive if needed.
R IOUT +
ǒ
2.0 V * R LIMIT
Rcs1*Rth
Rcs1)Rth
Rph
Rcs2)
10 *
Ǔ
* ǒIout ICC_MAX * DCRǓ * 2
PROGRAMMING ICC_MAX
A resistor to Ground is monitored on startup and this sets the ICC_MAX value. 10 mA is sourced from these pins to generate
a voltage on the program resistor. The resistor value should be no less than 10k.
ICC_MAX +
R * 10 mA * 64 A
2V
PROGRAMMING TSENSE
A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a
voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter.
A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification
table for the thermal sensing voltage thresholds and source current.
TSENSE
Rcomp1
0.0
Cfilter
0.1uF
Rcomp2
8.2K
AGND
t’RNTC
100k
AGND
Figure 8. TSENSE Circuit
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15
NCP81141
PRECISION OSCILLATOR
Switching frequency is programmed by a resistor Rosc to ground at the Rosc pin. The typical frequency range is from
500 kHz to 1.2 MHz. The FREQ pin provides approximately 2 V out and the source current is mirrored into the internal ramp
generator. The switching frequency can be found in figure below with a given Rosc. The frequency shown in the figure is under
condition of 10 A output current at VID = 1.8 V. The frequency has a variation over VID voltage and loading current, which
maintains similar output ripple voltage over different operation condition.
Figure 9. Operating Frequency vs. ROSC
The oscillator generates a triangular ramp that is 0.5 ~ 2.5 V in amplitude depending on the VRMP pin voltage to provide
input voltage feed forward compensation.
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NCP81141
Programming the Ramp Feed-Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed-forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 3.2 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when
the controller is disabled.
The PWM ramp time is changed according to the following
V RAMPpk + pk pp + 0.1
V VRMP
Figure 10. RPM Mode
Figure 11. Ramp Feed Forward & ROSC setup
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NCP81141
Programming DAC Feed−Forward Filter
The DAC feed−forward implementation is realized by having a filter on the VSN pin. Programming Rvsn sets the gain of
the DAC feed−forward and Cvsn provides the time constant to cancel the time constant of the system per the following
equations. Cout is the total output capacitance and Rout is the output impedance of the system.
Rvsn + Cout * Rout * 453.6
Cvsn +
10 6
Rout * Cout
Rvsn
Figure 12. DAC Feed−Forward Filter
Programming DROOP
The signals CSCOMP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop
to the output voltage.
Droop + DCR * ǒR CSńR phǓ
Figure 13. Droop
Phase COMPARITOR
The noninverting input of the comparator for phase one is connected to the output of the error amplifier (COMP) and the
phase current (IL*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a
1.3 V offset. The operating input voltage range of the comparator is from 0 V to 3.0 V and the output of the comparator generates
the PWM signal which is applied to the input of the internal driver.
During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty
cycle is still calculated by approximately Vout/Vin.
Protection Features
UNDERVOLTAGE LOCKOUT
There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81141
monitors the VCC Shunt supply. The gate driver monitors both the gate driver VCC and the BST voltage.
SOFT START
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table.
OVER CURRENT LATCH−OFF PROTECTION
The NCP81141 compares a programmable current−limit set point to the voltage from the output of the current−summing
amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external
resistor connected between ILIM and CSCOMP is then compared to the internal current limit current ICL. If the current
generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (ICL), an internal
latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150%
load current) after which the outputs will remain disabled until the VCC voltage or EN is toggled.
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18
NCP81141
The voltage swing seen on CSCOMP cannot go below ground. This limits the voltage drop across the DCR. The over−current
limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equation:
R ILIM +
ǒILIM * DCR * R CSńR PHǓ * 2
I CL
Where ICL = 10 mA.
Figure 14. Current Limit
UNDER VOLTAGE MONITOR
The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300 mV
below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.
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19
NCP81141
OVER VOLTAGE PROTECTION
The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output
voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the DAC will be ramped down slowly. At the
same time, the high side gate driver is turned off and the low side gate driver is turned on until the voltage falls to 100 mV. The
part will stay in this mode until the VCC voltage or EN is toggled. During start up, the OVP threshold is set to 2.9 V. This allows
the controller to start up without false triggering the OVP.
Figure 15. OVP Behavior at Startup
Figure 16. OVP During Normal Operation Mode
During start up, the OVP threshold is set to 2.2 V. This allows the controller to start up without false triggering the OVP.
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20
NCP81141
ORDERING INFORMATION
Package
Shipping†
NCP81141MNTWG
QFN28
(Pb−Free)
4000 / Tape & Reel
NCP81141MNTXG
QFN28
(Pb−Free)
4000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Figure 17. Alternative Extended Soldering Footprint
ON Semiconductor claims no responsibility for damage or usage
beyond that of specific recommended soldering footprint
Intel is trademark of Intel Corporation in the U.S. and/or other countries.
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21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN28 4x4, 0.4P
CASE 485AR−01
ISSUE A
DATE 20 NOV 2009
1
SCALE 2:1
PIN ONE
REFERENCE
B
A
D
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
L
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÏÏ
ÏÏ
EXPOSED Cu
0.10 C
0.10 C
L
MOLD CMPD
DETAIL B
TOP VIEW
ALTERNATE
CONSTRUCTION
A
DETAIL B
A3
0.10 C
GENERIC
MARKING DIAGRAM*
0.08 C
NOTE 4
A1
SIDE VIEW
SEATING
PLANE
C
XXXXXX
XXXXXX
ALYWG
G
0.10 C A B
D2
DETAIL A
K
8
0.10 C A B
15
28X
L
E2
1
PIN 1
INDICATOR
22
e
28X
BOTTOM VIEW
b
0.07 C A B
0.05 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
4.00 BSC
2.50
2.70
4.00 BSC
2.50
2.70
0.40 BSC
0.30 REF
0.30
0.50
−−−
0.15
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
4.30
2.71
28X
0.62
1
2.71
4.30
PACKAGE
OUTLINE
0.40
PITCH
DOCUMENT NUMBER:
98AON30349E
28X
0.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
Case Outline Number:
http://onsemi.com
QFN28 4X4, 0.4P
DESCRIPTION:
October, 2002
− Rev. 0
PAGE 1 OFXXX
2
1
DOCUMENT NUMBER:
98AON30349E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION. REQ. BY M. LIN.
15 MAY 2008
A
CHANGED DIMENSIONS D2, E2, K, L, MOUNTING FOOTPRINT AND MARKING
DIAGRAM INFORMATION. REQ. BY J. LIU.
20 NOV 2009
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 01A
Case Outline Number:
485AR
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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