NCP81158MNTXG

NCP81158 Synchronous Buck MOSFET Driver The NCP81158 is a high−performance dual MOSFET gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. The driver outputs can be placed into a high−impedance state via the tri−state PWM and EN inputs. The NCP81158 comes packaged with an integrated boost diode to minimize external components. A VCC UVLO function guarantees the outputs are low when the supply voltage is low. • • • MARKING DIAGRAM 1 1 Features • • • • • • www.onsemi.com Space−efficient 3 mm x 3 mm DFN8 thermally−enhanced Package VCC Range of 4.5 V to 5.5 V Internal Bootstrap Diode 5 V 3−stage PWM Input Diode Braking Capability via EN Mid−state Adaptive Anti−cross Conduction Circuit Protects Against Cross−conduction during FET Turn−on and Turn−off Output Disable Control Turns Off Both MOSFETs via Enable Pin VCC Undervoltage Lockout These Devices are Pb−free, Halogen−free/BFR−free and are RoHS Compliant Typical Applications • Power Solutions for Notebook and Desktop Systems DFN8 CASE 506BJ 81158 A L Y W G 8 81158 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PINOUT DIAGRAM BST 1 PWM 2 EN 3 VCC 4 FLAG 9 8 DRVH 7 SW 6 GND 5 DRVL ORDERING INFORMATION Device Package Shipping† NCP81158MNTXG DFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 0 1 Publication Order Number: NCP81158/D NCP81158 BST VCC DRVH PWM Logic SW Anti−Cross Conduction VCC DRVL EN ZCD Detection UVLO Figure 1. Block Diagram PIN DESCRIPTIONS Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. 3 EN Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input: EN = High to enable the gate driver; EN = Low to disable the driver; EN = Mid to go into diode mode (both high and low side gate drive signals are low) 4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node. 7 SW 8 DRVH Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. www.onsemi.com 2 NCP81158 APPLICATION CIRCUIT 5 V _ POWER R1 1 .02 VIN R2 C2 0 .0 0 .1 uF NCP81158 Q1 C4 4 .7 uF C5 4 .7 uF C6 4 .7 uF C7 390 uF R3 BST DRVH L 0 .0 PWM SW PWM EN DRON VCC C1 1 uF VCCP Q2 GND Q3 R4 2 .2 C3 2700 pF DRVL PAD Figure 2. Application Circuit www.onsemi.com 3 235 nH NCP81158 ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION Symbol Pin Name VMAX VMIN VCC Main Supply Voltage Input 6.5 V 7.5 V < 80 ns −0.3 V BST Bootstrap Supply Voltage 35 V wrt/ GND 40 V v 50 ns wrt/ GND 6.5 V wrt/ SW 7.7 V < 50 ns wrt/ SW −0.3 V wrt/SW SW Switching Node (Bootstrap Supply Return) 35 V 40 V v 80 ns −5 V −10 V (200 ns) DRVH High Side Driver Output BST + 0.3 V SW + 7 V (< 80 ns) −0.3 V wrt/SW −2 V (< 200 ns) wrt/SW DRVL Low Side Driver Output VCC + 0.3 V 7 V (< 80 ns) −0.3 V DC −5 V (< 200 ns) PWM DRVH and DRVL Control Input 6.5 V −0.3 V Enable Pin 6.5 V −0.3 V 0V 0V EN GND Ground Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *All signals referenced to AGND unless noted otherwise. THERMAL INFORMATION Symbol RqJA Parameter Thermal Characteristic QFN Package (Note 1) Value Unit 119 °C/W TJ Operating Junction Temperature Range (Note 2) −40 to 150 °C TA Operating Ambient Temperature Range −40 to +100 °C TSTG Maximum Storage Temperature Range −55 to +150 °C MSL Moisture Sensitivity Level − QFN Package 1 *The maximum package power dissipation must be observed. 1. 1 in2 Cu, 1 oz. thickness. 2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM. NCP81158 ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted) Parameter Test Conditions Min Typ Max Unit 5.5 V SUPPLY VOLTAGE 4.5 VCC Operation Voltage UNDERVOLTAGE LOCKOUT VCC Start Threshold 3.8 4.35 4.5 V VCC UVLO Hysteresis 150 200 250 mV 2.0 mA SUPPLY CURRENT Shutdown Mode ICC + IBST, EN = GND 1.0 Normal Mode ICC + IBST, EN = 5 V, PWM = OSC 4.7 mA Standby Current ICC + IBST, EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 0.9 mA Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 1.1 mA BOOTSTRAP DIODE Forward Voltage VCC = 5 V, forward bias current = 2 mA www.onsemi.com 4 0.1 0.4 0.6 V NCP81158 NCP81158 ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted) Parameter Test Conditions Min Typ Max Unit PWM INPUT PWM Input High 3.4 PWM Mid−State 1.3 V PWM Input Low ZCD Blanking Timer 2.7 V 0.7 V 350 ns HIGH SIDE DRIVER Output Impedance, Sourcing Current VBST−VSW = 5 V 0.9 1.7 W Output Impedance, Sinking Current VBST−VSW = 5 V 0.7 1.7 W DRVH Rise Time trDRVH VCC = 5 V, 3 nF load, VBST−VSW = 5 V 16 25 ns DRVH Fall Time tfDRVH VCC = 5 V, 3 nF load, VBST−VSW =5 V 11 18 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 10 30 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 10 40 ns SW Pulldown Resistance SW to PGND 45 kW DRVH Pulldown Resistance DRVH to SW, BST−SW = 0 V 45 kW LOW SIDE DRIVER Output Impedance, Sourcing Current 0.9 1.7 W Output Impedance, Sinking Current 0.4 0.8 W DRVL Rise Time trDRVL CLOAD = 3 nF 16 25 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 11 15 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 10 30 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 5.0 25 ns DRVL Pulldown Resistance DRVL to PGND, VCC = PGND 45 kW EN INPUT Input Voltage High 3.3 Input Voltage Mid 1.35 V 1.8 Input Voltage Low Input bias current −1.0 Propagation Delay Time 20 V 0.6 V 1.0 mA 40 ns 20 mA SW NODE SW Node Leakage Current Zero Cross Detection Threshold Voltage −6.0 mV Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 1. DECODER TRUTH TABLE ZCD DRVL DRVH PWM High (Enable High) Input ZCD Reset Low High PWM Mid (Enable High) Positive Current Through the Inductor High Low PWM Mid (Enable High) Zero Current Through the Inductor Low Low PWM Low (Enable High) ZCD Reset High Low X Low Low Enable at Mid www.onsemi.com 5 NCP81158 PWM tpdlDRVL tfDRVL DRVL 90% 1V 1V 90% 10% tpdhDRVH 10% tpdlDRVH tfDRVH trDRVH 90% DRVH−SW 1V 90% 10% trDRVL 1V 10% tpdh DRVL Figure 3. Gate Timing Diagram PWM DRVH−SW DRVL IL Figure 4. Timing Diagram APPLICATION INFORMATION High−Side Driver The NCP81158 gate driver is a single−phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. The high−side driver is designed to drive a floating low−RDS(on) N−channel MOSFET. The gate voltage for the high−side driver is developed by a bootstrap circuit referenced to the SW pin. The bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. When the NCP81158 is starting up, the SW pin is held at ground, allowing the Low−Side Driver The low−side driver is designed to drive a ground−referenced low−RDS(on) N−channel MOSFET. The voltage supply for the low−side driver is internally connected to the VCC and GND pins. www.onsemi.com 6 NCP81158 mode as long as VCC is greater than the UVLO threshold and EN is high. The threshold limits are specified in the electrical characteristics table in this datasheet. Refer to Figure 21 for the gate timing diagrams and Table 1 for the EN/PWM logic table. When PWM is set above PWMHI, DRVL will first turn off after a propagation delay of tpdlDRVL. To ensure non−overlap between DRVL and DRVH, there is a delay of tpdhDRVH from the time DRVL falls to 1 V, before DRVH is allowed to turn on. When PWM falls below PWMLO, DRVH will first turn off after a propagation delay of tpdlDRVH. To ensure non−overlap between DRVH and DRVL, there is a delay of tpdhDRVL from the time DRVH – SW falls to 1 V, before DRVL is allowed to turn on. When PWM enters the mid−state voltage range, DRVL goes high after the non−overlap delay, and stays high for the duration of the ZCD blanking + debounce timers. Once these timers expire, SW is monitored for zero current detection and pulls DRVL low once zero current is detected. bootstrap capacitor to charge up to VCC through the bootstrap diode. When the PWM input is driven high, the high−side driver will turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the SW pin rises. When the high−side MOSFET is fully turned on, SW will settle to VIN and BST will settle to VIN + VCC (excluding parasitic ringing). Bootstrap Circuit The bootstrap circuit relies on an external charge storage capacitor (CBST) and an integrated diode to provide current to the high−side driver. A multi−layer ceramic capacitor (MLCC) with a value greater than 100 nF should be used for CBST. Power Supply Decoupling The NCP81158 can source and sink relatively large currents to the gate pins of the MOSFETs. In order to maintain a constant and stable supply voltage, a low−ESR capacitor should be placed near the VCC and GND pins. A MLCC between 1 mF and 4.7 mF is typically used. Undervoltage Lockout Thermal Considerations DRVH and DRVL are low until VCC reaches the VCC UVLO threshold, typically 4.35 V. Once VCC reaches this threshold, the PWM signal will control DRVH and DRVL. There is a 200 mV hysteresis on VCC UVLO. There are pull−down resistors on DRVH, DRVL and SW to prevent the gates of the MOSFETs from accumulating enough charge to turn on when the driver is powered off. As power in the NCP81158 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCP81158 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCP81158 can handle is given by: Three−State EN Input Placing EN into a logic−high and logic−low will turn the driver on and off, respectively, as long as VCC is greater than the UVLO threshold. The EN threshold limits are specified in the electrical characteristics table in this datasheet. Setting the voltage on EN to a mid−state level will pull both DRVH and DRVL low. Setting EN to the mid−state level can be used for body diode braking to quickly reduce the inductor current. By turning the LS FET off and having the current conduct through the LS FET body diode, the voltage at the switch node will be at a greater negative potential compared to having the LS FET on. This greater negative potential on switch node allows there to be a greater voltage across the output inductor, since the opposite terminal of the inductor is connected to the converter output voltage. The larger voltage across the inductor causes there to be a greater inductor current slew rate, allowing the current to decrease at a faster rate. P D(MAX) + ƪTJ(MAX) * TAƫ R qJA (eq. 1) Since TJ is not recommended to exceed 150°C, the NCP81158, soldered on to a 645 mm2 copper area, using 1 oz. copper and FR4, can dissipate up to 1.05 W when the ambient temperature (TA) is 25°C. The power dissipated by the NCP81158 can be calculated from the following equation: (eq. 2) P D [ VCC @ ƪǒn HS @ Qg HS ) n LS @ Qg LSǓ @ f ) I standbyƫ Where nHS and nLS are the number of high−side and low−side FETs, respectively, QgHS and QgLS are the gate charges of the high−side and low−side FETs, respectively and f is the switching frequency of the converter. Three−State PWM Input Switching PWM between logic−high and logic−low states will allow the driver to operate in continuous conduction www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 3x3, 0.5P CASE 506BJ−01 ISSUE O 1 SCALE 2:1 PIN 1 REFERENCE 2X 0.10 C 2X ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ 0.10 C EDGE OF PACKAGE A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL A E OPTIONAL CONSTRUCTION DIM A A1 A3 b D D2 E E2 e K L L1 L TOP VIEW DETAIL A OPTIONAL CONSTRUCTION DETAIL B 0.05 C DATE 08 NOV 2007 A 8X 0.05 C NOTE 4 8X 8X (A3) SIDE VIEW A1 D2 L 1 C DETAIL A 4 8 5 e 8X ÉÉ ÉÉ 1 MOLD CMPD DETAIL B E2 K GENERIC MARKING DIAGRAM* SEATING PLANE EXPOSED Cu OPTIONAL CONSTRUCTION b 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 SOLDERMASK DEFINED MOUNTING FOOTPRINT 1.85 8X 0.35 8X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.64 1.84 3.00 BSC 1.35 1.55 0.50 BSC 0.20 −−− 0.30 0.50 0.00 0.03 XXXXX XXXXX ALYWG G 8 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 3.30 1.55 0.63 0.50 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON25786D DFN8 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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