NCP81245MNTXG

NCP81245 Three-Rail Output Controller with Single Intel Proprietary Interface for Desktop and Notebook CPU Applications www.onsemi.com The NCP81245 (3+3+1 phase) three−output buck solution is optimized for Intel’s IMVP8 CPUs. The two multi−phase rail control systems are based on Dual−Edge pulse−width modulation (PWM) combined with DCR current sensing providing an ultra fast initial response to dynamic load events and reduced system cost. The single−phase rail makes use of ON Semiconductor’s patented high performance RPM operation. RPM control maximizes transient response while allowing for smooth transitions between discontinuous−frequency−scaling operation and continuous−mode full−power operation. The NCP81245 has an ultra−low offset current monitor amplifier with programmable offset compensation for high−accuracy current monitoring. MARKING DIAGRAM 1 52 NCP81245 FAWLYYWW G QFN52 MN SUFFIX CASE 485BE F A WL YY WW G = Wafer Fab = Assembly Site = Lot ID = Year = Work Week = Pb−Free Package Three−Phase Rails Feature • Dual Edge Modulation for Fastest Initial Response to Transient • • • • • • • • • • • • • Loading High Performance Operational Error Amplifier Digital Soft Start Ramp Dynamic Reference Injection Accurate Total Summing Current Amplifier Dual High Impedance Differential Voltage and Total Current Sense Amplifiers Phase−to−Phase Dynamic Current Balancing True Differential Current Balancing Sense Amplifiers for Each Phase Adaptive Voltage Positioning (AVP) Switching Frequency Range of 300 kHz − 750 kHz Vin range 4.5 V to 20 V Startup into Pre−Charged Loads While Avoiding False OVP UltraSonic Operation These Devices are Pb−Free and are RoHS Compliant Single−Phase Rail Features • • • • • • January, 2017 − Rev. 6 Device NCP81245MNTXG Package Shipping† QFN52 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. • UltraSonic Operation • Adjustable Vboot • Digitally Controlled Operating Frequency Enhanced RPM Control System Ultra Low Offset IOUT Monitor Dynamic VID Feed−Forward Programmable Droop Gain Zero Droop Capable Thermal Monitor © Semiconductor Components Industries, LLC, 2017 ORDERING INFORMATION Applications • Desktop & Notebook Processors • Gaming 1 Publication Order Number: NCP81245/D NCP81245 +5V SKT_SNS+ VSP VCC VSN GND VDRV SKT_SNS− DIFFOUT VIN LG HG BST PWM1 PWM DRON EN VCC FB VIN ON DrMOS SW PGND GND SMOD ZCD CSP1 COMP VDRV BST PWM PWM2 EN VCC TSENSE VIN Vcc_Rail1 ON DrMOS SW PGND GND SMOD ZCD NTC Vpu VIN LG HG IOUT CSP2 VDRV VRHOT Vpu BST PWM PWM3 SDIO EN VCC ALERT PSYS VIN ON DrMOS SW PGND GND SMOD ZCD CSP3 SCLK batt chrgr VIN LG HG Vpu CSREF CSSUM ILIM CSCOMP NTC VDRV TSENSE VIN LG HG NCP81245 BST NTC PWM1 PWM DRON EN VCC VIN ON DrMOS SW PGND GND SMOD ZCD IOUT CSP1 VDRV SKT_SNS+ BST SKT_SNS− VSN VIN LG HG VSP PWM PWM2 EN VCC DIFFOUT VIN Vcc_Rail2 ON DrMOS SW PGND GND SMOD ZCD FB CSP2 VDRV BST EN VRRDY PWM PWM3 EN VCC VIN VIN ON DrMOS SW PGND GND SMOD ZCD CSP3 VRMP VIN LG HG COMP CSREF CSSUM SKT_SNS+ SKT_SNS− VSP ILIM VSN CSCOMP NTC VDRV COMP VIN LG HG BST IOUT PWM PWM ILIM CSP EN VCC CSN VIN Vcc_Rail3 ON DrMOS SW PGND GND SMOD ZCD NTC Figure 1. www.onsemi.com 2 NCP81245 VSP_3PH_A VSN_3PH_A IMON_3PH_A DIFFOUT_3PH_A FB_3PH_A COMP_3PH_A ILIM_3PH_A CSCOMP_3PH_A CSSUM_3PH_A CSREF_3PH_A CSP1_3PH_A CSP2_3PH_A CSP3_3PH_A 1 2 3 4 5 6 7 8 9 10 11 12 13 NCP81245 TAB: GROUND Figure 2. Pinout www.onsemi.com 3 39 38 37 36 35 34 33 32 31 30 29 28 27 VRHOT# VSP_3PH_B VSN_3PH_B IMON_3PH_B DIFFOUT_3PH_B FB_3PH_B COMP_3PH_B ILIM_3PH_B CSCOMP_3PH_B CSSUM_3PH_B CSREF_3PH_B CSP1_3PH_B CSP2_3PH_B NCP81245 1.3V VRHOT# 31 VSP THERMAL MONITOR OVP VSN 47 VSP_2ph _ ENABLE ALERT# 33 OCP OVP SCLK 34 48 VSN_2ph DAC DAC SVID INTERFACE & LOGIC SDIO 32 VSP VSN DIFF AMP OVP DRVON CSCOMP DAC FEED− FORWARD _ PS# ENABLE CSREF 2 DIFFOUT_2ph 3 FB_2ph 4 COMP_2ph + VR_RDY 38 DATA REGISTERS VR READY LOGIC ERROR AMP 1.3V ROSC_COREGT14 ROSC_SAUS 15 MUX ICCMAX_2ph 18 ICCMAX_1a 19 ICCMAX_1b 20 CURRENT SENSE AMP IOUT_2ph ADC IOUT_1a OVP ADDR_VBOOT21 IOUT_1b 6 CSCOMP_2ph _ 7 CSSUM_2ph + 8 CSREF_2ph Buffer OVERCURRENT PROGRAMMING 5 ILIM_2ph OVERCURRENT COMPARATORS MAX OVP TSENSE_2ph 11 TSENSE_1ph 23 ENABLE PSYS 46 OCP VRMP 12 1 PS# OSCILLATOR & RAMP GENERATORS VRMP DRVON COMP OVP OCP ENABLE PWM GENERATORS PWM1 EN 37 UVLO & EN COMPARATORS PWM2 VCC 13 PS# GROUND 49 PS# IOUT CURRENT BALANCE AMPLIFIERS IPH2 IPH1 ZERO CURRENT DETECTION POWER STATE GATE IOUT_2ph CURRENT MONITOR 35 DRVON 9 CSP2_2ph 10 CSP1_2ph 16 PWM1_2ph 17 PWM2_2ph Figure 3. Block Diagram of Dual Edge Architecture www.onsemi.com 4 NCP81245 DAC FEED− FORWARD CURRENT DAC DAC VSN gm VSP 25 VSN_1a 24 VSP_1a 26 COMP_1a gm DROOP CURRENT + Av=1 _ FROM SVID INTERFACE DAC FEEDFORWARD OVP OVP REF DRVON COMP gm OVP CURR PWM GENERATOR OCP RAMP OVERCURRENT PROGRAMMING OVERCURRENT COMPARATORS OCP OCP REF FREQ IOUT RAMP GENERATOR 27 ILIM_1a gm DAC VRMP 29 CSP_1a CURRENT SENSE AMP 28 CSN_1a PWM PS# ZERO CURRENT DETECTION Figure 4. Block Diagram of Enhanced RPM Architecture www.onsemi.com 5 CURRENT MONITOR 30 IOUT_1a 22 PWM_1a NCP81245 Table 1. QFN52 PIN LIST DESCRIPTION Pin Name 1 VSP_3PH_A Differential output voltage sense positive for multi−phase rail “A” Description 2 VSN_3PH_A Differential output voltage sense negative for multi−phase rail “A” 3 IMON_3PH_A A resistor to ground programs IOUT gain for multi−phase rail “A” 4 DIFFOUT_3PH_A Output of multi−phase rail “A” differential remote sense amplifier 5 FB_3PH_A 6 COMP_3PH_A 7 ILIM_3PH_A 8 CSCOMP_3PH_A 9 CSSUM_3PH_A Inverting input of total−current−sense amplifier for multi−phase rail “A” 10 CSREF_3PH_A Total−current−sense amplifier reference voltage input for multi−phase rail “A” 11 CSP1_3PH_A Current−balance amplifier positive input for Phase 1 of multi−phase rail “A” 12 CSP2_3PH_A Current−balance amplifier positive input for Phase 2 of multi−phase rail “A” 13 CSP3_3PH_A Current−balance amplifier positive input for Phase 3 of multi−phase rail “A” 14 TTSENSE_3PH_A 15 VRMP 16 VCC 17 DRON 18 PWM1_3PH_A / ICCMAX_3PH_A Phase 1 PWM output of multi−phase rail “A” / A resistor to ground programs ICCMAX for multi−phase rail “A” 19 PWM2_3PH_A / ADDR Phase 2 PWM output of multi−phase rail “A” / A resistor to ground configures Intel proprietary interface addresses for all 3 rails (ADDR) 20 PWM3_3PH_A / VBOOT Phase 3 PWM output of multi−phase rail “A” / A resistor to ground configures boot voltage for all 3 rails (VBOOT) 21 PWM3_3PH_B / ROSC_3PH Phase 3 PWM output of multi−phase rail “B” / Phase 4 PWM output of multi−phase rail “A” / A resistor to ground configures Fsw for both “A” and “B” multi−phase rails (ROSC_3PH) 22 PWM2_3PH_B / ROSC_1PH Phase 2 PWM output of multi−phase rail “B” / A resistor to ground configures Fsw for 1ph rail (ROSC_1ph) 23 PWM1_3PH_B / ICCMAX_3PH_B Phase 1 PWM output of multi−phase rail “B” / A resistor to ground programs ICCMAX for multi−phase rail “B” 24 TTSENSE_1PH / PSYS Temperature sense input for the single−phase rail / System input power monitor. A resistor to ground scales this signal 25 TTSENSE_3PH_B 26 CSP3_3PH_B Current−balance amplifier positive input for Phase 3 of multi−phase rail “B” / Phase 4 of multi−phase rail “A” 27 CSP2_3PH_B Current−balance amplifier positive input for Phase 2 of multi−phase rail “B” 28 CSP1_3PH_B Current−balance amplifier positive input for Phase 1 of multi−phase rail “B” 29 CSREF_3PH_B Total−current−sense amplifier reference voltage input for multi−phase rail “B” 30 CSSUM_3PH_B Inverting input of total−current−sense amplifier for multi−phase rail “B” 31 CSCOMP_3PH_B 32 ILIM_3PH_B 33 COMP_3PH_B 34 FB_3PH_B 35 DIFFOUT_3PH_B Output of multi−phase rail “B” differential remote sense amplifier 36 IMON_3PH_B A resistor to ground programs IOUT gain for multi−phase rail “B” 37 VSN_3PH_B Differential output voltage sense negative for multi−phase rail “B” Error amplifier voltage feedback for multi−phase rail “A” Error amplifier output and PWM comparator inverting input for multi−phase rail “A” A resistor to CSCOMP_3PH_A programs the over−current threshold for multi−phase rail “A” Total−current−sense amplifier output for multi−phase rail “A” Temperature sense input for multi−phase rail “A” Vin feed−forward input. Controls a current used to generate the ramps of the modulators Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground External FET driver enable for discrete driver or DrMOS Temperature sense input for multi−phase rail “B” Total−current−sense amplifier output for multi−phase rail “B” A resistor to CSCOMP_3PH_B programs the over−current threshold for multi−phase rail “B” Error amplifier output and PWM comparator inverting input for multi−phase rail “B” Error amplifier voltage feedback for multi−phase rail “B” www.onsemi.com 6 NCP81245 Table 1. QFN52 PIN LIST DESCRIPTION Pin Name 38 VSP_3PH_B 39 VR_HOT# 40 SDIO 41 ALERT# 42 SCLK 43 EN 44 PWM_1PH / ICCMAX_1PH Description Differential output voltage sense positive for multi−phase rail “B” Thermal logic output for over−temperature condition on TTSENSE pins Serial VID data interface Serial VID ALERT# Serial VID clock Enable input. High enables all three rails PWM output of the single−phase rail / A resistor to ground programs ICCMAX for the single−phase rail 45 VR_RDY 46 IMON_1PH VR_RDY indicates all three rails are ready to accept Intel proprietary interface commands A resistor to ground programs IOUT gain for the single−phase rail 47 CSP_1PH Differential current sense positive for the single−phase rail 48 CSN_1ph Differential current sense negative for the single−phase rail 49 ILIM_1ph A resistor to ground programs ILIM gain for the single−phase rail 50 COMP_1ph 51 VSN_1ph Differential output voltage sense negative for single−phase rail 52 VSP_1ph Differential output voltage sense positive for single−phase rail 53 Tab Compensation for single−phase rail GND ELECTRICAL INFORMATION Table 2. ABSOLUTE MAXIMUM RATINGS Pin Symbol VMAX VMIN ISOURCE ISINK COMPX VCC + 0.3 V −0.3 V 2 mA 2 mA CSCOMPX VCC + 0.3 V −0.3 V 2 mA 2 mA VSN GND + 300 mV GND−300 mV 1 mA 1 mA VRDY VCC + 0.3 V −0.3 V N/A 2 mA VCC 6.5 V −0.3 V N/A N/A VRMP +25 V −0.3 V All Other Pins VCC + 0.3 V −0.3 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *All signals referenced to GND unless noted otherwise. Table 3. THERMAL INFORMATION Description Thermal Characteristic QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Symbol Typ Unit RJA 68 °C/W TJ −40 to +125 °C −40 to +100 °C °C Operating Ambient Temperature Range Maximum Storage Temperature Range TSTG −40 to +150 Moisture Sensitivity Level QFN Package MSL 1 *The maximum package power dissipation must be observed. 1. 2) JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM 2. 3) JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM www.onsemi.com 7 NCP81245 Table 4. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF Test Conditions Parameter Min Typ Max Unit 900 nA ERROR AMPLIFIER −900 Input Bias Current Open Loop DC Gain CL = 20 pF to GND, RL = 10 kW to GND 80 dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND 20 MHz Slew Rate DVin = 100 mV, G = −10 V/V, DVout = 0.75 V − 1.52 V, CL = 20 pF to GND, DC Load = 10k to GND 5 V/ms Maximum Output Voltage ISOURCE = 2.0 mA Minimum Output Voltage ISINK = 2.0 mA 3.5 V 1 V DIFFERENTIAL SUMMING AMPLIFIER Input Bias Current −25 25 nA VSP Input Voltage Range −0.3 3.0 V VSN Input Voltage Range −0.3 0.3 V −3dB Bandwidth CL = 20 pF to GND, RL = 10 k W to GND 22.5 MHz Closed Loop DC gain VS to DIFF VS+ to VS− = 0.5 to 1.3 V 1.0 V/V Maximum Output Voltage ISOURCE = 2 mA Minimum Output Voltage ISINK = 2 mA 3.5 V 0.8 V −300 300 mV 7.5 mA 7.5 nA CURRENT SUMMING AMPLIFIER Offset Voltage (Vos) Input Bias Current CSREF= 1 V −7.5 Input Bias Current CSSUM= 1 V −7.5 Open Loop Gain Current Sense Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 kW to GND Maximum CSCOMP (A) Output Voltage Isource = 2 mA Minimum CSCOMP(A) Output Voltage Isink = 500 uA 80 dB 15 MHz 3.5 V 0.15 V −50 50 nA 0 2.3 V CURRENT BALANCE AMPLIFIER Input Bias Current CSPX − CSPX + 1 = 1.2 V Common Mode Input Voltage Range CSPx = CSREF Differential Mode Input Voltage Range CSNx = 1.2 V −100 100 mV Closed loop Input Offset Voltage Matching CSPx = 1.2 V, Measured from the average −1.5 1.5 mV Current Sense Amplifier Gain 0V < CSPx < 0.1 V, 5.7 6.3 V/V Multiphase Current Sense Gain Matching CSREF = CSP = 10 mV to 30 mV −3 −3dB Bandwidth 6.0 3 8 % MHz BIAS SUPPLY 4.75 Supply Voltage Range VCC Quiescent Current Enable high VCC Quiescent Current Enable low www.onsemi.com 8 33 5.25 V 50 mA 60 mA NCP81245 Table 4. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF Parameter Test Conditions Min Typ Max Unit 4.5 V BIAS SUPPLY UVLO Threshold VCC rising VCC falling 4 VCC UVLO Hysteresis 250 mV VRMP 4.5 Supply Range UVLO Threshold VRamp rising VRamp falling 20 V 4.25 V 3 UVLO Hysteresis V 675 mV DAC SLEW RATE >10 mV/ms Soft Start Slew Rate 1/2 SR Fast mV/ms Slew Rate Slow 1/2 SR Fast mV/ms Slew Rate Fast ENABLE INPUT Enable High Input Leakage Current Enable = 0 VIH −1 1 0.8 V VIL Enable Delay Time mA Measure time from Enable transitioning HI , VBOOT is not 0 V 0.3 V 2.5 ms DRON Output High Voltage Sourcing 500 mA Output Low Voltage Sinking 500 mA 3.0 V 0.1 Pull Up Resistances V 2.0 kW Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% 160 ns Internal Pull Down Resistance VCC = 0 V 70 kW OVERCURRENT PROTECTION 11 mA 16.5 mA Ilim Threshold Current (delayed OCP shutdown) PS0 Ilim Threshold Current (immediate OCP shutdown) PS0 PS1, PS2, PS3 (N = PS0 phase count) 15/N Shutdown Delay Immediate 300 ns Delayed 50 ms ILIM Output Voltage Offset 9 PS1, PS2, PS3 (N = PS0 phase count) 10/N 13.5 Ilim sourcing 10 mA 10 15 −2 2 mV 0.25 mA IOUT_3PH_A/IOUT_3PH_B OUTPUT Output Offset Current VIlim = 5 V Output current max Ilimit sink current 20 mA Current Gain (Iout current)/(Ilimit Current) Rlim = 20k, Riout = 5k DAC = 0.8 V, 1.25 V, 1.52 V www.onsemi.com 9 mA 200 9.5 10 10.5 A/A NCP81245 Table 4. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF Parameter Test Conditions Min Typ Max Unit 300 1200 kHz −10 10 % OSCILLATOR Switching Frequency Range Switching Frequency Accuracy 300 kHz < Fsw < 1 MHz OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP) Over Voltage Threshold During Soft−Start Over Voltage Threshold Above DAC VSP rising Over Voltage Delay VSP rising to PWMx low Under Voltage Threshold Below DAC−DROOP VSP falling Under−voltage Hysteresis VSP rising 1.9 2.0 2.1 V 370 400 430 mV 25 225 Under−Voltage Delay 300 ns 370 mV 25 mV 5 ms MODULATORS (PWM COMPARATORS) FOR A RAIL & B RAIL Minimum Pulse Width Fsw = 350 kHz 40 ns 0% Duty Cycle COMP voltage when the PWM outputs remain LO 1.3 V 100% Duty Cycle COMP voltage when the PWM outputs remain HI VRMP=12.0V 2.5 V PWM Phase Angle Error Between adjacent phases ±5 ° VRHOT Assert Threshold 468 mV VRHOT Rising Threshold 488 mV Alert Assertion Threshold 488 mV Alert Rising Threshold 510 mV TSENSE 125 mA 0.3 V −1 1 mA Voltage Range 0 2 V Total Unadjusted Error (TUE) −1 1 % 1 LSB TSENSE Bias Current 115 120 VRHOT Output Low Saturation Voltage IVR_HOT = −4 mA Output Leakage Current High Impedance State ADC Differential Nonlinearity (DNL) 8−bit Power Supply Sensitivity +/−1 % Conversion Time 7.4 ms Round Robin 206 ms VRDY OUTPUT Output Low Saturation Voltage IVR_RDY = 4 mA 0.3 V Rise Time External pull−up of 1 kW to 3.3 V CTOT = 45 pF, DVo = 10% to 90% 150 ns Fall Time External pull−up of 1 KW to 3.3 V CTOT = 45 pF, DVo = 90% to 10% 150 ns Output Leakage Current When High VR_RDY = 5.0 V 1 mA VR_RDY Delay (falling) Due to OCP or OVP www.onsemi.com 10 −1 0.3 ms NCP81245 Table 4. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < TA < 100°C; 4.75 V < VCC < 5.25 V ; CVCC = 0.1mF Parameter Test Conditions Min Typ Max Unit PWM OUTPUTS Output High Voltage Sourcing 500 mA Output Mid Voltage No Load Output Low Voltage Sinking 500 mA Rise and Fall Time CL (PCB) = 50 pF, DVo =10% to 90% of VCC Tri−State Output Leakage Gx = 2.0 V, x = 1−2, EN = Low VCC − 0.2 1.9 V 2.0 2.1 V 0.3 V 5 −1 ns 1 mA PHASE DETECTION 4.75 CSPX Phase Disable Voltage V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 11 NCP81245 SINGLE PHASE ELECTRICAL TABLE FOLLOWS Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C