NCS2632DTBR2G

NCS2632 NOCAP], Pop-Free, 3 VRMS Audio Line Driver with Adjustable Gain The NCS2632 is a pop−free stereo line driver. It uses ON Semiconductor’s patented NOCAP technology which allows the elimination of the external DC−blocking capacitors by providing ground−referenced outputs through the generation of an internal negative supply rail. The device can drive 3 VRMS into a 600 W load at 5 V power supply. By eliminating the two external heavy coupling capacitors, the NOCAP approach offers significant space and cost savings compared to similar audio solutions. The NCS2632 has differential inputs and is available with an external adjustable gain ranging from ±1 V/V to ±10 V/V. The gain is adjusted with external resistors. The device can also be configured as a 2nd order low pass filter to complement DAC’s and SOC converters. In addition to the NOCAP architecture, it contains specific circuitry to prevent “Pop & Click” noise from occurring during Enable / Shutdown transitions. The Signal-to-Noise Ratio reaches 105 dB, offering high fidelity audio sound. The NCS2632 exhibits a high power supply rejection with a typical value of 90 dB. This device also features an Under−Voltage Protection (UVP) function which can be adjusted using an external resistor bridge. The device is available in a TSSOP−14 package. http://onsemi.com MARKING DIAGRAM 14 14 1 TSSOP−14 CASE 948G A L Y W G 1 NCS 2632 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (*Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8473/D. Features ORDERING INFORMATION • NOCAP See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Eliminates Pop/Clicks Eliminates Output DC−Blocking Capacitors – Provides Flat Frequency Response 20 Hz – 20 kHz Supply Voltage from 2.2 V to 5.5 V Low Noise and THD ♦ SNR = 105 dB ♦ Typical Vn at 8 mVrms, A−Weighted ♦ THD+N < 0.001% at 1 kHz Output Voltage into 600 W Load ♦ 2 VRMS with 3.3 V Supply Voltage ♦ 3 VRMS with 5 V Supply Voltage Adjustable Gain from ± 1 V/V to ± 10 V/V Differential Input High PSRR: 90 dB External Under−Voltage Detection Function Enhanced Pop & Click Suppression Function Offset Voltage ≤ ±400 mV ♦ ♦ • • • • • • • • • © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 4 • Outputs pass ±8 kV contact discharge according to IEC61000−4−2 under application conditions • Available in a TSSOP−14 package • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • • • • • 1 Set−Top Boxes PDP / LCD TV Blu−ray™ Player, DVD Players Home Theater in a Box Laptops, Notebook PCs Publication Order Number: NCS2632/D NCS2632 VDD INLP INLM OUTL EN CP CN Charge Pump Circuitry Click/Pop Suppression Circuitry Bias Circuitry AGND UVP AGND PGND AGND OUTR VSS INRP INRM Figure 1. NCS2632, Simplified Block Diagram 1 INRP INLP 14 2 INRM INLM 13 3 OUTR OUTL 12 4 AGND UVP 11 5 EN PGND 10 6 VSS 7 CN VDD 9 CP 8 Figure 2. NCS2632, Pinout http://onsemi.com 2 NCS2632 PIN FUNCTION AND DESCRIPTION Pin Name Type 1 INRP Input Right channel positive input Description 2 INRM Input Right channel negative input 3 OUTR Output Right channel output 4 AGND Ground Analog ground. Connect to PGND 5 EN Input 6 VSS Power Negative rail output. Connected to ground through 1 mF low ESR ceramic reservoir capacitor. 7 CN − Flying capacitor Negative terminal. Connected to CP through 1 mF low ESR ceramic capacitor. 8 CP − Flying capacitor Positive terminal. Connected to CN through 1 mF low ESR ceramic capacitor. 9 VDD Power Power Supply Input 10 PGND Ground Power ground 11 UVP Input 12 OUTL Output 13 INLM Input Left channel negative input 14 INLP Input Left channel positive input Enable pin. Active High Under−voltage detection pin. Left Channel Output ABSOLUTE MAXIMUM RATINGS (Note 1) Parameter Symbol Value Unit VDD −0.3 to 5.5 V Input Voltage VI VSS – 0.3 to VDD + 0.3 V Minimum Load Impedance RL >600 W –0.3 to VDD +0.3 V TJ(max) −40 to 150 °C Supply Voltage, VDD to GND Logic Pin Voltage (EN) Maximum Junction Temperature Storage Temperature Range ESD Capability (Note 2) Human Body Model Machine Model Latch−up Current (Note 3) Moisture Sensitivity Level (Note 4) TSTG −40 to 150 °C ESDHBM ESDMM 2000 200 V ILU 100 mA MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115) 3. Latch−up Current tested per JEDEC standard: JESD78 4. Moisture Sensitivity Level tested per IPC/JEDEC standard: J−STD−020A THERMAL CHARACTERISTICS Parameter Junction−to−Ambient Thermal Resistance, TSSOP−14 (Note 5) 5. Values based on copper area of 645 mm2 (or 1 in2) Symbol Value Unit qJA 115 °C/W of 1 oz copper thickness and FR4 PCB substrate. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit VDD 2.2 3.3 5.5 V High−Level Input Voltage VIH (EN) 1.2 Low−Level Input Voltage VIL (EN) Supply Voltage with UVP connected to Ground Ambient Temperature TA http://onsemi.com 3 −40 V 0.4 V 85 °C NCS2632 ELECTRICAL CHARACTERISTICS, TA = 25°C (unless otherwise noted) Parameter Symbol Test Conditions |VOS| VDD = 2.5 V to 5 V, Voltage follower − gain = 1 High−Level Input Current (EN) |IIH| Low−Level Input Current (EN) Supply Current Output Offset Voltage Min Typ Max Unit 100 400 mV VDD = 5 V, VI = VDD 100 nA |IIL| VDD = 5 V, VI = 0 V 100 nA IDD VDD = 2.2 V, No load, EN = VDD 7 11 mA VDD = 5.5 V, No load, EN = VDD 8 11 mA 60 500 nA Shutdown mode, VDD = 2.2 V to 5.5 V Under−Voltage Protection (UVP) Threshold VUVP UVP Internal Hysteresis Current Source IHYS 5 mA fcp 400 kHz Charge Pump Frequency 1.25 V OPERATING CHARACTERISTICS VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted) Parameter Symbol Test Conditions Min VO THD = 1%, VDD = 3.3 V, f = 1 kHz 2.05 THD = 1%, VDD = 5 V, f = 1 kHz 3.05 THD = 1%, VDD = 5 V, f = 1 kHz, RL = 100 kW 3.1 Output Voltage (Outputs In Phase) Total Harmonic Distortion plus Noise THD+N Typ Max Unit Vrms VO = 2 Vrms, f = 1 kHz 0.001 % VO = 2 Vrms, f = 10 kHz 0.001 % dB Power Supply Rejection PSRR VDD = 2.5 V to 5 V 90 Crosstalk XTALK VO = 2 Vrms, f = 1 kHz −120 dB IO VDD = 3.3 V 21 mA Output Current Limit Input Resistor Range (Note 6) RIN 1 10 47 kW Feedback Resistor Range (Note 6) Rfb 4.7 20 100 kW Maximum Capacitive Load (Note 6) COUT 220 pF Noise Output Voltage VN A−weighted 8 mVrms Signal to Noise Ratio SNR VO = 2 Vrms, THD + N = 0.1% A−weighted filter 105 dB 6. Guaranteed by design. http://onsemi.com 4 NCS2632 TYPICAL CHARACTERISTICS VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted) 10 0.1 0.01 0.01 0.1 0.0001 10 0.1 1 10 Figure 4. THD+N vs. Output Voltage over Temperature, RL = 2.5 kW, VDD = 5 V, f = 1 kHz 10 VDD = 2.0 V VDD = 3.0 V VDD = 3.3 V VDD = 4.0 V VDD = 4.2 V VDD = 5.0 V VDD = 5.5 V 0.1 VDD = 2.2 V VDD = 3.0 V VDD = 3.3 V VDD = 3.6 V VDD = 4.2 V VDD = 5.0 V VDD = 5.5 V 1 0.01 0.001 0.1 0.01 0.001 0.01 0.1 0.1 1 0.0001 10 0.01 0.1 1 10 VOUT (V) VOUT (V) Figure 5. THD+N vs. Output Voltage over Supply, RL = 2.5 kW, f = 1 kHz Figure 6. THD+N vs. Output Voltage over Supply, RL = 600 W, f = 1 kHz 0.1 VDD = 5 V, VOUT = 3 V VDD = 3.3 V, VOUT = 2 V VDD = 2.2 V, VOUT = 1.4 V VDD = 3.3 V, VOUT = 2.2 V VDD = 5 V, VOUT = 3.3 V 0.01 THD+N (%) THD+N (%) 0.01 Figure 3. THD+N vs. Output Voltage over Temperature, RL = 2.5 kW, VDD = 3.3 V, f = 1 kHz THD+N (%) THD+N (%) 1 VOUT (V) 1 0.01 0.001 0.001 0.0001 0.01 VOUT (V) 10 0.0001 0.1 0.001 0.001 0.0001 −40°C 25°C 85°C 125°C 1 THD+N (%) 1 THD+N (%) 10 −40°C 25°C 85°C 125°C 20 200 2000 0.0001 20,000 20 200 2000 20,000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. THD+N vs. Frequency, RL = 2.5 kW Figure 8. THD+N vs. Frequency, RL = 600 W http://onsemi.com 5 NCS2632 TYPICAL CHARACTERISTICS 6.00 6.00 5.98 5.98 5.96 5.96 GAIN (dB) GAIN (dB) VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted) 5.94 VDD = 2.2 V, VOUT = 1.4 V VDD = 3.3 V, VOUT = 2 V VDD = 5 V, VOUT = 3 V 5.92 20 200 2000 5.90 20,000 2000 Figure 9. Gain vs. Frequency, RL = 2.5 kW Figure 10. Gain vs. Frequency, RL = 600 W −20 −20 −40 −40 −60 −80 −100 20,000 −60 −80 −100 −120 −120 20 200 2000 −140 20,000 2000 Figure 11. Crosstalk vs. Frequency, RL = 2.5 kW, VDD = 3.3 V, VO = 2 Vrms Figure 12. Crosstalk vs. Frequency, RL = 2.5 kW, VDD = 5 V, VO = 2 Vrms 0 100 −20 80 −40 60 40 200 20,000 VDD = 2.2 V VDD = 3.3 V VDD = 5 V −60 −80 −100 VDD = 5 V, VOUT = 3 Vrms VDD = 3.3 V, VOUT = 2 Vrms 20 200 FREQUENCY (Hz) 120 20 20 FREQUENCY (Hz) PSRR (dB) SNR (dB) 200 FREQUENCY (Hz) 0 0 20 FREQUENCY (Hz) 0 −140 VDD = 3.3 V, VOUT = 2 V VDD = 5 V, VOUT = 3 V 5.92 CROSSTALK (dB) CROSSTALK (dB) 5.90 5.94 2000 −120 20,000 20 200 2000 20,000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Signal−to−Noise Ratio vs. Frequency, RL = 2.5 kW Figure 14. Power Supply Rejection Ratio vs. Frequency, RL = 2.5 kW http://onsemi.com 6 NCS2632 TYPICAL CHARACTERISTICS VDD = 3.3 V, TA = 25°C, RL = 2.5 kW, CVSS = 1 mF, CIN = 10 mF, RIN = 10 kW, Rfb = 20 kW (unless otherwise noted) 6 5 8.0 4 7.5 ⎢VSS⎜ (V) SUPPLY CURRENT (mA) 8.5 7.0 2 VDD = 2.2 V VDD = 3.0 V VDD = 5.0 V VDD = 5.5 V 6.5 6.0 −40 25 3 1 0 −50 85 VDD = 3.3 V VDD = 5 V −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Quiescent Current vs. Temperature, No Load, VI = 0 V, EN = High Figure 16. VSS vs. Temperature EN tOFF ≈ 80 ms EN tON ≈ 650 ms OUT OUT VSS VSS Figure 18. Shutdown Turn−Off Time, RL = 2.5 kW, VDD = 5 V Figure 17. Startup Turn−On Time, RL = 2.5 kW, VDD = 5 V EN EN tOFF ≈ 100 ms OUT tON ≈ 550 ms OUT VSS VSS Figure 20. Shutdown Turn−Off Time, RL = 2.5 kW, VDD = 3.3 V Figure 19. Startup Turn−On Time, RL = 2.5 kW, VDD = 3.3 V http://onsemi.com 7 125 NCS2632 APPLICATION INFORMATION DESCRIPTION disable, contributing this way to eliminate potential source of pop noise. The device shuts down when the UVP voltage goes below 1.25 V typically. To monitor the lower main power supply limit, an external voltage divider constituted with three resistors, RUP, RDW and RHYS is used (Figure 21). Resistors values have to be chosen based on the requested power supply shutdown threshold and hysteresis for a given application. It is recommended to have RHYS >> RDW // RUP. RHYS is optional in the case where hysteresis is not necessary. The NCS2632 is a stereo line driver with a NOCAP architecture. This architecture eliminates the need to use two large, external capacitors required by conventional audio line driver applications. The NCS2632 is basically composed of two true ground amplifiers with internal power supply rail, one UVP−circuit block, and short−circuit protection. The gain of the NCS2632 can be adjusted with two external resistors. The NOCAP approach is a patented architecture that requires only two 1 mF low ESR ceramic capacitors (fly capacitor and reservoir capacitor). It generates a symmetrical positive and negative voltage and it allows the output of the amplifiers to be biased around the ground (True Ground). The NCS2632 includes a special circuitry for eliminating any pop and click noise during turn on and turn off time. This circuitry combined with the true ground output architecture and a trimmed output offset voltage makes the elimination of pop and click particularly efficient. Board Main Power Suppply IHYS RUP On/Off UVP PVDD RHYS Vn UNDER−VOLTAGE PROTECTION (UVP) PIN MANAGEMENT RDW The UVP pin can be used to shut down the audio line driver by monitoring the board’s main power supply. Then the line driver can be shut down before upstream devices Figure 21. Voltage Divider Connected to UVP for Power Supply Monitoring http://onsemi.com 8 NCS2632 When the resistor divider is connected to the pin UVP as shown in Figure 21, the UVP pin voltage is a function of PVDD and IHYS according to the below equation: V UVP + PVDD With VUVPth = 1.25 V and IHYS = 5 mA ǒ RDW RDW ) RHYS RDW ) RUP RUP RDW ) RUP Ǔ I HYS (eq. 1) This gives a PVDD Shutdown threshold. PVDD Shutdown Threshold: PVDD SD + V UVPth RDW ) RUP RDW RUP ǒRHYS ) RDW Ǔ RDW ) RUP * I HYS RDW ) RUP RDW (eq. 2) Simplified PVDD Shutdown threshold assuming RHYS >> RDW // RUP: PVDD SD + ǒV UVPth * I HYS RDW ) RUP RHYSǓ (eq. 3) RDW The PVDD Startup threshold is given by the below equation. PVDD Hysteresis: RDW ) RUP PVDD UP + V UVPth (eq. 4) RDW The hysteresis component is: PVDD Hysteresis: RUP ǒRHYS ) RDW Ǔ RDW ) RUP DPVDD + V HYS + I HYS + I HYS ǒRHYS ) RDWRDWRUP ) RUPǓ RDW ) RUP RDW PVDD UP (eq. 5) V UVPth Simplified PVDD Hysteresis assuming RYS >> RDW // RUP: DPVDD + V HYS + I HYS RHYS RDW ) RUP RDW For a given PVDD threshold RUP will be a function of RDW. RUP and RDW: RUP + ǒ PVDD UP V UVPth Ǔ *1 + I HYS RYS RDW PVDD UP V UVPth (eq. 6) (eq. 7) According to Equation 6, assuming RHYS >> RDW // RUP, and for a given hysteresis VHYS and PVDD threshold, RHYS is: RHYS RHYS + V HYS I HYS V UVPth PVDD UP + 1.25 5 mA V HYS PVDD UP For example, to get PVDDSD = 2.5 V and 0.625 V hysteresis, Power Divider Resistors have to be: RUP = 1.5 kW, RDW = 1 kW and RHYS = 51 kW http://onsemi.com 9 (eq. 8) NCS2632 GAIN SETTING RESISTOR SELECTION (RIN and RFB) A closed−loop gain in the range of 1 to 10 is recommended to optimize overall system performance. Selecting values that are too low requires a relatively large input ac-coupling capacitor, CIN. Selecting values that are too high increases the overall noise of the amplifier. RIN and RFB set the closed−loop gain of the amplifier. The resistor values have to be chosen so that amplifier stability is preserved. A low gain configuration (close to 1) minimizes the THD + noise values and maximizes the signal to noise ratio. RFB Vin− CIN RIN Av + Vin+ CIN Vout Vin+ * Vin− + R FB R in (eq. 9) Vout RIN RFB Figure 22. Differential Input Gain Configuration R FB CIN R IN Vin− Av + Vout Vin− + −R FB R IN (eq. 10) Vout Figure 23. Inverting Gain Configuration CIN Vin+ Rx Av + Vout RFB RIN CIN Figure 24. Non−Inverting Gain Configuration http://onsemi.com 10 V out Vin+ +1) R FB R IN (eq. 11) NCS2632 Table 1. RECOMMENDED RESISTOR VALUES Input Resistor Value, RIN Feedback Resistor Value, RFB Differential Input Gain Inverting Input Gain Non Inverting Input Gain 22 kW 22 kW 1.0 V/V –1.0 V/V 2.0 V/V 22 kW 33 kW 1.5 V/V –1.5 V/V 2.5 V/V 33 kW 68 kW 2.06 V/V –2.06 V/V 3.1 V/V 100 kW 10.0 V/V –10.0 V/V 11.0 V/V 10 kW INPUT CAPACITOR THD+N. Use a X5R / X7R ceramic capacitor and place it close to the VDD pin. A value of 1mF is recommended. For filtering lower frequency noise signals, a 10 mF or greater capacitor placed near the audio power amplifier would also help. The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with RIN. The size of the capacitor must be large enough to couple at low frequencies without severe attenuation in the audio bandwidth (20 Hz − 20 kHz). The cut off frequency for the input high−pass filter is: fc + 1 2pR inC in SHUTDOWN FUNCTION The device enters shutdown mode when Enable signal is low. During the shutdown mode, the internal charge pump is shut down, and the DC quiescent current of the circuit does not exceed 500 nA. The output is pulled to ground through a low output impedance of about 40 ohms. (eq. 12) A fc < 20 Hz is recommended. CHARGE PUMP CAPACITOR SELECTION USING THE NCS2632 AS A 2nd ORDER FILTER It is recommended to use ceramic capacitors with low ESR for better performances. X5R or X7R capacitors are recommended. The flying capacitor Cfly (1 mF) serves to transfer charge during the generation of the negative voltage. The VSS reservoir capacitor CVSS must be equal at least to the Cfly capacitor to allow maximum charge transfer. The 1 mF capacitors have to be connected as close as possible to the corresponding pins. Lower value capacitors can be used but the device may not operate to specifications. Audio DACs can require an external low-pass filter to remove out-of-band noise. This is possible with the NCS2632, which can be used as a standard Operational Amplifier with the advantage of better performances including “pop & click” noise behavior. Single-ended and differential topologies can be implemented. In Figures 25 and 26, a Multiple-FeedBack (MFB) topoplogy, with differential inputs and single-ended inputs is shown. The two topologies use AC-Coupling capacitors (CIN) to block the DC-signal component coming from the source; they contribute to reducing the output offset voltage. POWER SUPPLY DECOUPLING CAPACITORS The NCS2632 is a True Ground amplifier that requires an adequate decoupling capacitor on VDD to reduce noise and R FB C IN RIN CINT RINT Vin− C DIFF Vout Vin+ CIN RIN RINT CINT RFB Figure 25. 2nd Order Active Low Pass Filter − Differential Input http://onsemi.com 11 NCS2632 RFB C IN R IN C INT RINT Vin− CT Vout Figure 26. 2nd Order Active Low Pass Filter − Inverting Input INITIALIZATION AND POP−FREE POWER UP/DOWN Pop−free power−up/−down is ensured by keeping EN (Enable pin) low during power supply ramp−up or ramp−down. The EN pin should be kept low until the input ac−coupling capacitors are fully charged before asserting the EN pin high; this way, proper pre−charge of the ac−coupling is performed, and pop−free power−up is achieved. Figure 27 illustrates the preferred sequence. For an on/off/on power sequence, VDD is required to be ramped down to 0 V before ramping back up for power on (shown in Figure 27). This ensures that the NCS2632 internal circuits are properly initialized to guarantee an optimal output. +VDD VDD Ramp−up VDD Supply VDD Ramp−down 0V EN 0V Internal VSS Supply (Negative Rail) VSS VSS −VDD Dtcharge Dtdischarge AC−coupled Input Capacitor Pre−Charge Time Capacitor Discharge Figure 27. Initialization and Power Up/Down Sequence CAPACITIVE LOAD ESD PERFORMANCE The NCS2632 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be accepted by adding a series resistor of 10 W or larger. From the system level perspective, the outputs of the NCS2632 are rated to Level 4 of the IEC61000−4−2 ESD standard. Using the contact discharge method, the outputs pass a ±8 kV discharge with an RC network of R = 33 ohms and C = 1 nF at each output to simulate the application environment. http://onsemi.com 12 NCS2632 APPLICATION SCHEMATIC C1 R1 LEFT INPUT C1 R1 − R3 R2 C2 R2 C3 + C3 R3 INLP INLM 1mF LEFT OUTPUT Regulated VDD 3.3V/5.0 V OUTL EN ENABLE RUP CP Charge Pump Circuitry 1mF CN Click/Pop Suppression Circuitry Bias Circuitry AGND AGND Board Main Power Suppply UVP RDW PGND OUTR AGND VSS RIGHT OUTPUT 1mF C3 − C1 R1 RIGHT INPUT + INRP INRM R3 C1 R1 C3 R2 C2 R2 R3 R1 = R2 = R3 = 5.6 kW, C1 = 100 nF, C2 = 470 pF, C3 = 220 pF Figure 28. Application Schematic ORDERING INFORMATION Device NCS2632DTBR2G Package Shipping† TSSOP−14 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOCAP is a trademark of Semiconductor Components Industries, LLC (SCILLC). Blu−ray and Blu−ray Disc are trademarks of Blu−ray Disc Association. http://onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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