NCV33163
2.5 A, Step-Up/Down/
Inverting Switching
Regulators
The NCV33163 series are monolithic power switching regulators
that contain the primary functions required for DC−to−DC converters.
This series is specifically designed to be incorporated in step−up,
step−down, and voltage−inverting applications with a minimum
number of external components.
These devices consist of two high gain voltage feedback
comparators, temperature compensated reference, controlled duty
cycle oscillator, driver with bootstrap capability for increased
efficiency, and a high current output switch. Protective features consist
of cycle−by−cycle current limiting, and internal thermal shutdown.
Also included is a low voltage indicator output designed to interface
with microprocessor based systems.
These devices are contained in a 16 pin dual−in−line heat tab plastic
package for improved thermal conduction.
•
MARKING
DIAGRAMS
16
16
PDIP−16
P SUFFIX
CASE 648C
1
NCV33163P
AWLYYWWG
1
16
SO−16WB
DW SUFFIX
CASE 751G
16
NCV33163DW
AWLYYWWG
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
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Output Switch Current in Excess of 2.0 A
Operation from 2.5 V to 60 VOC Input
Low Standby Current
Precision 2% Reference
Controlled Duty Cycle Oscillator
Driver with Bootstrap Capability for Increased Efficiency
Cycle−by−Cycle Current Limiting
Internal Thermal Shutdown Protection
Low Voltage Indicator Output for Direct Microprocessor Interface
Heat Tab Power Package
Moisture Sensitivity Level (MSL) Equals 1
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
Pb−Free Packages are Available
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
LVI Output
1
16 Bootstrap Input
Voltage Feedback 2
2
15
Voltage Feedback 1
3
14
4
13
5
12
Timing Capacitor
6
11
VCC
7
10
Ipk Sense
8
9 Driver Collector
Switch
Emitter
GND
GND
Switch Collector
(Top View)
ORDERING INFORMATION
Shipping†
Device
Package
NCV33163P
PDIP−16
25 Units / Rail
NCV33163PG
PDIP−16
(Pb−Free)
25 Units / Rail
NCV33163DWR2
SO−16WB 1000 Tape & Reel
NCV33163DWR2G SO−16WB 1000 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
NCV33163/D
NCV33163
Ipk Sense
8
ILimit
-
9
Driver
Collector
+
VCC
Timing
Capacitor
10
7
+
6
11
OSC
5
12
Control Logic
and Thermal
Shutdown
GND
4
Voltage
Feedback 1
Switch
Collector
GND
13
+
14
3
Voltage
Feedback 2
2
LVI Output
1
+
+
-
Switch
Emitter
VFB
15
LVI
+
+
-
16
Bootstrap
Input
+
(Bottom View)
This device contains 114 active transistors.
Figure 1. Representative Block Diagram
MAXIMUM RATINGS (Note 1)
Rating
Power Supply Voltage
Symbol
Value
Unit
VCC
60
V
Switch Collector Voltage Range
VC(switch)
−1.0 to + 60
V
Switch Emitter Voltage Range
VE(switch)
− 2.0 to VC(switch)
V
Switch Collector to Emitter Voltage
VCE(switch)
60
V
Switch Current (Note 2)
ISW
2.5
A
Driver Collector Voltage
VC(driver)
−1.0 to +60
V
Driver Collector Current
IC(driver)
150
mA
IBS
−100 to +100
mA
VIpk (Sense)
(VCC−7.0) to (VCC+1.0)
V
Vin
−1.0 to + 7.0
V
Low Voltage Indicator Output Voltage Range
VC(LVI)
−1.0 to + 60
V
Low Voltage Indicator Output Sink Current
IC(LVI)
10
mA
Bootstrap Input Current Range (Note 2)
Current Sense Input Voltage Range
Feedback and Timing Capacitor Input Voltage Range
°C/W
Thermal Characteristics
P Suffix, Dual−In−Line Case 648C
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13)
DW Suffix, Surface Mount Case 751G
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case (Pins 4, 5, 12, 13)
RqJA
RqJC
80
15
RqJA
RqJC
94
18
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature
TA
− 40 to + 115
°C
Storage Temperature Range
Tstg
− 65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 1500 V per MIL−STD−883, Method 3015.
Machine Model Method 150 V.
2. Maximum package power dissipation limits must be observed.
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NCV33163
ELECTRICAL CHARACTERISTICS
(VCC = 15 V, Pin 16 = VCC, CT = 620 pF, for typical values TA = 25°C, for min/max values TA = −40°C to +115°C.)
Symbol
Characteristic
Min
Typ
Max
46
45
55
−
59
60
Unit
OSCILLATOR
Frequency
TA = 25°C
Total Variation over VCC = 2.5 V to 60 V, and Temperature
fOSC
Charge Current
Ichg
−
225
−
mA
Idischg
−
25
−
mA
Ichg/Idischg
8.0
9.0
10
−
Sawtooth Peak Voltage
VOSC(P)
−
1.25
−
V
Sawtooth Valley Voltage
VOSC(V)
−
0.55
−
V
4.9
−
4.85
5.05
0.008
−
5.2
0.03
5.25
V
%/V
V
−
100
200
mA
1.225
−
1.213
1.25
0.008
−
1.275
0.03
1.287
V
%/V
V
− 0.4
0
0.4
mA
−
230
250
−
−
270
−
1.0
20
−
−
0.6
1.0
1.0
1.4
−
0.02
100
mA
Discharge Current
Charge to Discharge Current Ratio
kHz
FEEDBACK COMPARATOR 1
Threshold Voltage
TA = 25°C
Line Regulation (VCC = 2.5 V to 60 V, TA = 25°C)
Total Variation over Line, and Temperature
Vth(FB1)
Input Bias Current (VFB1 = 5.05 V)
IIB(FB1)
FEEDBACK COMPARATOR 2
Threshold Voltage
TA = 25°C
Line Regulation (VCC = 2.5 V to 60 V, TA = 25°C)
Total Variation over Line, and Temperature
Vth(FB2)
Input Bias Current (VFB2 = 1.25 V)
IIB(FB2)
CURRENT LIMIT COMPARATOR
Threshold Voltage
TA = 25°C
Total Variation over VCC = 2.5 V to 60 V, and Temperature
Vth(Ipk Sense)
Input Bias Current (VIpk (Sense) = 15 V)
IIB(sense)
mV
mA
DRIVER AND OUTPUT SWITCH (Note 3)
Sink Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded)
Non−Darlington Connection (RPin 9 = 110 W to VCC, ISW/IDRV ≈ 20)
Darlington Connection (Pins 9, 10, 11 connected)
VCE(sat)
Collector Off−State Leakage Current (VCE = 60 V)
IC(off)
Bootstrap Input Current Source (VBS = VCC + 5.0 V)
V
Isource(DRV)
0.5
2.0
4.0
mA
VZ
VCC +
6.0
VCC +
7.0
VCC +
9.0
V
Input Threshold (VFB2 Increasing)
Vth
1.07
1.125
1.18
V
Input Hysteresis (VFB2 Decreasing)
VH
−
15
−
mV
Output Sink Saturation Voltage (Isink = 2.0 mA)
VOL(LVI)
−
0.15
0.4
V
Output Off−State Leakage Current (VOH = 15 V)
IOH
−
0.01
5.0
mA
ICC
−
6.0
10
mA
Bootstrap Input Zener Clamp Voltage (IZ = 25 mA)
LOW VOLTAGE INDICATOR
TOTAL DEVICE
Standby Supply Current (VCC = 2.5 V to 60 V, Pin 8 = VCC,
Pins 6, 14, 15 = GND, remaining pins open)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
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100
10
VCC = 15 V
TA = 25°C
1)ton, RDT = ∞
2)ton, RDT = 20 k
3)ton, toff, RDT = 10 k
4)toff, RDT = 20 k
5)toff, RDT = ∞
Δ f OSC, OSCILLATOR FREQUENCY CHANGE (%)
t on -t off , OUTPUT SWITCH ON-OFF TIME ( μ s)
NCV33163
1
2
3
4
5
1.0
0.1
1.0
CT, OSCILLATOR TIMING CAPACITOR (nF)
10
2.0
VCC = 15 V
CT = 620 pF
0
-2.0
-4.0
-6.0
-55
-25
IIB , INPUT BIAS CURRENT (A)
μ
140
VCC = 15 V
VFB1 = 5.05 V
120
100
80
60
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
V Z, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (V)
I source (DRV), BOOTSTRAP INPUT CURRENT SOURCE (mA)
Figure 4. Feedback Comparator 1 Input Bias
Current versus Temperature
2.8
VCC = 15 V
Pin 16 = VCC + 5.0 V
2.4
2.0
1.6
1.2
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
100
125
Figure 3. Oscillator Frequency Change
versus Temperature
V th(FB2) , COMPARATOR 2 THRESHOLD VOLTAGE (mV)
Figure 2. Output Switch On−Off Time
versus Oscillator Timing Capacitor
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
125
1300
Vth Max = 1275 mV
VCC = 15 V
1280
1260
Vth Typ = 1250 mV
1240
Vth Min = 1225 mV
1220
1200
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 5. Feedback Comparator 2 Threshold
Voltage versus Temperature
7.6
IZ = 25 mA
7.4
7.2
7.0
6.8
-55
Figure 6. Bootstrap Input Current
Source versus Temperature
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 7. Bootstrap Input Zener Clamp
Voltage versus Temperature
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125
125
NCV33163
1.2
VCC
-0.4
-0.8
Bootstrapped, Pin 16 = VCC + 5.0 V
-1.2
-1.6
-2.0
Darlington Configuration
Emitter Sourcing Current to GND
Pins 7, 8, 10, 11 = VCC
Pins 4, 5, 12, 13 = GND
TA = 25°C, (Note 2)
VCE (sat), SINK SATURATION (V)
VCE (sat), SOURCE SATURATION (V)
0
Non-Bootstrapped, Pin 16 = VCC
0
0.8
1.6
2.4
IE, EMITTER CURRENT (A)
0.8
Grounded Emitter Configuration
Collector Sinking Current From VCC
Pins 7, 8 = VCC = 15 V
Pins 4, 5, 12, 13, 14, 15 = GND
TA = 25°C, (Note 2)
Saturated Switch, RPin9 = 110 W to VCC
0.6
0.4
0.2
0
3.2
Darlington, Pins 9, 10, 11 Connected
1.0
GND
0
0.8
Figure 8. Output Switch Source Saturation
versus Emitter Current
V OL (LVI) , OUTPUT SATURATION VOLTAGE (V)
V E , EMITTER VOLTAGE (V)
GND
IC = 10 mA
-0.8
IC = 10 mA
-1.2
VCC = 15 V
Pins 7, 8, 9, 10, 16 = VCC
Pins 4, 6 = GND
Pin 14 Driven Negative
-1.6
-2.0
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0.5
VCC=5 V
TA=25°C
0.4
0.3
0.2
0.1
0
0
252
250
248
-25
8.0
1.6
VCC = 15 V
246
-55
2.0
4.0
6.0
Isink, OUTPUT SINK CURRENT (mA)
Figure 11. Low Voltage Indicator Output Sink
Saturation Voltage versus Sink Current
IIB (Sense), INPUT BIAS CURRENT (μ A)
V th (Ipk Sense) , THRESHOLD VOLTAGE (mV)
Figure 10. Output Switch Negative Emitter
Voltage versus Temperature
254
3.2
Figure 9. Output Switch Sink Saturation
versus Collector Current
0
-0.4
1.6
2.4
IC, COLLECTOR CURRENT (A)
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
VCC = 15 V
VIpk (Sense) = 15 V
1.4
1.2
1.0
0.8
0.6
-55
Figure 12. Current Limit Comparator Threshold
Voltage versus Temperature
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 13. Current Limit Comparator Input Bias
Current versus Temperature
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NCV33163
7.2
I CC, SUPPLY CURRENT (mA)
6.0
4.0
Pins 7, 8, 16 = VCC
Pins 4, 6, 14 = GND
Remaining Pins Open
TA = 25°C
0
0
10
20
30
VCC, SUPPLY VOLTAGE (V)
6.4
5.6
4.8
4.0
-55
40
3.0
1.8
Pin 16 Open
JUNCTION-TO-AIR ( °C/W)
2.2
Pin 16 = VCC
1.4
-25
0
25
50
75
100
80
5.0
RqJA
4.0
2.0 oz
Copper
L
3.0 mm
Graphs represent symmetrical layout
3.0
2.0
40
PD(max) for TA = 70°C
20
0
125
L
60
0
10
20
1.0
30
40
0
50
L, LENGTH OF COPPER (mm)
Figure 16. Minimum Operating Supply
Voltage versus Temperature
Figure 17. P Suffix (DIP−16) Thermal Resistance
and Maximum Power Dissipation
versus P.C.B. Copper Length
100
2.8
PD(max) for TA = 50°C
90
80
2.4
ÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎ
Graph represents symmetrical layout
70
L
60
2.0 oz.
Copper
L
50
3.0 mm
RqJA
40
10
2.0
1.6
1.2
0.8
0.4
30
0
125
Printed circuit board heatsink example
TA, AMBIENT TEMPERATURE (°C)
JUNCTION-TO-AIR ( °C/W)
1.0
-55
100
ÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
100
R θ JA, THERMAL RESISTANCE
2.6
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 15. Standby Supply Current
versus Temperature
CT = 620 pF
Pins 7,8 = VCC
Pins 4, 14 = GND
Pin 9 = 1.0 kW to 15 V
Pin 10 = 100 W to 15 V
R θ JA, THERMAL RESISTANCE
V CC(min) , MINIMUM OPERATING SUPPLY VOLTAGE (V)
Figure 14. Standby Supply Current
versus Supply Voltage
-25
20
30
40
0
50
L, LENGTH OF COPPER (mm)
Figure 18. DW Suffix (SOP−16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
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P D , MAXIMUM POWER DISSIPATION (W)
2.0
VCC = 15 V
Pins 7, 8, 16 = VCC
Pins 4, 6, 14 = GND
Remaining Pins Open
PD, MAXIMUM POWER DISSIPATION (W)
I CC, SUPPLY CURRENT (mA)
8.0
NCV33163
Ipk Sense
RSC
7
VCC
Timing Capacitor
CT
RDT
Shutdown
0.25 V
+
8
6
Current
Limit
+
9
10
+
Switch Collector
Oscillator
11
Q1
Q2
R
Q
S
Latch
5
Thermal
GND
4
Voltage Feedback 1
12
60
GND
13
+
3
14
45 k
Voltage Feedback 2
LVI Output
Driver Collector
2
+
+
+
-
1
LVI
Switch Emitter
Feedback
Comparator
+
+
-
15
2.0 mA
1.25 V 15 k
+
1.125 V
+
7.0 V
16 Bootstrap Input
+
-
(Bottom View)
Figure 19. Representative Block Diagram
1
Comparator Output
0
1.25 V
Timing Capacitor CT
0.55 V
t
9t
1
Oscillator Output
0
On
Output Switch
Off
Nominal Output
Voltage Level
Output Voltage
Startup
Quiescent Operation
Figure 20. Typical Operating Waveforms
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= Sink Only
Positive True Logic
NCV33163
INTRODUCTION
resistor increases the discharge current which reduces the
on−time of the output switch. A graph of the Output Switch
On−Off Time versus Oscillator Timing Capacitance for
various values of RDT is shown in Figure 2. Note that the
maximum output duty cycle, ton/ton + toff, remains constant
for values of CT greater than 0.2 nF. The converter output
can be inhibited by clamping CT to ground with an external
NPN small−signal transistor.
The NCV33163 series are monolithic power switching
regulators optimized for DC−to−DC converter applications.
The combination of features in this series enables the system
designer to directly implement step−up, step−down, and
voltage−inverting converters with a minimum number of
external components. Potential applications include cost
sensitive consumer products as well as equipment for the
automotive, computer, and industrial markets. A
Representative Block Diagram is shown in Figure 19.
Feedback and Low Voltage Indicator Comparators
Output voltage control is established by the Feedback
comparator. The inverting input is internally biased at 1.25 V
and is not pinned out. The converter output voltage is
typically divided down with two external resistors and
monitored by the high impedance noninverting input at Pin 2.
The maximum input bias current is ±0.4 mA, which can cause
an output voltage error that is equal to the product of the input
bias current and the upper divider resistance value. For
applications that require 5.0 V, the converter output can be
directly connected to the noninverting input at Pin 3. The high
impedance input, Pin 2, must be grounded to prevent noise
pickup. The internal resistor divider is set for a nominal
voltage of 5.05 V. The additional 50 mV compensates for a
1.0% voltage drop in the cable and connector from the
converter output to the load. The Feedback comparator’s
output state is controlled by the highest voltage applied to
either of the two noninverting inputs.
The Low Voltage Indicator (LVI) comparator is designed
for use as a reset controller in microprocessor−based
systems. The inverting input is internally biased at 1.125 V,
which sets the noninverting input thresholds to 90% of
nominal. The LVI comparator has 15 mV of hysteresis to
prevent erratic reset operation. The Open Collector output is
capable of sinking in excess of 6.0 mA (see Figure 11). An
external resistor (RLVI) and capacitor (CDLY) can be used to
program a reset delay time (tDLY) by the formula shown
below, where Vth(MPU) is the microprocessor reset input
threshold. Refer to Figure 21.
OPERATING DESCRIPTION
The NCV33163 operates as a fixed on−time, variable
off−time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 20. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the feedback comparator sets the latch, immediately
terminating switch conduction. The feedback comparator
will inhibit the switch until the load current causes the output
voltage to fall below nominal. Under these conditions,
output switch conduction can be inhibited for a partial
oscillator cycle, a partial cycle plus a complete cycle,
multiple cycles, or a partial cycle plus multiple cycles.
Oscillator
The oscillator frequency and on−time of the output switch
are programmed by the value selected for timing capacitor
CT. Capacitor CT is charged and discharged by a 9 to 1 ratio
internal current source and sink, generating a negative going
sawtooth waveform at Pin 6. As CT charges, an internal
pulse is generated at the oscillator output. This pulse is
connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
allowing the latch to be reset if the comparator output is low.
Thus, the output switch is always disabled during ramp−up
and can be enabled by the comparator output only at the start
of ramp−down. The oscillator peak and valley thresholds are
1.25 V and 0.55 V, respectively, with a charge current of
225 mA and a discharge current of 25 mA, yielding a
maximum on−time duty cycle of 90%. A reduction of the
maximum duty cycle may be required for specific converter
configurations. This can be accomplished with the addition
of an external deadtime resistor (RDT) placed across CT. The
tDLY = RLVI CDLY In
ǒ
1
Vth(MPU)
1−
Vout
Ǔ
Current Limit Comparator, Latch and Thermal
Shutdown
With a voltage mode ripple converter operating under
normal conditions, output switch conduction is initiated by
the oscillator and terminated by the Voltage Feedback
comparator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Current Limit
comparator will protect the Output Switch.
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NCV33163
additional device heating and reduced conversion
efficiency.
Figure 10 shows that by clamping the emitter to 0.5 V, the
collector current will be in the range 10 mA over
temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements.
A bootstrap input is provided to reduce the output switch
saturation voltage in step−down and voltage−inverting
converter applications. This input is connected through a
series resistor and capacitor to the switch emitter and is used
to raise the internal 2.0 mA bias current source above VCC.
An internal zener limits the bootstrap input voltage to VCC
+7.0 V. The capacitor’s equivalent series resistance must
limit the zener current to less than 100 mA. An additional
series resistor may be required when using tantalum or other
low ESR capacitors. The equation below is used to calculate
a minimum value bootstrap capacitor based on a minimum
zener voltage and an upper limit current source.
The switch current is converted to a voltage by inserting
a fractional ohm resistor, RSC, in series with VCC and output
switch transistor Q2. The voltage drop across RSC is
monitored by the Current Sense comparator. If the voltage
drop exceeds 250 mV with respect to VCC, the comparator
will set the latch and terminate output switch conduction on
a cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle. The
calculation for a value of RSC is:
RSC +
0.25 V
Ipk (Switch)
Figures 12 and 13 show that the Current Sense comparator
threshold is tightly controlled over temperature and has a
typical input bias current of 1.0 mA. The propagation delay
from the comparator input to the Output Switch is typically
200 ns. The parasitic inductance associated with RSC and the
circuit layout should be minimized. This will prevent
unwanted voltage spikes that may falsely trip the Current
Limit comparator.
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 170°C, the Latch
is forced into the “Set” state, disabling the Output Switch.
This feature is provided to prevent catastrophic failures from
accidental device overheating. It is not intended to be used
as a replacement for proper heatsinking.
CB(min) + I Dt + 4.0 mA ton + 0.001 ton
DV
4.0 V
Parametric operation of the NCV33163 is guaranteed
over a supply voltage range of 2.5 V to 60 V. When operating
below 3.0 V, the Bootstrap Input should be connected to
VCC. Figure 16 shows that functional operation down to
1.7 V at room temperature is possible.
Package
The NCV33163 is contained in a heat−sinkable 16−lead
plastic dual−in−line package in which the die is mounted on
a special heat tab copper alloy lead frame. This tab consists
of the four center ground pins that are specifically designed
to improve thermal conduction from the die to the circuit
board. Figures 17 and 18 show a simple and effective
method of utilizing the printed circuit board medium as a
heat dissipater by soldering these pins to an adequate area of
copper foil. This permits the use of standard layout and
mounting practices while having the ability to halve the
junction−to−air thermal resistance. These examples are for
a symmetrical layout on a single−sided board with two
ounce per square foot of copper.
Driver and Output Switch
To aid in system design flexibility and conversion
efficiency, the driver current source and collector, and
output switch collector and emitter are pinned out
separately. This allows the designer the option of driving the
output switch into saturation with a selected force gain or
driving it near saturation when connected as a Darlington.
The output switch is designed to switch a maximum of 60 V
collector to emitter, with up to 2.5 A peak collector current.
The minimum value for RSC is:
RSC(min) +
0.25 V
+ 0.100 W
2.5 A
When configured for step−down or voltage−inverting
applications, as in Figures 21 and 25, the inductor will
forward bias the output rectifier when the switch turns off.
Rectifiers with a high forward voltage drop or long turn−on
delay time should not be used. If the emitter is allowed to go
sufficiently negative, collector current will flow, causing
APPLICATIONS
The following converter applications show the simplicity
and flexibility of this circuit architecture. Three main
converter topologies are demonstrated with actual test data
shown below each of the circuit diagrams.
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9
NCV33163
0.25 V
+
8
RSC
Vin
12 V
0.075
9
7
+
Cin
330
Current
Limit
+
10
+
6
CT
680 pF
Oscillator
11
Q1
Q2
R
Q
S
Latch
5
Thermal
4
12
60
13
+
3
14
45 k
2
RLVI
10 k
Low Voltage
Indicator Output
1
CDLY
+
+
-
+
LVI
Feedback
Comparator
1N5822
0.02
2.0 mA
1.25 V 15 k
+
1.125 V
+
+
-
15
16
+
7.0 V
CB
L
2200
(Bottom View)
Test
RB
Condition
180 mH
Coilcraft LO451-A
Vout
+
5.05 V/3.0 A
CO
Results
Line Regulation
Vin = 8.0 V to 24 V, IO = 3.0 A
6.0 mV = ± 0.06%
Load Regulation
Vin = 12 V, IO = 0.6 A to 3.0 A
2.0 mV = ± 0.02%
Output Ripple
Vin = 12 V, IO = 3.0 A
36 mVpp
Short Circuit Current
Vin = 12 V, RL = 0.1 W
3.3 A
Efficiency, Without Bootstrap
Vin = 12 V, IO = 3.0 A
76.7%
Efficiency, With Bootstrap
Vin = 12 V, IO = 3.0 A
81.2%
Figure 21. Step−Down Converter
8
7
9
8
10
7
+
Q3
10
+
6
11
Q1
Q2
5
4
9
+
12
5
13
4
11
Q1
Q2
12
13
+
3
14
15
2
15
16
1
3
14
2
1
6
Q3
+
16
+
(Bottom View)
(Bottom View)
Figure 22A. External NPN Switch
Figure 22B. External PNP Saturated Switch
Figure 22. External Current Boost Connections for Ipk (Switch) Greater Than 2.5 A
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10
NCV33163
0.25 V
+
8
RSC
0.075
Vin
12 V
Cin
+
Current
Limit
+
L
9
7
180 mH
Coilcraft
LO451-A
10
+
330
6
Oscillator
CT
680 pF
11
Q1
Thermal
4
Q2
R
Q
S
Latch
5
12
60
13
+
1N5822
3
14
45 k
2
Low Voltage
Indicator
Output
1
RLVI
1.0 k
R1
2.2 k
+
+
-
+
LVI
+
+
-
Feedback
Comparator
1.25 V 15 k
+
1.125 V
R2
47 k
15
2.0 mA
16
7.0 V
+
Vout
28 V/600 mA
+C
O
(Bottom View)
330
Test
Condition
Results
Line Regulation
Vin = 9.0 V to 16 V, IO = 0.6 A
30 mV = ± 0.05%
Load Regulation
Vin = 12 V, IO = 0.1 A to 0.6 A
50 mV = ± 0.09%
Output Ripple
Vin = 12 V, IO = 0.6 A
140 mVpp
Efficiency
Vin = 12 V, IO = 0.6 A
88.1%
Figure 23. Step−Up Converter
8
7
+
8
10
7
9
10
+
6
11
Q1
Q2
5
4
9
+
12
5
13
4
3
14
2
1
6
11
Q1
Q2
12
13
+
3
14
15
2
15
16
1
Q3
Q3
16
+
+
(Bottom View)
(Bottom View)
Figure 24A. External NPN Switch
Figure 24B. External PNP Saturated Switch
Figure 24. External Current Boost Connections for Ipk (Switch) Greater Than 2.5 A
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11
NCV33163
0.25 V
+
8
RSC
Vin
12 V
0.075
Cin
330
Current
Limit
+
9
7
+
10
+
6
CT
470 pF
Oscillator
11
Q1
Q2
R
Q
S
Latch
5
Thermal
4
12
60
13
+
Coilcraft LO451-A
3
14
L
180 mH
45 k
2
+
1
LVI
R2
8.2 k
+
+
-
Feedback
Comparator
1.25 V 15 k
+
1.125 V
+
+
-
R1
953
15
0.02
2.0 mA
16
+
7.0 V
1N5822
2200
(Bottom View)
Test
RB
CB
Vout
-12 V/1.0 A
+ CO
Condition
Results
Line Regulation
Vin = 9.0 V to 16 V, IO = 1.0 A
5.0 mV = ± 0.02%
Load Regulation
Vin = 12 V, IO = 0.6 A to 1.0 A
2.0 mV = ± 0.01%
Output Ripple
Vin = 12 V, IO = 1.0 A
130 mVpp
Short Circuit Current
Vin = 12 V, RL = 0.1 W
3.2 A
Efficiency, Without Bootstrap
Vin = 12 V, IO = 1.0 A
73.1%
Efficiency, With Bootstrap
Vin = 12 V, IO = 1.0 A
77.5%
Figure 25. Voltage−Inverting Converter
8
7
+
9
8
10
7
9
10
+
6
11
Q1
Q2
6
11
Q1
Q2
12
5
13
4
3
14
3
14
2
15
2
15
5
4
Q3
+
Q3
16
1
13
+
16
1
+
12
+
(Bottom View)
(Bottom View)
Figure 26A. External NPN Switch
Figure 26B. External PNP Saturated Switch
Figure 26. External Current Boost Connections for Ipk (Switch) Greater Than 2.5 A
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12
NCV33163
Step−Down
Calculation
ton
(Notestoff
1, 2, 3)
V
V out ) V
F
* V sat * V out
in
ǒ
ton
ƒ
t on
t
off
Voltage−Inverting
V out ) V – V
F
in
V – V sat
in
|V out| ) V
Ǔ
t on
) 1
t
off
CT
32.143 · 10 –6
ƒ
IL(avg)
Iout
Ipk (Switch)
Step−Up
ƒ
DI
L
2
ǒ
Vripple(pp)
V
DIL
DI
ǒ
1
8ƒ CO
V
Vout
ǒ
L
Ǔ
Ǔ
ǒ
t on
V
R1
Ǔ
DI
L
2
) (ESR)2
[
Ǔ
) 1
V
ǒ
R2
ref
R1
Ǔ
t on
) 1
t
off
ǒ
Ǔ
t on
) 1
t
off
IL(avg) )
t on
ǒ
V
t on I out
C
t on
t
off
DI
L
2
0.25
Ipk (Switch)
Ǔ
L
ǒ
I out
DI
* V sat
in
F
* V sat
in
32.143 · 10 –6
ƒ
t on
) 1
t
off
2
R2
ref
ƒ
0.25
Ipk (Switch)
* V sat * V out
in
ǒ
IL(avg) )
0.25
Ipk (Switch)
L
Ǔ
t on
) 1
t
off
32.143 · 10 –6
ƒ
I out
IL(avg) )
RSC
ǒ
t on
t
off
V
in
C
O
Ǔ
V
L
ǒ
R2
ref
t on
t on I out
[
) 1
Ǔ
* V sat
DI
R1
O
Ǔ
) 1
The following Converter Characteristics must be chosen:
Nominal operating input voltage.
Desired output voltage.
Desired output current.
Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less
than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit
threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will
proportionally reduce converter output current capability.
p − Maximum output switch frequency.
Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value
since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
Vin −
Vout −
Iout −
DIL −
NOTES:
NOTES:
NOTES:
NOTES:
1.
2.
3.
3.
Vsat − Saturation voltage of the output switch, refer to Figures 8 and 9.
VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.
The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum
operating input voltage.
Figure 27. Design Equations
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP
CASE 648C−04
ISSUE D
DATE 07/28/1998
SCALE 1:1
A
T B
B
K
C
N
F
T
E
G
16X
DESCRIPTION:
98ASB42434B
PDIP
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
0.744
0.783
0.240
0.260
0.145
0.185
0.015
0.021
0.050 BSC
0.040
0.70
0.100 BSC
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.040
MILLIMETERS
MIN
MAX
18.90
19.90
6.10
6.60
3.69
4.69
0.38
0.53
1.27 BSC
1.02
1.78
2.54 BSC
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
SEATING
PLANE
D
0.005 (0.13)
DOCUMENT NUMBER:
0.005 (0.13)
J
8
16X
1
L
9
B
16
M
M
A
M
T A
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
1
SCALE 1:1
DATE 08 OCT 2021
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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