Automotive Advanced
Secondary Side LLC
Resonant Converter Controller
with Synchronous Rectifier
Control
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NCV4390
The NCV4390 is an advanced Pulse Frequency Modulated (PFM)
controller for LLC resonant converters with Synchronous
Rectification (SR) that offers best in class efficiency for isolated
DC/DC converters. It employs a current mode control technique based
on a charge control, where the triangular waveform from the oscillator
is combined with the integrated switch current information to
determine the switching frequency. This provides a better
control−to−output transfer function of the power stage simplifying the
feedback loop design while allowing true input power limit capability.
Closed−loop soft−start prevents saturation of the error amplifier and
allows monotonic rising of the output voltage regardless of load
condition. A dual edge tracking adaptive dead time control minimizes
the body diode conduction time thus maximizing efficiency.
• Secondary Side PFM Controller for LLC Resonant Converter with
Synchronous Rectifier Control
• Charge Current Control for Better Transient Response and Easy
•
•
•
•
•
•
•
•
•
Feedback Loop Design
Adaptive Synchronous Rectification Control with Dual Edge
Tracking
Closed Loop Soft−Start for Monotonic Rising Output
Wide Operating Frequency (39 kHz ~ 690 kHz)
Green Functions to Improve Light−Load Efficiency
♦ Symmetric PWM Control at Light−Load to Limit the Switching
Frequency while Reducing Switching Losses
♦ Disabling SR at Light−Load Condition
Protection Functions with Auto−Restart
♦ Over−Current Protection (OCP)
♦ Output Short Protection (OSP)
♦ NON Zero−Voltage Switching Prevention (NZS) by
Compensation Cutback (Frequency Shift)
♦ Power Limit by Compensation Cutback (Frequency Shift)
♦ Overload Protection (OLP)
Programmable Dead Times for Primary Side Switches and Secondary
Side Synchronous Rectifiers
VDD Under−Voltage Lockout (UVLO)
Wide Operating Temperature Range −40°C to +125°C
Automotive Qualified to AEC−Q100 Grade 1
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
© Semiconductor Components Industries, LLC, 2020
June, 2020 − Rev. 1
MARKING DIAGRAM
NCV4390
AWLYWWG
1
Features
•
SOIC−16
CASE 751B−05
1
NCV4390
A
L
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
5VB
1
16
GND
PWMS
2
15
VDD
FMIN
3
14
PROUT1
FB
4
13
PROUT2
COMP
5
12
SROUT1
SS
6
11
SROUT2
ICS
7
10
SR1DS
CS
8
9
RDT
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Publication Order Number:
NCV4390/D
NCV4390
Applications
• Automotive On Board Charger
• EV High Voltage DC/DC Converters
DG1
VIN
Q1
RG1
RGS1
PRDRV+
CIN
SR2
DG2
PRDRV−
Ns
RG2
SRDRV1
CR
RGS2
VO
SRDRV2
Np
Q2
COUT
Ns
CT
SR1
RCS2
RCS1
RSRDS1
C5VB
RPWMS
RICS
5VB
GND
PWMS
VDD
FMIN
RFMIN
FB
CCOMP
COMP
CSS
SS
CICS
RSRDS2
CVDD
PROUT1
PRDRV+
PROUT2
PRDRV−
SROUT1
SRDRV1
SROUT2
SRDRV2
ICS
RFB1
R
SR1DS
CS
RDT
CDT
RDT
Figure 1. Typical Application Schematic of NCV4390
Block Diagram
ICS_RST
+
3V
+
−
HALF_CYCLE
VCT
1.5V
VSAW
+
−
FMIN
−
3
COMP_I
3/4
1V
Digital
PFM/PWM
Block
PWM_CTRL
PWM
CT_RST
ICS
6
COMP
5
Dead Time
Setting
SR_SKIP
Compensation
Cutback signal
Generator
1.2V
2.4V
2
PROUT1
PROUT2
SR_SHRNK
OSP
Dual Edge Adaptive
Tracking SR Control Block
SR1_CND
−
PWM_CTRL
+
3.5V
−3.5V
PROUT2
3
RDT
12
SROUT1
11
SROUT2
10
SR1DS
15
VDD
1
5VB
16
GND
SR2_CND
+
−
PWMM
+
−
−
13
SR STOP
SR Conduction Detect
Block
8
PROUT1
PWMM
4
PWM Mode
Entry Level
Setting
14
SHUTDOWN
SKIP
RST
+
−
CS
Protection
Block
SR_SHRNK
UP1 UP4 DOWN
+
SS
OCP2
Current
Analyzer
RST
5V
Dead Time
Control
Block
CT_RST
SR_SKIP
Auto−Restart
Control
PWMS
CLK2
7
ICS_RST
FB
CLK1
NON ZVS
Detect
8.5V/10V
VDD_GOOD
+
OCP2
−
Figure 2. Internal Block Diagram of NCV4390
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2
BIAS
NCV4390
PIN DESCRIPTION
Pin Number
Pin Name
Description
1
5VB
2
PWMS
PWM mode entry level setting.
3
FMIN
Minimum frequency setting pin.
5 V REF
4
FB
5
COMP
Output voltage sensing for feedback control.
6
SS
Soft−start time programming pin.
7
ICS
Current information integration pin for current mode control.
8
CS
Current sensing for over current protection.
9
RDT
Output of error amplifier.
Dead time programming pin for the primary side switches and secondary side SR switches.
10
SR1DS
11
SROUT2
SR1 Drain−to−source voltage detection.
Gate drive output for the secondary side SR MOSFET 2.
12
SROUT1
Gate drive output for the secondary side SR MOSFET 1.
13
PROUT2
Gate drive output 2 for the primary side switch.
14
PROUT1
Gate drive output 1 for the primary side switch.
15
VDD
IC Supply voltage.
16
GND
Ground.
ORDERING AND SHIPPING INFORMATION
Ordering Code
Device Marking
Package
Shipping†
NCV4390DR2G
NCV4390
SOIC−16
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NCV4390
MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
VDD
VDD Pin Supply Voltage to GND
−0.3
20.0
V
V5VB
5VB Pin Voltage
−0.3
5.5
V
VPWMS
PWMS Pin Voltage
−0.3
5.0
V
VFMIN
FMIN Pin Voltage
−0.3
5.0
V
FB Pin Voltage
−0.3
5.0
V
COMP Pin Voltage
−0.3
5.0
V
VSS
SS Pin Voltage
−0.3
5.0
V
VICS
ICS Pin Voltage
−0.5
5.0
V
VCS
CS Pin Voltage
−5.0
5.0
V
VRDT
RDT Pin Voltage
−0.3
5.0
V
VSR1DS
SR1DS Pin Voltage
−0.3
5.0
V
VPROUT1
PROUT1 Pin Voltage
−0.3
VDD
V
VPROUT2
PROUT2 Pin Voltage
−0.3
VDD
V
VSROUT1
SROUT1 Pin Voltage
−0.3
VDD
V
VSROUT2
SROUT2 Pin Voltage
−0.3
VDD
V
TJ
Junction Temperature
−40
150
°C
TL
Lead Soldering Temperature (10 Seconds)
260
°C
150
°C
Human body Model,
ANSI / ESDA / JEDEC
JS−001−2012
2
kV
Charged Device Model,
JESD22−C101
1
kV
VFB
VCOMP
TSTG
Storage Temperature
ESD
Electrostatic Discharge
Capability
−65
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
All voltage values are with respect to the GND pin.
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
RθJA
Junction−to−Ambient Thermal Characteristics
115
°C/W
RECOMMENDED OPERATING CONDITIONS
Symbol
Min.
Max.
Unit
VDD
VDD Pin Supply Voltage to GND
0
18
V
V5VB
5VB Pin Voltage
0
5
V
VINS
Signal Input Voltage
0
5
V
−40
+125
°C
TJ
Parameter
Operating Junction Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Allowable operating ambient temperature can be limited by the power dissipation of NCV4390.
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NCV4390
ELECTRICAL CHARACTERISTICS (VDD = 12 V, C5VB = 33 nF and TJ = −40°C to 125°C unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
115
mA
SUPPLY VOLTAGE (VDD PIN)
Startup Supply Current
VDD = 9 V
80
Operating Current
VCOMP = 0.1 V, VFB = 3 V, VSS = 0 V
2.8
mA
IDD_DYM1
Dynamic Operating Current
fSW = 100 kHz; CL = 1 nF, with PR
Operation Only
10
mA
IDD_DYM2
Dynamic Operating Current
fSW = 100 kHz; CL = 1 nF, with PR &
SR Operation
13
mA
ISTARTUP
IDD
VDD.ON
VDD ON Voltage (VDD Rising)
VDD.OFF
VDD OFF Voltage
(VDD Falling)
VDD.HYS
UVLO Hysteresis
9
10
11
8.6
V
V
0.9
1.4
1.9
V
TJ = 25°C
4.99
5.05
5.11
V
−40°C < TJ < 125°C
4.90
5.05
5.20
V
TJ = 25°C
2.37
2.40
2.43
V
−40°C < TJ < 125°C
2.34
2.40
2.46
V
REFERENCE VOLTAGE
V5VB
5 V Reference
ERROR AMPLIFIER (COMP PIN)
VSS.CLMP
gm
Voltage Feedback Reference
Error Amplifier Gain
Transconductance
300
mmho
ICOMP1
Error Amplifier Maximum
Output Current (Sourcing)
VFB = 1.8 V, VCOMP = 2.5 V
67
90
115
mA
ICOMP2
Error Amplifier Maximum
Output Current (Sinking)
VFB = 3.0 V, VCOMP = 2.5 V
67
90
115
mA
VCOMP.CLMP1
Error Amplifier Output High
Clamping Voltage
VFB = 1.8 V
4.2
4.4
4.6
V
VCOMP.PWM
VCOMP Internal Clamping
Voltage for PWM Operation
RPWM = 130 k
1.26
1.41
1.56
V
RPWM = 82 k
1.4
1.6
1.8
V
PWMS Pin Voltage
RPWM = 82 k
1.9
2.0
2.1
V
1.15
1.25
1.35
V
VPWMS
VCOMP.SKP
VCOMP Threshold for Entering
Skip Cycle Operation
VCOMP.SKP.HYS
VCOMP Threshold Hysteresis
for Entering Skip Cycle
Operation
50
mV
DEAD TIME (DT PIN)
IDT
Dead−Time Programming
Current
VRDT = 1.2 V
140
150
160
mA
VTHDT1
First Threshold for Dead−Time
Detection
0.9
1.0
1.1
V
VTHDT2
Second Threshold for
Dead−Time Detection
2.8
3.0
3.2
V
VRDT.ON
VRDT ON Voltage
(VRDT Rising)
1.2
1.4
1.6
V
32
40
52
mA
3.45
3.60
3.75
V
8.2
10.5
12.8
mA
SOFT−START (SS PIN)
ISS.T
Total Soft−Start Current
(Including ISS.UP)
VOLP
Overload Protection Threshold
ISS.UP
Soft−Start Capacitor Charge
Current for Delayed Shutdown
VSS = 1 V
VSS = 3 V
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NCV4390
ELECTRICAL CHARACTERISTICS (VDD = 12 V, C5VB = 33 nF and TJ = −40°C to 125°C unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
8.2
10.5
12.8
mA
SOFT−START (SS PIN)
ISS.DN
Soft−Start Capacitor Discharge
Current
VSS = 3 V
VSS.MAX
SS Capacitor Maximum
Charging Voltage
4.5
4.7
4.9
V
VSS.INIT
SS Capacitor Initialization
Voltage
0.05
0.10
0.20
V
FEEDBACK (FB PIN)
VFB.OVP1
VFB Threshold for Entering
Skip Cycle Operation
VCOMP = 3 V
2.53
2.65
2.77
V
VFB.OVP2
VFB Threshold for Exiting Skip
Cycle Operation
VCOMP = 3 V
2.18
2.30
2.42
V
VERR.OSP
Error Voltage to Enable Output
Short Protection (OSP)
VSS = 2.4 V
1.0
1.2
1.4
V
FMIN Pin Voltage
RFIMN = 10 kW,
1.4
1.5
1.6
V
PROUT Switching Frequency
RMINF = 10 kW, VCS = 1 V
VCOMP = 4.0 V, VICS = 0 V
96
100
104
kHz
fOSC.min
Minimum PROUT Switching
Frequency (40 MHz/1024)
RMINF = 40 kW, VCS = 1 V
VCOMP = 4.0 V, VICS = 0 V
36
39
42
kHz
fOSC.max
Maximum PROUT Switching
Frequency (40 MHz/58)
RMINF = 2 kW, VCS = 1 V
VCOMP = 2.0 V, VICS = 0 V
635
690
735
kHz
D
PROUT Duty Cycle in PFM
Mode
RMINF = 20 kW, VCS = 1 V
VCOMP = 4.0 V
OSCILLATOR
VFMIN
fOSC
50
%
INTEGRATED CURRENT SENSING (ICS PIN)
VICS.CLMP
ICS Pin Signal Clamping Voltage
ICS = 400 mA
10
RDS−ON.ICS
ICS Pin Clamping MOSFET
RDS−ON
ICS = 1.5 mA
20
VTH1
SR_SHRNK Enable Threshold
VCOMP = 2.4 V
VTH1.HYS
SR_SHRNK Disable Hysteresis
VCOMP = 2.4 V
VTH2
SR_SKIP Disable Threshold
VCOMP = 2.4 V
0.10
0.15
0.20
V
VTH3
SR_SKIP Enable Threshold
VCOMP = 2.4 V
0.025
0.075
0.125
V
VOCL1
Over−Current Limit First
Threshold
VCOMP = 2.4 V
1.12
1.20
1.28
V
VOCL2
Over−Current Limit Second
Threshold
VCOMP = 2.4 V
1.34
1.45
1.56
V
VOCL1.BR
Over-Current Limit First
Threshold in Deep Below
Resonance Operation
VCOMP = 2.4 V
1.34
1.45
1.56
V
VOCL2.BR
Over−Current Limit Second
Threshold in Deep Below
Resonance Operation
VCOMP = 2.4 V
1.59
1.70
1.81
V
VOCP1
Over−Current Protection
Threshold
VCOMP = 2.4 V
1.77
1.90
2.03
V
VOCP1.BR
Over−Current Protection
Threshold
VCOMP = 2.4 V
2.02
2.15
2.28
V
TOCP1.DLY
Debounce Time for Over−Current
Protection 1
0.15
0.20
6
mV
W
0.25
50
150
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50
V
mV
ns
NCV4390
ELECTRICAL CHARACTERISTICS (VDD = 12 V, C5VB = 33 nF and TJ = −40°C to 125°C unless otherwise specified)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3.3
3.5
3.7
V
CURRENT SENSING (CS PIN)
VOCP2P
TOCP2.DLY
VOCP2N
VCS.NZVS
VCOMP.NZVS
Over−Current Protection
Threshold
Debounce Time for Over−Current
Protection 2
150
Over−Current Protection
Threshold
ns
−4.0
−3.5
−3.0
V
CS Signal Threshold for Non-ZVS
Detection
VCOMP = 3.5 V
0.24
0.30
0.36
V
COMP Threshold for Non-ZVS
Detection
VCS = 0.1 V
2.7
3.0
3.3
V
GATE DRIVE (PROUT1 AND PROUT2)
PROUT Sinking Current
VPROUT1 & VPROUT2 = 6 V
140
mA
ISOURCE
PROUT Sourcing Current
VPROUT1 & VPROUT2 = 6 V
150
mA
tPR.RISE
Rise Time
VDD = 12 V, CL = 1 nF, 10% to 90%
100
ns
tPR.FALL
Fall Time
VDD = 12 V, CL = 1 nF, 90% to 10%
85
ns
ISINK
SYNCHRONOUS RECTIFICATION (SR) CONTROL
TRC_SRCD
(Note 1)
Internal RC Time Constant SR
Conduction Detection
50
100
150
ns
VSRCD.OFFSET1
(Note 1)
Internal Comparator Offset Rising
Edge Detection
0.15
0.25
0.35
V
VSRCD.OFFSET2
(Note 1)
Internal Comparator Offset
Falling Edge Detection
0.10
0.20
0.30
V
VSRCD.LOW
SR Conduction Detect threshold
0.4
0.5
0.6
V
TDLY.CMP.SR
SR Conduction Detect
Comparator Delay
VFB.SR.ON
SR Enable FB Voltage
1.6
1.8
2.0
V
VFB.SR.OFF
SR Disable FB Voltage
1.0
1.2
1.4
V
65
ns
SR OUTPUT (SROUT1 AND SROUT2)
PROUT Sinking Current
VSROUT1 & VSROUT2 = 6 V
140
mA
PROUT Sourcing Current
VSROUT1 & VSROUT2 = 6 V
150
mA
tSR.RISE
Rise Time
VDD = 12 V, CL = 1 nF, 10% to 90%
100
ns
tSR.FALL
Fall Time
VDD =12 V, CL = 1 nF, 90% to 10%
85
ns
ISR.SINK
ISR.SOURCE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. These parameters, although guaranteed by design, are not production tested.
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7
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. V5VB vs. Temperature
Figure 4. IDT vs. Temperature
Figure 5. VFMIN vs. Temperature
Figure 6. fOSC vs. Temperature
Figure 7. fOSC.MIN vs. Temperature
Figure 8. fOSC.MAX vs. Temperature
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8
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. DUTY CYCLE vs. Temperature
Figure 10. VRDT.OFF vs. Temperature
Figure 11. VSS.CLMP vs. Temperature
Figure 12. ISTARTUP vs. Temperature
Figure 13. IDD vs. Temperature
Figure 14. IDD_DYM1 vs. Temperature
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9
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. IDD_DYM2 vs. Temperature
Figure 16. VDD.ON vs. Temperature
Figure 17. VDD.OFF vs. Temperature
Figure 18. VDD.HYS vs. Temperature
Figure 19. gm vs. Temperature
Figure 20. ICOMP1 vs. Temperature
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10
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. ICOMP2 vs. Temperature
Figure 22. VCOMP.CLMP1 vs. Temperature
Figure 23. VCOMP.PWM vs. Temperature
Figure 24. VCOMP.SKIP vs. Temperature
Figure 25. VCOMP.SKIP.HYS vs. Temperature
Figure 26. VRDT.ON vs. Temperature
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11
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 27. VTHDT1 vs. Temperature
Figure 28. VTHDT2 vs. Temperature
Figure 29. ISS.T vs. Temperature
Figure 30. VOLP vs. Temperature
Figure 31. ISS.UP vs. Temperature
Figure 32. VSS.MAX vs. Temperature
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12
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 33. ISS.DN vs. Temperature
Figure 34. VSS.INIT vs. Temperature
Figure 35. VPWMS vs. Temperature
Figure 36. VFB.OVP1 vs. Temperature
Figure 37. VFB.OVP1 vs. Temperature
Figure 38. VERR.OSP vs. Temperature
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NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 39. RDS−ON.ICS vs. Temperature
Figure 40. VTH1 vs. Temperature
Figure 41. VTH1 vs. Temperature
Figure 42. VTH3 vs. Temperature
Figure 43. VOCL1 vs. Temperature
Figure 44. VOCL2 vs. Temperature
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14
NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 45. VOCL1.BR vs. Temperature
Figure 46. VOCL2.BR vs. Temperature
Figure 47. VOCP1 vs. Temperature
Figure 48. VOCP1.BR vs. Temperature
Figure 49. VOCP2P vs. Temperature
Figure 50. VOCP2N vs. Temperature
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NCV4390
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 51. VCS.NZVS vs. Temperature
Figure 52. VCOMP.NZVS vs. Temperature
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NCV4390
APPLICATION INFORMATION
Operation Principle of Charge Current Control
current flowing out of the FMIN pin. The FMIN pin voltage
is regulated at 1.5 V.
The LLC resonant converter has been widely used for
many applications because it can regulate the output over
entire load variations with a relatively small variation of
switching frequency, and achieve Zero Voltage Switching
(ZVS) for the primary side switches and Zero Current
Switching (ZCS) for the secondary side rectifiers over the
entire operating range. In addition, the resonant inductance
can be integrated with the transformer into a single magnetic
component. Figure 53 shows the simplified schematic of the
LLC resonant converter where voltage mode control is
employed. Voltage mode control is typically used for the
LLC resonant converter where the error amplifier output
voltage directly controls the switching frequency. However,
the compensation network design of the LLC resonant
converter is relatively challenging since the frequency
response with voltage mode control includes four poles
where the location of the poles changes with input voltage
and load variations.
NCV4390 employs charge current mode control to
improve the dynamic response of the LLC resonant
converter. Figure 54 shows the simplified schematic of a
half−bridge LLC resonant converter using NCV4390,
where Lm is the magnetizing inductance, Lr is the resonant
inductor and Cr is the resonant capacitor. Typical key
waveforms of the LLC resonant converter for heavy load
and light load conditions are illustrated in Figure 55 and
Figure 56, respectively. It is assumed that the operation
frequency is same as the resonance frequency, as determined
by the resonance between Lr and Cr. Since the primary−side
switch current does not increase monotonically, the switch
current
itself
cannot
be
used
for
pulse−frequency−modulation (PFM) for the output voltage
regulation. Also, the peak value of the primary−side current
does not reflect the load condition properly because the large
circulating current (magnetizing current) is included in the
primary−side switch current. However, the integral of the
switch current (VICS) does increase monotonically and has
a peak value similar to that used for peak current mode
control, as shown in Figure 55 and Figure 56.
Thus, NCV4390 employs charge current control, which
compares the total charge of the switch current (integral of
switch current) to the control voltage to modulate the
switching frequency. Since the charge of the switch current
is proportional to the average input current over one
switching cycle, charge control provides a fast inner loop
and offers excellent transient response including inherent
line feed−forward. The PFM block has an internal timing
capacitor (CT) whose charging current is determined by the
Q1
VIN
VO
Cr
Q2
CO
Lr
L
VCO
VC
+
Vc
Driver
VO.REF
−
Figure 53. LLC Resonant Converter with Voltage
Mode Control
VIN
Q1
PROUT1
Cr
Lr
VO
Q2
PROUT2
Lm
Current
sensing
ICS
Integrated signal (VICS)
3/4
Reset
+
VSAW
VREF
−
VCT
+
− 3V
PROUT2
1.5V
CT
+
Digital
OSC
−
PROUT1
FMIN
VCOMP.I
VCOMP.I
VSAW
PWM
control
1V
PROUT1
PROUT2
PWMS
1V
U1
COMP
Cutback
2.4V
SS
VCOMP
COMP
FB
Figure 54. Schematic of LLC resonant Converter
Power Stage Schematic
There is an upper limit (3 V) for the timing capacitor
voltage, which determines the minimum switching
frequency for a given resistor connected to the FMIN pin.
The sawtooth waveform (VSAW) is generated by adding the
integral of the Q1 switch current (VICS) and the timing
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17
NCV4390
To improve the light load efficiency, NCV4390 employs
hybrid control where the PFM is switched to pulse width
modulation (PWM) mode at light load as illustrated in
Figure 57. If want to not uses PWM mode in light load
condition, adjust PWM entry level using external PWM
resistor for under skip threshold level. The figure 58 show
that the switching frequency and duty ratio characteristics in
disable PWM mode. The typical waveforms for PFM mode
and PWM mode are shown in Figure 59 and Figure 60,
respectively. When the error amplifier voltage (VCOMP) is
below the PWM mode threshold, the internal COMP signal
is clamped at the threshold level and the PFM operation
switches to PWM mode.
capacitor voltage (VCT) of the oscillator. The sawtooth
waveform (Vsaw) is then compared with the compensation
voltage (VCOMP) to determine the switching frequency.
Ip
Im
ID
IDS1
Switching
frequency
Skip cycle
Duty cycle
PFM Mode
PWM Mode
D=50%
No
switching
VICS = k ∫ IDS1dt
VCOMP
1.25V 1.3V
Figure 55. Typical Waveforms of the LLC
Resonant Converter for Heavy Load Condition
VCOMP.PWM
4.4V
Figure 57. Mode Change with COMP Voltage
Duty cycle
Switching
frequency
Skip cycle
Ip
PFM Mode
D=50%
Im
No
switching
ID
VCOMP.PWM = Less than 1.25 V
( Disable PWM mode )
1.25V 1.3V
VCOMP
4.4V
Figure 58. Disable PWM mode with COMP Voltage
IDS1
Ip
Im
VICS
VICS = k ∫ IDS1dt
VCT
Figure 56. Typical Waveforms of LLC Resonant
Converter for Light−Load Condition
VCOMP
3/4 *VICS +VCT
Hybrid Control (PWM + PFM)
Counter of
The conventional PFM control method modulates only
the switching frequency with a fixed duty cycle of 50%,
which typically results in relatively poor light load
efficiency due to the large circulating primary side current.
PROUT1
PROUT2
Figure 59. Key Waveforms of PFM Operation
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18
NCV4390
Ip
VCTX
Q1
VICS
VICS
PROUT1
VCT
VCOMP.PWM −VCOMP
PROUT1
Current
transformer
+
VCOMP
VTH.PWM
3/4
VSENSE
VCOMP.PWM −VCOMP
CICS
ICS
VICS
+
VICS
−
−
*VICS +VCT
PROUT1
RICS
PROUT1
Q2
RCS2
Counter of
digital OSC
CS
PROUT2
PROUT1 PROUT2
Figure 60. Key Waveforms of PWM Operation
Main
transformer
Primary
winding
VCS
RCS1
Figure 61. Current Sensing of NCV4390
In PWM mode, the switching frequency is fixed by the
clamped internal COMP voltage (VCOMPI) and the duty
cycle is determined by the difference between COMP
voltage and the PWM mode threshold voltage. Thus, the
duty cycle decreases as VCOMP drops below the PWM
mode threshold, which limits the switching frequency at
light load condition as illustrated in Figure 57. The PWM
mode threshold can be programmed between 1.9 V and
under skip threshold using a resistor on the PWMS pin.
Disable PWM mode when the PWM mode threshold is set
below 1.25 V.
1
0.8
∫ VCTXdt
0.6
VICS
0.4
0.2
0
4
3
2
1
VCTX
0
−1
−2
Current Sensing
−3
NCV4390 senses instantaneous switch current and the
integral of the switch current as illustrated in Figure 61.
Since NCV4390 is located in the secondary side, it is typical
to use a current transformer for sensing the primary side
current. While the PROUT1 is LOW, the ICS pin is clamped
at 0 V with an internal reset MOSFET. Conversely, while
PROUT1 is high, the ICS pin is not clamped and the integral
capacitor (CICS) is charged and discharged by the voltage
difference between the sensing resistor voltage (VSENSE)
and the ICS pin voltage. During normal operation, the
voltage of the ICS pin is below 1.2 V since the power limit
threshold is 1.2 V. The current sensing resistor and current
transformer turns ratio should be designed such that the
voltage across the current sensing resistor (VSENSE) is
greater than 4 V at the full load condition. Therefore the
current charging and discharging CICS should be almost
proportional to the voltage across the current sensing
resistor (VSENSE). Figure 62 compares the VICS signal and
the ideal integral signal when the amplitude of VSENSE is
4 V. As can be seen, there is about 10% error in the VICS
signal compared to the ideal integral signal, which is
acceptable for most designs. If more accuracy of the VICS
is required, the amplitude of VSENSE should be increased.
−4
Figure 62. Disable PWM mode with COMP Voltage
Since the peak value of the integral of the current sensing
voltage (VICS) is proportional to the average input current
of the LLC resonant converter, it is used for four main
functions, listed and shown in Figure 63.
1. SR Gate Shrink: To guarantee stable SR operation
during light load operation, the SR dead time (both
of turn−on and turn−off transitions) is increased
resulting in SR gate shrink when VICS peak value
drops below VTH1 (0.2 V). The SR dead time is
reduced to the programmed value when VICS peak
value rises above 0.25 V
2. SR Disable and Enable: During very light−load
condition, the SR is disabled when the VICS peak
value is smaller than VTH3 (0.075 V). When the
VICS peak value increases above VTH2 (0.15 V),
the SR is enabled
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NCV4390
3. Over−Current Limit: The VICS peak value is also
used for input current limit. As can be seen in
Figure 64, there exist two different current limits
(fast and slow). When the VICS peak value
increases above the slow current limit level
(VOCL1) due to a mild overload condition, the
internal feedback compensation voltage is slowly
reduced to limit the input power. This continues
until the VICS peak value drops below VOCL1.
During a more severe over load condition, the
VICS peak value crosses the fast current limit
threshold (VOCL2) and the internal feedback
compensation voltage is quickly reduced to limit
the input power as shown in Figure 64 (b). This
continues until the VICS peak value drops below
VOCL2. The current limit threshold on the VICS
peak value also changes as the output voltage
sensing signal (VFB) decreases such that output
current is limited during overload condition as
shown in Figure65. In addition, these limit
thresholds change to higher values (VOCL1.BR and
VOCL2.BR) when the converter operates in deep
below resonance operation for a longer holdup
time (refer to holdup time boost function)
4. Over−Current Protection (OCP1): When the VICS
peak value is larger than VOCP1 (1.9 V), the over
current protection is triggered. 150 ns debounce
time is added for over−current protection. These
OCP threshold can be changed to a higher value
(VOCP1.BR) when the converter operates in deep
below resonance operation for a longer holdup
time (refer to holdup time boost function)
IPR
PROUT1
VOCP1
VOCL2
VOCL1
(a) Mild Overload Condition
IPR
PROUT1
VOCP1
VOCL2
VOCL1
(b) Severe Overload Condition
Figure 64. Current Limit of the ICS Pin by
Frequency Shift (Compensation Cutback)
1.45V
VOCL2
1.2V
VOCL1
1.0V
0.75V
0.5V
Output Power
2.0 V 2.4 V
Fast Current limit
Figure 65. Current Limit Threshold Modulation as
a Function of Feedback Voltage
Slow Current limit
SR Shrink
SR Enable
SR Disable
VICS PK
50mV
0.075V 0.15V
VFB
0.2V
1.2V
1.45V
VICS
Figure 63. Functions Related to VICS Peak Voltage
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NCV4390
The instantaneous switch current sensing on the CS pin is
also used for the following functions.
1. Non−ZVS Prevention: When the compensation
voltage (VCOMP) is higher than 3 V and VCS peak
value is smaller than 0.3 V at PROUT1 falling
edge, non−ZVS condition is detected, which
decreases the internal compensation signal to
increase the switching frequency
2. Over−Current Protection (OCP2): When VCS is
higher than 3.5 V or lower than −3.5 V,
over−current protection (OCP2) is triggered. The
instantaneous primary side current is also sensed
on CS pin. Since the OCP2 thresholds on the CS
pin are 3.5 V and −3.5 V as shown in Figure 66,
the CS signal is typically obtained from VSENSE
by using a voltage divider as illustrated in
Figure 61. 150 ns debounce time is also added for
OCP2
COMP
Compensation
Voltage
+
3V
−
0.3V
+
D Q
−
QN
PROUT1
− 3.5V
3.5V
ICS
Compensation
Cutback
OCP
−
+
1.9V
0.25V /
0.20V
−
+
−
PROUT1
0.15V /
+
0.075V
−
PROUT1
+
OCL1
−
PROUT1
OCP1
D Q
OCL2
−
PROUT1
SR Shrink
QN
D Q
SR Skip
QN
D Q
QN
+
Figure 67 shows utilization of current sensing by using
ICS and CS signals.
PFM block
+
−
OCP2
+
CS
NON ZVS
detect
Compensation
Cutback
D Q
QN
Figure 67. Utilization of Current Sensing Signal
VOCP2P
(3.5)V
VCS
VOCP2N
(−3.5V)
PROUT1
PROUT2
VOCP2P
(3.5)V
VCS
VOCP2N
(−3.5V)
PROUT1
PROUT2
Figure 66. Over−Current Protection of the CS Pin
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21
NCV4390
Soft−Start and Output Voltage Regulation
VSS
Figure 68 shows the simplified circuit block for feedback
control and closed loop soft−start. During normal, steady
state operation, the Soft−Start (SS) pin is connected to the
non−inverting input of the error amplifier which is clamped
at 2.4 V. The feedback loop operates such that the sensed
output voltage is same as the SS pin voltage. During startup,
an internal current source (ISS.T) charges the SS capacitor
and SS pin voltage progressively increases. Therefore, the
output voltage also rises monotonically as a result of closed
loop SS control.
The SS capacitor is also used for the shutdown delay time
during overload protection (OLP). Figure 69 shows the OLP
waveform. During normal operation, the SS capacitor
voltage is clamped at 2.4 V. When the output is over−loaded,
VCOMP is saturated to HIGH and the SS capacitor is
decoupled from the clamping circuit through the SS control
block. ISS is blocked by DBLCK and the SS capacitor is
slowly charged up by the current source ISS.UP. When the SS
capacitor voltage reaches 3.6 V, OLP is triggered. The time
required for the soft−start capacitor to be charged from 2.4 V
to 3.6 V determines the shutdown delay time for overload
protection.
VIN
4.8V
3.6V
2.4V
time
Ip
time
Figure 69. Delayed Shutdown with Soft−Start
Auto−Restart after Protection
All protections of NCV4390 are non−latching,
auto−restart, where the delayed restart is implemented by
charging and discharging the SS capacitor as illustrated in
Figure 70. During normal operation, the SS capacitor
voltage is clamped at 2.4 V. Once any protection is triggered,
the SS clamping circuit is disabled. The SS capacitor is then
charged up to 4.7 V by an internal current source (ISS.UP).
The SS capacitor is then discharged down to 0.1 V by
another internal current (ISS.DN). After charging and
discharging the SS capacitor three more times, auto recovery
is enabled.
Q1
Cr
Lr
VSS
Charged by I SS.UP
Discharged by I SS.DN
1/8 time scale
4.7V
Q2
3.6V
VO
2.4V
Charged by I SS.T
Lm
0.1V
Shutdown
delay
time
Ip
time
PROUT2
PROUT1
ICS
PFM
1.2V
SS
Control
ISS
DN
Disable SS
clamp
30 mA
2.4V
COMP
UP
VCOMP
10 mA
SS
time
Figure 70. Auto Re−Start after Protection is
Triggered
ISS.DN
DBLCK
time
ISS.UP
10 mA
FB
Figure 68. Schematic of Closed Loop Soft−Start
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22
NCV4390
5VB
Output Short Protection
To minimize the power dissipation through the power
stage during a severe fault condition, NCV4390 offers
Output Short Protection (OSP). When the output is heavily
over−loaded or short circuited, the feedback voltage (output
voltage sensing) does not follow the reference voltage of the
error amplifier (2.4 V). When the difference between the
reference voltage of the error amplifier and the FB voltage
is larger than 1.2 V, the OSP is triggered without waiting
until the OLP is triggered as shown in Figure 71.
RDT
VRDT
IDT
C DT
S1
Figure 72. Internal Current Source for of RDT Pin
Dead−Time Setting
With a single pin (RDT pin), the dead times between the
primary side gate drive signals (PROUT1 and PROUT2)
and secondary side SR gate drive signal (SROUT1 and
SROUT2) are programmed using a switched current source
as shown in Figure 72 and Figure 73. Once the 5 V bias is
enabled, the RDT pin voltage is pulled up. When the RDT
pin voltage reaches 1.4 V, the voltage across CDT is then
discharged down to 1 V by an internal current source IDT.
IDT is then disabled and the RDT pin voltage is charged up
by the RDT resistor. As shown in Figure 73, 1/64 of the time
required (TSET1) for RDT pin voltage to rise from 1 V to 3 V
determines the dead time between the secondary side SR
gate drive signals.
The switched current source IDT is then enabled and the
RDT pin voltage is discharged. 1/32 of the time required
(TSET2) for the RDT pin voltage to drop from 3 V to 1 V
determines the dead time between the primary side gate
drive signals. After the RDT voltage drops to 1 V, the current
source IDT is disabled a second time, allowing the RDT
voltage to be charged up to 5 V.
Table 1 shows the dead times for SROUT and PROUT
programmed with recommended RDT and CDT component
values. Since the time is measured by an internal 40 MHz
clock signal, the resolution of the dead time setting is 25 ns.
5V
4V
3V
2V
1V
TSET1
3.6V
The minimum and maximum dead times are therefore
limited at 75 ns and 375 ns respectively. To assure stable SR
operation while taking circuit parameter tolerance into
account, 75 ns dead time is not recommended especially for
the SR dead time.
When NCV4390 operates in PWM mode at light−load
condition, the dead time is doubled to reduce the switching
loss.
VSS
1.2V
VFB
Ip
time
VICS
1.2V
0.0V
TSET2
Figure 73. Multi−function Operation of RDT Pin
4.8V
2.4V
TSET1 / 64= SROUT Dead Time
TSET2 / 32 =PROUT Dead Time
time
Figure 71. Output Short Protection
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NCV4390
Table 1. DEAD TIME SETTING FOR PROUT AND SROUT
CDT = 180 pF
CDT = 220 pF
CDT = 270pF
CDT = 330 pF
CDT = 390 pF
CDT = 470 pF
CDT = 560 pF
RDT
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
SROUT
DT (ns)
PROUT
DT (ns)
28 k
75
375
75
375
75
375
100
375
125
375
150
375
175
375
30 k
75
250
75
325
100
375
100
375
125
375
150
375
175
375
33 k
75
200
75
250
100
300
125
375
150
375
175
375
200
375
36 k
75
175
75
200
100
250
125
325
150
375
175
375
225
375
40 k
75
150
100
175
125
225
150
275
175
325
200
375
250
375
44 k
75
125
100
150
125
200
150
250
175
300
225
350
275
375
48 k
100
125
125
150
150
175
175
225
200
275
250
325
300
375
53 k
100
100
125
125
150
175
200
200
225
250
275
300
325
375
58 k
125
100
150
125
175
150
200
200
250
250
300
300
350
350
64 k
125
100
150
125
175
150
225
200
275
225
325
275
375
325
71 k
150
100
175
125
200
150
250
175
300
225
350
250
375
325
78 k
150
100
175
100
225
150
275
175
325
200
375
250
375
300
86 k
175
75
200
100
250
125
300
175
375
200
375
250
375
300
94 k
175
75
225
100
275
125
325
175
375
200
375
225
375
275
104 k
200
75
250
100
300
125
375
150
375
200
375
225
375
275
114 k
225
75
275
100
325
125
375
150
375
175
375
225
375
275
126 k
250
75
300
100
375
125
375
150
375
175
375
225
375
275
138 k
275
75
325
100
375
125
375
150
375
175
375
225
375
250
152 k
300
75
350
100
375
125
375
150
375
175
375
225
375
250
Minimum Frequency Setting
(40 MHz/1024 = 39 kHz). Therefore, the maximum
allowable value for RFMIN is 25.5 KW.
The minimum switching frequency is limited by
comparing the timing capacitor voltage (VCT) with an
internal 3 V reference as shown in Figure 74. Since the rising
slope of the timing capacitor voltage is determined by the
resistor (RFMIN) connected to FMIN pin, the minimum
switching frequency is given as:
f SW .MIN + 100 kHz
10 kW
R FMIN
PWM Mode Entry Level Setting
When the COMP voltage drops below VCOMP.PWM as a
result of decreasing load, the internal COMP signal is
clamped at the threshold level and PFM operation switches
to PWM Mode. The PWM entry level threshold is
programmed using a external resistor on the PWMS pin as
shown in Figure 75. Once NCV4390 enters into PWM
mode, the SR gate drives are disabled. If want to uses
specially disable PWM mode, open PWMS pin or connect
to 1 MW.
(eq. 1)
The minimum programmable switching frequency is
limited by the digital counter running on an internal 40 MHz
clock. Since a 10 bit counter is used, the minimum switching
frequency given by the digital oscillator is 39 kHz
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24
NCV4390
Skip Cycle Operation
Ip
As illustrated in Figure 76, when the COMP voltage drops
below VCOMP.SKIP (1.25 V) as a result of decreasing load,
skip cycle operation is employed to reduce switching losses.
As the COMP voltage rises above 1.3 V, the switching
operation is resumed. When the FB voltage rises above
VFB.OVP1 (2.65 V), the skip cycle operation is also enabled
to limit the output voltage rising quickly. As the FB voltage
drops below VFB.OVP2 (2.3 V), the switching operation is
resumed.
VCOMP
VCOMP.SKIP
Figure 76. Skip Cycle Operation
VCOMP
VCOMP
VSAW
NCV4390 uses a dual edge tracking adaptive gate drive
method that anticipates the SR current zero crossing instant
with respect to two different time references. Figure 77 and
Figure 78 show the operational waveforms of the dual edge
tracking adaptive SR drive method operating below and
above resonance. To simplify the explanation, the SR dead
time is assumed to be zero. The first tracking circuit
measures SR conduction time (TSR_CNDCTN) and uses
this information to generate the first adaptive drive signal
(VPRD_DRV1) for the next switching cycle whose duration
is the same as the SR conduction time of previous switching
cycle. The second tracking circuit measures the turn−off
extension time which is defined as time duration from the
falling edge of the primary side drive to the corresponding
SR turn−off instant (TEXT). This information is then used
to generate the second adaptive drive signal (VPRD_DRV2)
for the next switching cycle. When the turn−off of the
primary side drive signal is after the turn−off of the
corresponding SR for below resonance operation, the
second adaptive SR drive signal is the same as the
corresponding primary side gate drive signal. However,
when the turn−off of the primary side drive signal is before
the turn−off instant of the corresponding SR for above
resonance operation, the second adaptive SR drive signal is
generated by extending the corresponding primary side gate
drive signal by TEXT of the previous switching cycle.
Since the turn off instant of the second adaptive gate drive
signal is extended by TEXT with respect to the falling edge
of the primary side gate drive signal, the duration of this
signal consequentially changes with switching frequency.
By combining these two signals VPRD_DRV1 and
VPRD_DRV2 with an AND gate, the optimal adaptive gate
drive signal is obtained.
The SR conduction times for SR1 and SR2 for each
switching cycle are measured using a single pin (SR1DS
pin). The SR1DS voltage and its delayed signal, resulting
1V
3V
3V
VCT
1V
VCT
1V
PROUT1
PROUT1
PROUT1
PROUT1
PROUT2
PROUT2
(a) PFM by COM voltage
(b) minimum Frequency limit
ICS
Integrated signal (VICS)
Reset
+
VSAW
VREF
−
+
− 3V
PROUT2
1.5V
CT
+
Digital
OSC
VCT
−
PROUT1
Min Freq Comparator
RFMIN
VCOMP.I
VCOMP.I
VSAW
PWM
control
1V
PROUT1
PROUT2
PWMS
50mV
U1
COMP
Cutback
FMIN
1V
2.4V
SS
VCOMP
COMP
FB
Figure 74. Minimum Switching Frequency Setting
Figure 75. PWM Mode Entry Level Setting
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NCV4390
from a 100 ns RC time constant, are compared as shown in
Figure 79. When the SR is conducting, the SR1DS voltage
is clamped to either ground or the high voltage rail (2 times
the output voltage) as illustrated in Figure 80. Whereas,
SR1DS voltage changes fast when there is a switching
transition. When both of the SR MOSFETs are turned off,
the SR1DS voltage oscillates. When the SR1DS voltage
changes faster than 0.25 V/100 ns on the rising edge and
0.2 V/100 ns on the falling edge the switching transition of
the SR conduction state is detected. Based on the detected
switching transition, NCV4390 predicts the SR current
zero−crossing instant for the next switching cycle. The
100 ns detection delay caused by the RC time constant is
compensated in the internal timing detection circuit for a
correct gate drive for SR.
IDS.PRI
DV
ISR2
DV
VRC VSR1DS
SR2
100ns
0.5V
SR1_OFF
SR2_OFF
SR2_OFF
ISR1
SR1
0.5V
+
−
+
SR1_OFF
−
RDS2
RDS1
CDS
0.25V
VSR1DS
SR1DS
VRC
RC
=100ns
S
Q
R
Q
+
SR2_OFF
−
0.2V
Figure 79. SR Conduction Detection with Single
Pin (SR1DS Pin)
ISR
TSR_CNDCTN(n+1)
TSR_CNDCTN (n)
Figure 80 and Figure 81 show the typical waveforms of
SR1DS pin voltage together with other key waveforms.
Since the voltage rating of SR1DS pin is 5 V, the voltage
divider should be properly designed such that no
over−voltage is applied to this pin. Additional bypass
capacitor (CDS) can be connected to SR1DS pin to improve
noise immunity. However, the equivalent time constant
generated from the bypass capacitor and voltage divider
resistors should be smaller than the internal RC time
constant (100 ns) of the detection circuit for proper SR
current zero crossing detection.
VPROUT
VPROUT
TSR_CNDCTN* (n−1)
100ns
IDS.PRI
ISR
SR2_OFF becomes HIGH
if DV>0.2V
SR1_OFF becomes HIGH
if DV>0.25V
TEXT(n)
VPRD1(n)
TSR_CNDCTN* (n)
TEXT(n+1)
VPRD1(n+1)
TEXT* (n)
VPRD2 (n)
VPRD2 (n+1)
Figure 77. Operation of Dual Edge Tracking
Adaptive SR Control (below Resonance)
IDS.PRI
IDS.PRI
VSR1.DS
5V
ISR
ISR
TSR_CNDCTN(n)
TSR_CNDCTN(n+1)
TEXT(n)
VPRD1 (n)
2V
1V
VPROUT
VPROUT
TSR_CNDCTN* (n−1)
4V
3V
ISR1
TEXT(n+1)
TSR_CNDCTN* (n)
VPRD1 (n+1)
ISR2
TEXT* (n)
VPRD2 (n)
VPRD2
Ip
Figure 78. Operation of Dual Edge Tracking
Adaptive SR Control (above Resonance)
Figure 80. SR Conduction Detection Waveform at
below Resonance Operation
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26
NCV4390
resonance operation during the holdup time as shown in
Figure 82. This holdup time boost operation is enabled when
the SR conduction time is smaller than 94% of the half
switching cycle for longer than 1.6 ms. The current limit
level on ICS pin is recovered to normal value when the SR
conduction time is larger than 98% of the half switching
cycle for longer than 3.2 ms.
VSR1DS
5V
4V
3V
2V
1V
ISR1
I
1.7V
1.45V
1.2V
VOCL2
VOCL1
Ip
Ipr
Figure 81. SR Conduction Detection Waveform at
above Resonance Operation
Holdup Time Boost Function
The holdup time of an off−line supply is defined as the
time required for the output voltage to remain within
regulation after the AC input voltage is removed. Since the
input bulk capacitor voltage drops during the holdup time,
more current is taken from the bulk capacitor to deliver the
same power to the load. With a fixed power limit level of
power supply designed for nominal input voltage, the
holdup time tends to be limited due to the increased input
current of the power supply.
NCV4390 has a holdup time boost function which
increases the current limit threshold on the ICS pin voltage
when the LLC resonant converter operates in deep below
SR c onduc tion time
Half switc hing period
< 94%
SR c onduc tion time
Half switc hing period
Figure 82. Holdup Time Boost Function Operation
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27
NCV4390
QUICK SETUP GUIDELINE for CURRENT SENSING and SOFT−START
Assuming the switching frequency is the same as the
resonance frequency, the peak voltage of the secondary side
voltage of current transformer (VSENSE) is given as:
V SENSE
PK
NS
NP
p
2
+ IO
1
n CT
V ICS
PK
NS
NP
p
2
+ IO
1
n CT
+ IO
(R CS1 ) R CS2)
R CS1 t 3.5 V
T SS +
C SS
[example] IO = 21 A, NP = 35, NS = 2, nCT = 50,
RCS1 = 30 W, RCS2 = 70 W ³ VCSPK = 1.131 V in nominal
load condition.
The resistor and capacitor on the ICS pin should be
selected such that the current limit is not triggered during
normal operation.
VSENSE
NS
1
nCT
NP
R CS1 ) R CS2
1
C ICS
R ICS
1
f
t 1.2 V
2 SW
[example] Io = 20 A, NP = 35, NS = 2, nCT = 50,
RCS1 = 30 W, RCS2 = 70 W, RICS = 10 kW, CICS = 1 nF,
fS = 100 kHz.
³ VICSPK = 1.14 V in nominal load condition (actual
VICSPK is lower by about 10% as shown in Figure 62 due to
a quasi integral effect).
Assuming the actual VICSPK (VICSPKA) is 1 V, the
soft−start capacitor should be selected such that the overload
protection is not triggered during startup with full load
condition.
[example] IO = 20 A, NP = 35, NS = 2, nCT = 50,
RCS1 + RCS2 = 100 W ³ VSENSEPK = 3.59 V in nominal
load condition.
The voltage divider on the CS pin should be selected such
that OCP is not triggered during normal operation.
V CS
PK
2.4 V
I SS
+ 40.8 ms u
C OUT
VO
1.2*VICS
V ICS
+ 22.5 ms
PK
IO
PK
VICS
Q1
PROUT1
PROUT1
PROUT2
PROUT1
PROUT1
ICS
+
+
VSENSE
CICS
−
+
VICS
−
Digital
OSC
1:nCT
Q2
CS
VCS
VCOMP.I
RCS1
NP
PROUT2
NS
NS
FMIN
1V
U1
COMP
Cutback
−
VO
RFMIN
VCOMP.I
−
OCP
1.5V
CT
3V
PWM
control
−3.5V +
Main
transformer
VREF
VCT
+
+
3.5V
VSAW
−
−
RCS2
Primary
side
winding
ICS
analyzer
Integrated signal (VICS)
+
RICS
−
Current
transformer
2.4V
VCOMP
PWMS
COUT
COMP
Secondary Side winding
Figure 83. Basic Application Circuit for Current Sensing and Soft−Start
www.onsemi.com
28
FB
SS
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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