NCV48220D50R2G

NCV48220 LDO Regulator - Very Low Quiescent Current, Charge Pump Boost Converter 150 mA The NCV48220 is very low quiescent current 150 mA LDO regulator with integrated battery voltage charge pump boost converter for automotive applications requiring full functionality during battery voltage drop events (e.g. cranking). The NCV48220 require very low number of external components. Very low quiescent current as low as 35 mA typical for NCV48220 makes it suitable for applications permanently connected to battery requiring very low quiescent current. The Enable function can be used for further decrease of quiescent current down to 1 mA. The NCV48220 contains protection functions as current limit, thermal shutdown and reverse bias current protection. Features • • • • • • • • • Output Voltage: 5 V LDO Output Current: up to 150 mA Very Wide Input Voltage Operation Range: from 3 V to 40 V Very Low Quiescent Current: typ 35 mA Enable Function (1.0 mA max quiescent current when disabled) Microprocessor Compatible Control Functions: ♦ Reset Output AEC−Q100 Grade 1 Qualified and PPAP Capable Protection Features: ♦ Current Limitation ♦ Thermal Shutdown ♦ Reverse Bias Output Current This is a Pb−Free Device www.onsemi.com MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 8 1 A L Y W G V4822050 ALYWG G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Typical Applications • Stop−Start Applications • Instruments and Clusters • Infotainment © Semiconductor Components Industries, LLC, 2016 September, 2019 − Rev. 1 1 Publication Order Number: NCV48220/D NCV48220 CFLY C+ V BAT C− V in V out Vout Cin VDD Cout V CP C CP Microprocessor NCV48220 OFF ON EN I/O RO GND Figure 1. Application Schematic C+ C− VCP LDO Vin Charge Pump Power Switches Vref Vout R RO RO Charge Pump Drivers and Logic Rin1 Battery Voltage Monitor Rin2 Vref EN with Overcurrent and Overtemperature Protections and Reset Circuitry Enable Vref Vref Figure 2. Simplified Block Diagram www.onsemi.com 2 GND NCV48220 VCP 1 8 Vout C+ RO C− EN GND Vin SOIC−8 Figure 3. Pin Connections (Top Views) Table 1. PIN FUNCTION DESCRIPTION Pin No. SOIC−8 Pin Name 1 VCP Charge Pump Output Voltage (Input Voltage of LDO). 2 C+ Flying Capacitor Positive Connection. 3 C− Flying Capacitor Negative Connection. 4 Vin Charge Pump Input Voltage. 5 GND 6 EN Enable Input; low level disables the IC. 7 RO Reset Output. 30 kW internal Pull−up resistor connected between RO and Vout. RO goes Low when Vout is out of regulation. See ELECTRICAL CHARACTERISTICS table for delay time specifications. 8 Vout Regulated Output Voltage of LDO. Description Power Supply Ground. www.onsemi.com 3 NCV48220 MAXIMUM RATINGS Symbol Min Max Unit Charge Pump Input Voltage DC (Note 1) Rating Vin −0.3 40 V Charge Pump Input Voltage (Note 2) Load Dump − Suppressed US − 45 V Charge Pump Output Voltage VCP −0.3 16 V Positive Flying Capacitor Voltage VC+ −0.3 16 V Negative Flying Capacitor Voltage VC− −0.3 7 V Regulated Output Voltage Vout −0.3 7 V Enable Input Voltage DC DC Transient, t < 100 ms VEN −0.3 − 40 45 Reset Output Voltage VRO −0.3 7 V TJ(max) − 150 °C TSTG −55 150 °C Maximum Junction Temperature Storage Temperature Range V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in production. Passed Class A according to ISO16750−1. ESD CAPABILITY (Note 3) Rating ESD Capability, Human Body Model Symbol Min Max Unit ESDHBM −2 2 kV 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes 1 V Integrated Reset Output Pull Up Resistor www.onsemi.com 5 % of Vout NCV48220 ELECTRICAL CHARACTERISTICS (Vin = 13.5 V, VEN = 3 V, ICP = 0 mA, CFLY = 10 mF with ESR ≈ 10 mW, CCP = 10 mF for typical values TJ = 25°C; for min/max values −40°C ≤ TJ ≤ 150°C, unless otherwise noted.) (Note 7) Parameter Test Conditions Symbol Min Typ Max Unit tRD − 102.4 0 128 − 153.6 ms tRR 16 25 38 ms Thermal Shutdown Temperature (Note 10) TSD 150 175 195 °C Thermal Shutdown Hysteresis (Note 10) TSH − 10 − °C RESET OUTPUT Reset Delay Time (Note 9) Min Available Time Max Available Time Reset Reaction Time THERMAL SHUTDOWN Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 8. Measured when output voltage falls 100 mV below the regulated voltage at VCP = 13.5 V. 9. Reset Delay Times can be chosen from list: 0, 2, 4, 8, 16, 32, 64, 128 ms (Reset Delay Time 0 ms represents Power Good function) and these delay times are factory preset. 10. Values based on design and/or characterization. www.onsemi.com 6 NCV48220 TYPICAL CHARACTERISTICS 350 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 70 60 50 40 30 20 Vin = 13.5 V Iout = 100 mA 10 0 −40 −20 20 0 40 60 80 100 120 140 50 0 5 10 15 20 25 30 5.10 50 40 30 20 Vin = 13.5 V TJ = 25°C 10 0 40 35 Figure 5. Quiescent Current vs. Input Voltage Vout, OUTPUT VOLTAGE (V) Iq, QUIESCENT CURRENT (mA) 100 Figure 4. Quiescent Current vs. Junction Temperature 20 40 60 80 100 120 140 Vin = 13.5 V 5.05 5.00 4.95 4.90 −40 −20 160 0 20 40 60 80 100 120 140 160 Iout, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Quiescent Current vs. Output Current Figure 7. Output Voltage vs. Junction Temperature 300 VDO, DROPOUT VOLTAGE (mV) 6 Vout, OUTPUT VOLTAGE (V) 150 Vin, INPUT VOLTAGE (V) 60 5 4 3 2 TJ = 25°C Iout = 75 mA 1 0 200 TJ, JUNCTION TEMPERATURE (°C) 70 0 250 0 160 TJ = 25°C Iout = 100 mA CP inactive 300 Vin increasing at Power Up (from 0 V) 0 2 4 6 8 10 12 200 150 TJ = 25°C 100 50 0 14 TJ = 125°C 250 0 30 60 90 120 150 180 Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 8. Output Voltage vs. Input Voltage Figure 9. Dropout Voltage vs. Output Current www.onsemi.com 7 NCV48220 TYPICAL CHARACTERISTICS 400 ILIM, OUTPUT CURRENT LIMIT (mA) 250 200 150 100 50 0 −40 −20 Iout = 150 mA 20 0 40 60 80 300 TJ = 125°C 250 200 150 100 50 0 100 120 140 160 Vout = 0 V 0 2 4 12 14 16 Figure 11. Output Current Limit vs. Input Voltage 100 Unstable Region 300 10 250 Stable Region ESR (W) 200 150 1 100 0 −40 −20 0.1 Vin = 13.5 V Vout = 4.8 V 50 20 0 40 60 80 Vin = 13.5 V Cout = 3.3 mF − 100 mF 0.01 0 100 120 140 160 25 400 20 Vin 6 300 Vout 150 Vout 5.2 5.1 5.0 200 4.9 150 4.8 100 5 −10 −0.5 125 250 5.5 0 100 TJ = 25°C Vin = 13.5 V trise/fall = 1 ms Cout = 10 mF 350 Vout, OUTPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) 30 75 Figure 13. Output Stability with Output Capacitor ESR 7.5 TJ = 25°C Iout = 5 mA 7 trise/fall = 1 ms Cout = 10 mF 6.5 40 50 Iout, OUTPUT CURRENT (mA) Figure 12. Output Current Limit vs. Junction Temperature −20 −1 10 Figure 10. Dropout Voltage vs. Junction Temperature 350 10 8 Vin, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) 6 TJ, JUNCTION TEMPERATURE (°C) 400 ILIM, OUTPUT CURRENT LIMIT (mA) TJ = 25°C 350 0 0.5 1 1.5 2 4.5 2.5 50 0 −0.4 4.7 Iout −0.2 0 0.2 0.4 0.6 0.8 TIME (ms) TIME (ms) Figure 14. Line Transient Figure 15. Load Transient www.onsemi.com 8 1 4.6 1.2 Vout, OUTPUT VOLTAGE (V) VDO, DROPOUT VOLTAGE (mV) 300 NCV48220 TYPICAL CHARACTERISTICS Vin, INPUT VOLTAGE (V) 9 80 8 70 12 7 10 6 Vout 8 5 6 4 4 3 TJ = 25°C Iout = 5 mA trise/fall = 1 ms Cout = 10 mF 2 0 −2 −4 −0.2 0 0.2 0.4 0.6 0.8 1.2 1 2 1 50 40 30 20 10 0 −1 1.6 1.4 TJ = 25°C Vin_DC = 13.5 V Vin_AC = 0.5 Vp−p Iout = 150 mA Cout = 10 mF 60 PSRR (dB) Vin 14 Vout, OUTPUT VOLTAGE (V) 16 0 10 100 1K TIME (ms) 45 9 40 8 IEN, ENABLE CURRENT (mA) 10 TJ = 125°C 7 6 TJ = 25°C 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 1M 10M TJ = 125°C 35 30 TJ = 25°C 25 20 15 10 5 0 10 0 10 5 15 20 25 30 35 VEN, ENABLE VOLTAGE (V) VEN, ENABLE VOLTAGE (V) Figure 18. Enable Current vs. Enable Voltage Figure 19. Enable Current vs. Enable Voltage 10 Vin = 13.5 V 9 Idis, DISABLE CURRENT (mA) 100K Figure 17. PSRR vs. Frequency Vrt, OUTPUT VOLTAGE RESET THRESHOLD (V) IEN, ENABLE CURRENT (mA) Figure 16. Power Up Transient 0 10K FREQUENCY (Hz) 8 7 6 5 4 3 2 1 0 −40 −20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) Figure 20. Disable Current vs. Junction Temperature 4.8 Vin = 13.5 V 4.75 4.7 4.65 4.6 4.55 4.5 −40 −20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) Figure 21. Output Voltage Reset Threshold vs. Junction Temperature www.onsemi.com 9 40 NCV48220 3.0 6.8 2.9 6.6 VCP_ON_OFF, CHARGE PUMP OPERATING THRESHOLD (V) VUVLO_Upper 2.8 2.7 2.6 VUVLO_Lower 2.5 2.4 2.3 2.2 −40 −20 0 20 40 60 80 Iout = 100 mA 6.4 VCP_OFF 6.2 6 5.8 VCP_ON 5.6 5.4 5.2 −40 −20 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) FSW, SWITCHING FREQUENCY (kHz) 8 6 4 Vin = 3 V Iout = 75 mA 20 40 80 60 100 120 140 160 480 470 460 450 440 430 420 410 400 −40 −20 0 20 40 80 100 120 140 160 Figure 25. Switching Frequency vs. Junction Temperature 6.5 10 VCP 6 TJ = 25°C Iout = 30 mA Cin = 4.7 mF CCP = 10 mF Cout = 10 mF 5 5.5 5 Vout 200 60 TJ, JUNCTION TEMPERATURE (°C) Vin 0 100 120 140 160 Vin = 13.5 V 15 −5 −200 80 500 Figure 24. Charge Pump Output Impedance vs. Junction Temperature 0 60 490 TJ, JUNCTION TEMPERATURE (°C) Vin, INPUT VOLTAGE (V) VCP, CHARGE PUMP OUTPUT VOLTAGE (V) Rout_CP, CHARGE PUMP OUTPUT IMPEDANCE (W) 10 0 40 Figure 23. Charge Pump Operating Threshold vs. Junction Temperature 12 0 −40 −20 20 TJ, JUNCTION TEMPERATURE (°C) Figure 22. Undervoltage Lockout vs. Junction Temperature 2 0 400 600 4.5 800 1000 1200 1400 1600 TIME (ms) Figure 26. Starting Profile Transient www.onsemi.com 10 Vout, OUTPUT VOLTAGE (V) VUVLO, UNDERVOLTAGE LOCKOUT THRESHOLD (V) TYPICAL CHARACTERISTICS NCV48220 Vin VCP_OFF Vin_UVLO rise Vin_UVLO fall t VCP VCP_LIM VCP_ON t Short term overcurrent Vout < tRR Long term > tRR VRT + VRH VRT t VRO tRD tRR tRD tRR VROH VROL t Figure 27. Reset Function, Charge Pump Function and Timing Diagram www.onsemi.com 11 NCV48220 DEFINITIONS General Current Limit All measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. Current Limit is value of output current by which output voltage drops below 96 % of its nominal value. PSRR Power Supply Rejection Ratio is defined as ratio of output voltage and input voltage ripple. It is measured in decibels (dB). Output voltage The output voltage parameter is defined for specific temperature, input voltage and output current values or specified over Line, Load and Temperature ranges. Line Transient Response Typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. Line Regulation The change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. Load Transient Response Typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low−load and high−load conditions. Load Regulation The change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. Thermal Protection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating. Dropout Voltage The input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. It is measured when the output drops 100 mV below its nominal value. The junction temperature, load current, and minimum input supply requirements affect the dropout level. Maximum Package Power Dissipation The power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower. Quiescent and Disable Currents Quiescent Current (Iq) is the difference between the input current (measured through the LDO input pin) and the output load current. If Enable pin is set to LOW the regulator reduces its internal bias and shuts off the output, this term is called the disable current (IDIS). www.onsemi.com 12 NCV48220 APPLICATIONS INFORMATION Circuit Description Low duty cycle pulse load current technique has been used to maintain junction temperature close to ambient temperature. List of recommended output capacitors: GCM31CR71H225MA55 (2.2 mF, 50 V, X7R, 1206) GCM31CR71C335KA37 (3.3 mF, 16 V, X7R, 1206) GCM31CR71E475MA55 (4.7 mF, 25 V, X7R, 1206) GCM31CC71E106MA03 (10 mF, 25 V, X7S, 1206) KCM55WC71E107MH13 (100 mF, 25 V, X7S, 2220) The NCV48220 is an integrated low dropout regulator with integrated battery voltage charge pump boost converter that provides a regulated voltage at 150 mA to the output. Device is enabled with an input to the enable pin. The regulator voltage is provided by a PMOS pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible dropout voltage. The output current capability is 150 mA, and the base drive quiescent current is controlled to prevent oversaturation when the input voltage is low or when the output is overloaded. Charge pump boost converter is active only during charge pump output voltage (input voltage of LDO) decreasing under charge pump operating activation threshold and inactive after input voltage increasing over charge pump operating deactivation threshold. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. CGA5L3X7R1H225M (2.2 mF, 50 V, X7R, 1206) CGA5L1X7R1E335M (3.3 mF, 25 V, X7R, 1206) CGA5L1X7R1E475M (4.7 mF, 25 V, X7R, 1206) CGA5L1X7R1E106M (10 mF, 25 V, X7R, 1206) CKG57NX7S1C107M (100 mF, 16 V, X7S, 2220) Charge Pump Capacitor Selection Low ESR capacitors are necessary to minimize power losses, especially at high load current during active charge pump boost mode. The exact value of CFLY and CCP is not important. Charge pump output impedance (Rout_CP) is given by equation 1. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (Vout) and drives the gate of a PMOS series pass transistor via a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PMOS is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. R out_CP ^ 2 S(R SW) ) f SW 1 C FLY )4 ESR FLY ) ESR C CP (eq. 1) Charge pump output voltage ripple is determined by the value of CCP and the load current (Iout). CCP is charged and discharged at a current roughly equal to the load current. V ripple_CP + Regulator Stability Considerations The input capacitor (Cin) and charge pump output capacitor (CCP) is necessary to stabilize the input impedance to avoid voltage line influences. The output capacitor (Cout) helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor Cout, shown in Figure 1 should work for most applications; see also Figure 13 for output stability at various load and Output Capacitor ESR conditions. Stable region of ESR in Figure 13 shows ESR values at which the LDO output voltage does not have any permanent oscillations at any dynamic changes of output load current. Marginal ESR is the value at which the output voltage waving is fully damped during four periods after the load change and no oscillation is further observable. ESR characteristics were measured with ceramic capacitors and additional series resistors to emulate ESR. 2 I OUT f SW C CP (eq. 2) This equation doesn’t including the impact of non−overlap time and CCP capacitor ESR. Since the output is not being driven during the non−overlap time, this time should be included in the ripple calculation. CCP capacitor discharge time is approximately 60 % of a switching period V ripple_CP + I OUT ǒ f SW 0.6 )2 C CP ESR C CP Ǔ (eq. 3) For example, with a 450 kHz switching frequency, a 10 mF CCP capacitor with an ESR of 0.25 W and a 100 mA load the ripple voltage is 65 mV peak to peak. Enable Input The enable pin is used to turn the regulator on or off. By holding the pin below 0.8 V, the output of the regulator will be turned off. When the voltage on the enable pin is greater than 2.5 V, the output of the regulator will be enabled to power its output to the regulated output voltage. The enable pin may be connected directly to the input pin to give constant enable to the output regulator. www.onsemi.com 13 NCV48220 RQJA, THERMAL RESISTANCE (5C/W) Thermal Considerations As power in the NCV48220 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCV48220 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV48220 can handle is given by: P D(MAX) + ƪTJ(MAX) ) TAƫ P D_CP1 + (2 R QJA CP inactive : P D_CP2 + V IN * V CP) ǒ V IN * V ǒ I OUT CP max. V ǒ V ǒ CP max. V CP_LIM P D_Iq + V in Ǔ CP_LIM ǒI * V OUT q@I OUT 160 140 1 oz, Single Layer 120 100 2 oz, Single Layer 80 60 1 oz, 4 Layer 0 Ǔ Ǔ I Out Ǔ 400 600 800 1000 Figure 28. Thermal Resistance vs. PCB Copper Area Hints Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the device and make traces as short as possible. Place filter components as near as possible to the device to increase EMC performance. Input Capacitor Cin is required if regulator is located far from power supply filter. If extremely fast input voltage transients are expected with slew rate in excess of 4 V/ms then appropriate input filter must be used. The filter can be composed of several capacitors in parallel. (eq. 5) Ǔ 200 Copper heat spreader area (mm2) I Out (eq. 6) P D_LDO + 180 (eq. 4) Since TJ is not recommended to exceed 150°C, then the NCV48220 soldered on 645 mm2, 1 oz copper area, FR4 can dissipate up to 1.2 W and up to 1.7 W for 4 layers PCB (all layers are 1 oz) when the ambient temperature (TA) is 25 °C. See Figure 28 for RQJA versus PCB area. Power dissipated is given by three main parts. The first is dependent on the charge pump boost mode activation. The second part including the power dissipated on LDO and the last represent current consumption. CP active : 200 (eq. 7) (eq. 8) The power dissipated by the NCV48220 can be calculated from the following equations: P D1 + P D_CP1 ) P D_LDO ) P D_Iq (eq. 9) P D2 + P D_CP2 ) P D_LDO ) P D_Iq (eq. 10) ORDERING INFORMATION Device NCV48220D50R2G Output Voltage Reset Delay Time†† Marking Package Shipping† 5.0 V 0 ms V4822050 SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ††For information about another Output Voltage, Reset Delay Time, Packages options contact factory. Reset Delay Time can be chosen from following list of values: 0, 2, 4, 8, 16, 32, 64 and 128 ms. www.onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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