NCV8665D50G

NCV8665 Linear Regulator - Low Dropout, Very Low Iq, Reset, Delay Reset 150 mA The NCV8665 is a precision 5.0 V fixed output, low dropout integrated voltage regulator with an output current capability of 150 mA. Careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent ground current of 30 mA. NCV8665 is pin for pin compatible with the NCV8675 and the NCV4275 and it could replace this part when lower output current, and very low quiescent current is required. The output voltage is accurate within ±2.0%, and maximum dropout voltage is 600 mV at full rated load current. It is internally protected against 45 V input transients, input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features. http://onsemi.com MARKING DIAGRAMS 1 D2PAK 5−PIN DS SUFFIX CASE 936A 5 • • 5 V Fixed Output (3.3 V and 2.5 V Versions are Also Available) ±2.0% Output Accuracy, Over Full Temperature Range 40 mA Maximum Quiescent Current at IOUT = 100 mA 600 mV Maximum Dropout Voltage at 150 mA Load Current Wide Input Voltage Operating Range of 5.5 V to 45 V Internal Fault Protection ♦ −42 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb−Free Devices VIN VOUT Bandgap Reference Error Amplifier Current Limit and Saturation Sense + − Thermal Shutdown AWLYWWG 1 Features • • • • • • V665−50G SOIC−8 D SUFFIX CASE 751 8 1 8 V6655 ALYWX G 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Lead Free Indicator PIN CONNECTIONS D2PAK Pin SOIC−8 1. VIN Pin 2. RO Tab, 3. GND* 4. D 5. VOUT * Tab is connected to Pin 3 1. VIN 2. RO 3. D 4. VOUT 5−8. GND ORDERING INFORMATION Reset Generator D See detailed ordering and shipping information in the dimensions section on page 9 of this data sheet. GND RO Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2008 October, 2019− Rev. 1 1 Publication Order Number: NCV8665/D NCV8665 PIN DESCRIPTIONS Symbol Function VIN Unregulated input voltage; 5.5 V to 45 V; Battery Input Voltage. Bypass to GND with a 0.1 mF ceramic capacitor. RO Reset Output; open collector active Reset (Accurate when VOUT > 1.0 V) GND D VOUT Ground; Pin 3 internally connected to Tab Reset Delay; timing capacitor to GND for Reset Delay function Output; ±2.0%, 150 mA. 10 mF, ESR < 16 W ABSOLUTE MAXIMUM RATINGS Pin Symbol, Parameter Symbol Min Max Unit VIN −42 +45 V VOUT, DC Voltage VOUT −0.3 +16 V Reset Output Voltage VRO −0.3 25 V Reset Output Current IRO −5.0 5.0 mA Reset Delay Voltage VD −0.3 7.0 V Reset Delay Current ID −2.0 2.0 mA Storage Temperature TSTG −55 +150 °C ESD Capability, Human body Model (Note 1) VESDHB 4000 V ESD Capability, Machine Model (Note 1) VESDMM 200 V VIN, DC Input Voltage Moisture Sensitivity Level MSL 1 − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model (HBM) tested per AEC−Q100−002 (EIA/JESD22−A 114C) ESD Machine Model (MM) tested per AEC−Q100−003 (EIA/JESD22−A 115C) 2. Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78. OPERATING RANGE Pin Symbol, Parameter Symbol Min Max Unit Input Voltage Operating Range VIN 5.5 45 V Junction Temperature TJ −40 150 °C Unit THERMAL RESISTANCE Symbol Min Max Junction to Ambient (Note 3) Parameter D2PAK RqJA − 85.4 Junction to Case (Note 3) D2PAK RqJC − 6.8 Junction to Ambient (Note 4) SOIC−8 RqJA − 138 Junction to Lead 6 (Note 4) SOIC−8 YqJL6 − 21 °C/W mounted on a 35x35x1mm FR4 PCB with a single layer of 100 mm2 of 1 oz copper heat spreading area. mounted on a 35x35x1mm FR4 PCB with a single layer of 100 mm2 of 1 oz copper heat spreading area including traces directly connected 3. As 4. As to the leads. Pb SOLDERING TEMPERATURE AND MSL Parameter Symbol Min Max Unit Lead Temperature Soldering Reflow (SMD styles only), Pb−Free (Note 5) Tsld − 265 pk °C MSL, 8−Lead EP, LS Temperature 260°C MSL 5. This device series incorporates ESD protection and exceeds the following ratings: Human Body Model (HBM)  2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM)  200 V per JEDEC standard: JESD22–A115. http://onsemi.com 2 1 − NCV8665 ELECTRICAL CHARACTERISTICS VIN = 13.5 V, TJ = −40°C to +150°C, unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Unit OUTPUT Output Voltage VOUT 0.1 mA  IOUT  150 mA (Note 6) 6 V  VIN  28 V 4.900 5.000 5.100 V Output Voltage VOUT 0 mA  IOUT  150 mA 5.5 V  VIN  28 V −40_C  TJ  125_C 4.900 5.000 5.100 V Line Regulation DVOUT versus VIN IOUT = 5 mA 8 V  VIN  32 V −25 5 +25 mV Load Regulation DVOUT Vs. IOUT 1 mA  IOUT  150 mA (Note 6) −35 5 +35 mV Dropout Voltage VIN − VOUT IOUT = 100 mA (Notes 6 and 7) IOUT = 150 mA (Notes 6 and 7) 200 250 500 600 mV IOUT = 100mA TJ = 25°C TJ = −40°C to +85°C 30 30 34 40 1.8 12 3.5 19 Quiescent Current Iq Active Ground Current IG(ON) IOUT = 50 mA (Note 6) IOUT = 150 mA (Note 6) Power Supply Rejection PSRR VRIPPLE = 0.5 VPP, F = 100 Hz Output Capacitor for Stability COUT ESR IOUT = 0.1 mA to 150 mA Reset Switching Threshold VOUT,rt − 4.50 Reset Output Low Voltage VROL RExt > 5.0 k, VOUT > 1.0 V − Reset Output Leakage Current IROH VROH = 5.0 V Reset Charging Current ID,C Upper Timing Threshold 69 10 mA mA %/V 16 mF W 4.65 4.80 V 0.20 0.40 V − 0 10 mA VD = 1.0 V 2.0 4.0 6.5 mA VDU − 1.2 1.3 1.4 V Reset Delay Time trd CD = 47 nF 10 16 22 ms Reset Reaction Time trr CD = 47 nF 1.5 4.0 ms RESET TIMING D AND OUTPUT RO PROTECTION Current Limit IOUT(LIM) VOUT = 4.5 V (Note 6) 150 500 mA Short Circuit Current Limit IOUT(SC) VOUT = 0 V (Note 6) 100 500 mA (Note 8) 150 200 °C Thermal shutdown threshold TTSD 6. Use pulse loading to limit power dissipation. 7. Dropout voltage = (VIN – VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V. 8. Not tested in production. Limits are guaranteed by design. http://onsemi.com 3 NCV8665 VIN IN CIN 100 nF 5 COUT 10 mF ID CD 47 nF 1 IOUT OUT D RO 4 2 3 GND Iq Figure 2. Application Circuit http://onsemi.com 4 IRO VOUT RRO 5.0 kW VRO NCV8665 TYPICAL CHARACTERISTIC CURVES 0.45 6 5 125°C 0.35 0.3 OUTPUT VOLTAGE (V) DROPOUT VOLTAGE (V) 0.4 25°C 0.25 0.2 −40°C 0.15 0.1 0.05 50 100 150 200 1 0 10 20 30 40 50 LOAD CURRENT (mA) INPUT VOLTAGE (V) Figure 3. NCV8665 Dropout Voltage vs. Load Current Figure 4. NCV8665 Input Voltage vs. Output Voltage (Full Range) 6 18 16 5 Unstable Region 14 4 Stable Region 12 ESR (W) OUTPUT VOLTAGE (V) 2 0 0 3 2 10 8 6 4 1 0 2 4 6 8 Vin = 13.5 V CLOAD  10 mF 2 Load = 5 mA 0 0 10 50 100 150 INPUT VOLTAGE (V) OUTPUT LOAD (mA) Figure 5. NCV8665 Input Voltage vs. Output Voltage (Low Voltage) Figure 6. NCV8665 Stability Curve 0.5 10 125°C 8 7 25°C 6 −40°C 5 4 3 2 1 Vin = 13.5 V 0.45 QUIESCENT CURRENT (mA) 9 QUIESCENT CURRENT (mA) 3 Load = 5 mA 0 0 4 125°C 25°C 0.4 0.35 −40°C 0.3 0.25 0.2 0.15 0.1 0.05 Vin = 13.5 V 0 0 0 50 100 150 200 0 5 10 15 20 25 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 7. NCV8665 Quiescent Current vs. Load Current (Full Range) Figure 8. NCV8665 Quiescent Current vs. Load Current (Light Load) http://onsemi.com 5 NCV8665 0.05 10 0.045 9 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) TYPICAL CHARACTERISTIC CURVES 0.04 0.035 0.03 0.025 0.02 0.015 0.01 Vin = 13.5 V LOAD = 100 mA 0.005 0 −50 0 50 100 LOAD = 50 mA 8 7 6 5 4 3 2 1 150 0 0 10 20 30 40 50 TEMPERATURE (°C) INPUT VOLTAGE Figure 9. NCV8665 Quiescent Current vs. Temperature Figure 10. NCV8665 Quiescent Current vs. Input Voltage http://onsemi.com 6 NCV8665 Circuit Description Tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however attention must be paid to ESR constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the capacitance and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 2, Application Circuit, should work for most applications; however, it is not necessarily the optimized solution. The NCV8665 is an integrated low dropout regulator that provides 5.0 V, 150 mA protected output and a signal for power on reset. The regulation is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. The output current capability is 150 mA, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures. The delay time for the reset output is adjustable by selection of the timing capacitor. See Figure 2, Application Circuit, for circuit element nomenclature illustration. Reset Output The reset output is used as the power on indicator to the microcontroller. This signal indicates when the output voltage is suitable for reliable operation of the controller. It pulls low when the output is not considered to be ready. RO is pulled up to VOUT by an external resistor, typically 5.0 kW in value. The input and output conditions that control the Reset Output and the relative timing are illustrated in Figure 11, Reset Timing. Output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. The delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0 V to the upper timing threshold voltage VDU of 1.8 V. The charging current for this is ID of 5.5 mA. By using typical IC parameters with a 47 nF capacitor on the D Pin, the following time delay is derived: tRD = CD * VDU / ID tRD = 47 nF * (1.8 V) / 5.5 mA = 15.4 ms Other time delays can be obtained by changing the CD capacitor value. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (VOUT) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. Regulator Stability Considerations The input capacitor (CIN) is necessary to stabilize the input impedance to avoid voltage line influences. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. http://onsemi.com 7 NCV8665 VI t < Reset Reaction Time VQ VQ,rt t Reset Charge Current dVD  dt CD VD Upper Timing Threshold VDU Lower Timing Threshold VDL t Reset Delay Time VRO Reset Reaction Time t Power−on−Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output Figure 11. Reset Timing Calculating Power Dissipation in a Single Output Linear Regulator In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The maximum power dissipation for a single output regulator (Figure 12) is: PD(max)  [VI(max)  VQ(min)] IQ(max) VI  VI(max)Iq where VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: T RqJA  150° C  A PD IQ II (1) SMART REGULATOR® VQ } Control Features Iq Figure 12. Single Output Regulator with Key Performance Parameters Labeled Heatsinks A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: (2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in Equation NO TAG will keep the die temperature below 150°C. RqJA  RqJC  RqCS  RqSA http://onsemi.com 8 (3) NCV8665 where functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D. 160 1000 140 SOIC−8 2 oz 100 80 D2PAK 10 60 1 40 20 SOIC−8 100 SOIC−8 1 oz 120 R(t), (°C/W) THERMAL RESISTANCE JUNCTION−TO−AIR (°C/W) RqJC is the junction−to−case thermal resistance, RqCS is the case−to−heatsink thermal resistance, RqSA is the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are D2PAK 1 oz Single Pulse D2PAK 2 oz 0 100 200 300 400 500 600 700 800 900 0.1 0.000001 0.0001 0.01 1 100 COPPER AREA (mm2) PULSE TIME (sec) Figure 13. Thermal Resistance vs. PCB Area Figure 14. NCV8675 @ PCB Cu Area 100 mm2 PCB Cu thk 1 oz ORDERING INFORMATION Package Shipping† NCV8665DS50G D2PAK (Pb−Free) 50 Units / Rail NCV8665DS50R4G D2PAK (Pb−Free) 800 / Tape & Reel NCV8665D50G SOIC−8 (Pb−Free) 98 Units / Rail NCV8665D50R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 5−LEAD CASE 936A−02 ISSUE E DATE 28 JUL 2021 SCALE 1:1 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxx A WL Y WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASH01006A D2PAK 5−LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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