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onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
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Half Bridge Gate
Driver(Isolated High &
Non-Isolated Low)
NCV57200
The NCV57200 is a high voltage gate driver with one non−isolated
low side gate driver and one galvanic isolated high or low side gate
driver. It can directly drive two IGBTs in a half bridge configuration.
Isolated high side driver can be powered with an isolated power supply
or with Bootstrap technique from the low side power supply.
The galvanic isolation for the high side gate driver guarantees
reliable switching in high power applications for IGBTs that operate
up to 800 V, at high dv/dt. The optimized output stages provide a mean
of reducing IGBT losses. Its features include two independent inputs
with deadtime and interlock, accurate asymmetric UVLOs, and short
and matched propagation delays. The NCV57200 operates with its
VCC/VB up to 20 V.
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8
1
SOIC−8 NB
CASE 751−07
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Peak Current Output (+1.9 A / −2.3 A)
Low Output Voltage Drop for Enhanced IGBT Conduction
Secured Output Low State without VDD/VB
Floating Channel for Bootstrap Operation up to +800 V
CMTI up to 50 kV / ms
Reliable Operation for VS Negative Swing to −800 V
VDD & VBS Supply Range up to 20 V
3.3 V, 5 V, and 15 V Logic Input
Asymmetric Under Voltage Lockout Thresholds for High Side and
Low Side
Matched Propagation Delay 90 ns
Built−in 20 ns Minimum Pulse Width Filter (or Input Noise Filter)
Built−in 340 ns Dead−Time and High and Low Inputs Interlock
Output in Phase with Input Signal
AEC−Q100 Qualified and PPAP Capable
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
•
•
•
•
OBC
PTC Heater
e−Compressors
Automotive Power Supplies
© Semiconductor Components Industries, LLC, 2019
December, 2019 − Rev. 0
8
NCV57200
ALYWX
G
1
NCV57200
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VDD
VB
HIN
HO
LIN
VS
GND
LO
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1
Publication Order Number:
NCV57200/D
NCV57200
VB
VDD
VDD
UVLO2
Minimum
Pulse
Width
HIN
Input
Logic
HO
Output
Logic
VS
Deadtime
and
Interlock
VCC
Minimum
Pulse
Width
LIN
Matching
Delay
UVLO1
GND
Figure 1. Simplified Block Diagram
VDD
VDD
VB
HIN
HO
LIN
VS
GND
LO
Figure 2. Simplified Application Schematics
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2
LO
NCV57200
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
VDD
1
Power
Low side and main power supply. A good quality bypassing capacitor is required
from this pin to GND and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than VUVLO1−OUT−ON is present. Please
see Figure 5 for more details. A filter time of typical 1.5 ms helps to suppress
noise on VDD pin.
HIN
2
I
High side non-inverting gate driver input. It has an equivalent pull−down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at HIN before HO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to VDD.
There is deadtime and interlocking logic between HIN and LIN.
LIN
3
I
Low side non-inverting gate driver input. It has an equivalent pull−down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at LIN before LO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to VDD.
There is deadtime and interlocking logic between HIN and LIN.
GND
4
Power
LO
5
O
VS
6
Power
HO
7
O
VB
8
Power
Logic ground and low side driver return.
Low side driver output that provides the appropriate drive voltage and source/
sink current to the IGBT gate. LO is actively pulled low during startup and under
UVLO1 condition. There is deadtime and interlocking logic to prevent unintended
HO and LO cross conduction.
Bootstrap return or high side floating supply offset.
Galvanic isolated high side driver output that provides the appropriate drive
voltage and source/sink current to the IGBT gate. HO is actively pulled low
during startup and under UVLO2 condition. There is deadtime and interlocking
logic to prevent unintended HO and LO cross conduction.
Bootstrap or high side floating power supply. A good quality bypassing capacitor
is required from this pin to VS and should be placed close to the pins for best
results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than VUVLO2−OUT−ON is present. Please
see Figure 5 for more details. A filter time of typical 1.5 ms helps to suppress
noise on VB pin.
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3
NCV57200
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Parameter
High−Side Offset Voltage
Symbol
Minimum
Maximum
Unit
VS
−900
900
V
−900
900
−900
900
−900
900
High−Side Offset Voltage (tp < 500 ns)
VB
High−Side Supply Voltage
High−Side Supply Voltage (tp < 500 ns)
V
Low−Side and Logic−Fixed Supply Voltage
VDD
−0.3
25
V
High−Side Floating Supply Voltage
VBS
−0.3
25
V
High−Side Floating Output Voltage VHO
VHO
VS−0.3
VB+0.3
V
Low−Side Floating Output Voltage VLO
VLO
−0.3
VDD+0.3
V
Logic Input Voltage (HIN, LIN)
VIN
−0.3
VDD+0.3
V
±50
V/ns
Allowable Offset Voltage Slew Rate
dVS/dt
Maximum Junction Temperature
TJ(max)
−40
150
°C
TSTG
−65
150
°C
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESDHBM
±4
kV
ESD Capability, Charged Device Model (Note 2)
ESDCDM
±2
kV
Moisture Sensitivity Level
MSL
1
−
Lead Temperature Soldering Reflow
TSLD
260
°C
(SMD Styles Only), Pb Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 125°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Thermal Characteristics, SOIC−8 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Symbol
Value
Unit
RqJA
167
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. RECOMMENDED OPERATING RANGES (Note 6)
Symbol
Min
Max
Unit
High−Side Supply Voltage
VB
VS+UVLO2
VS+20
V
High−Side Supply Offset Voltage
VS
−800
800
V
High−Side (HO) Output Voltage
VHO
VS
VB
V
Low−Side (LO) Output Voltage
VLO
GND
VDD
V
Parameter
Logic Input Voltage (HIN, LIN)
VIN
GND
VDD
V
Low−Side Supply Voltage
VDD
UVLO1
20
V
TA
−40
+125
°C
Ambient Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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4
NCV57200
Table 5. ELECTRICAL CHARACTERISTICS VDD = VBS = 15 V.
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Test Conditions
Symbol
Min
Typ
Max
Unit
VBS Supply Under Voltage
Output Enabled
VUVLO2−OUT
11
11.5
12
V
VBS Supply Under Voltage
Output Disabled
VUVLO2−OUT
10
10.5
11
V
VBS Supply Voltage Output
Enabled/Disabled Hysteresis
VUVLO2−HYST
VDD Supply Under Voltage
Output Enabled
VUVLO1−OUT
VDD Supply Under Voltage
Output Disabled
VUVLO1−OUT
VDD Supply Voltage Output
Enabled/Disabled Hysteresis
VUVLO1−HYST
1.0
IHV_LEAK1
IHV_LEAK2
20
200
600
nA
Parameter
VOLTAGE SUPPLY
−ON
−OFF
1.0
V
12
12.5
13
V
11
11.5
12
V
−ON
−OFF
V
Leakage Current Between VS and
GND
VS = ± 800 V, TA = 25°C
VS = ± 800 V, TA = −40°C to 125°C
Quiescent Current VBS Supply
(VB Only)
HO = Low
IQBS1
260
325
mA
Quiescent Current VBS Supply
(VB Only)
HO = High
IQBS2
330
440
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = Float, VHIN = 0 V,
IQDD1
380
440
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = 3.3 V, VHIN = 0 V,
IQDD2
440
500
mA
Quiescent Current VDD Supply
(VDD Only)
VLIN = 0 V, VHIN = 3.3 V,
IQDD3
2.4
3
mA
0.9
V
LOGIC INPUT
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
Logic “1” Input Bias Current
VLIN = 3.3 V, VHIN = 3.3 V
Logic “1” Input Bias Current
Logic “0” Input Bias Current
2.4
V
ILIN1+, IHIN1+
25
50
mA
VLIN = 20 V, VHIN = 20 V,
VDD = VBS = 20 V
ILIN2+, IHIN2+
100
150
mA
VLIN = 0 V, VHIN = 0 V
ILIN−, IHIN−
40
100
nA
ISINK = 200 mA, TA = 25°C
VOL1
0.2
0.3
V
ISINK = 200 mA,
TA = −40°C to 125°C
VOL2
ISRC = 200 mA, TA = 25°C
VOH1
14.4
ISRC = 200 mA,
TA = −40°C to 125°C
VOH2
14
DRIVER OUTPUT
Output Low State
Output High State
0.5
14.5
V
A
Peak Driver Current, Sink
(Note 7)
VHO = VLO = 15 V
IPK−SNK1
2.3
VHO = VLO = 9 V
(near Miller Plateau)
IPK−SNK2
2.1
Peak Driver Current, Source
(Note 7)
VHO = VLO = 0 V
IPK−SRC1
1.9
VHO = VLO = 9 V
(near Miller Plateau)
IPK−SRC2
1.5
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5
A
NCV57200
Table 5. ELECTRICAL CHARACTERISTICS VDD = VBS = 15 V.
For typical values TA = 25°C, for min/max values, TA is the operating ambient temperature range that applies, unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
0.8
1.3
V
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
(VHO – VB) / (VLO – VDD)
IHO = 100 mA, ILO = 100 mA
(pulse test, tCLPmax = 10 ms)
VCLAMP−OUT
DYNAMIC CHARACTERISTIC
HO High Propagation Delay
CLOAD = 1 nF, VIH to 10% of Output
Change for PW > 150 ns
tPD−ON−H
60
90
110
ns
HO Low Propagation Delay
CLOAD = 1 nF, VIL to 90% of Output
Change for PW > 150 ns
tPD−OFF−H
60
90
110
ns
Propagation Delay Distortion(HS)
(= tPD−ON− tPD−OFF)
PW >150 ns
tDISTORT−H
−25
0
25
ns
LO High Propagation Delay
CLOAD = 1 nF, VIH to 10% of Output
Change for PW > 150 ns
tPD−ON−L
60
90
110
ns
LO Low Propagation Delay
CLOAD = 1 nF, VIL to 90% of Output
Change for PW > 150 ns
tPD−OFF−L
60
90
110
ns
Propagation Delay Distortion(LS)
(= tPD−ON− tPD−OFF)
PW >150 ns
tDISTORT−L
−25
0
25
ns
High Prop Delay Distortion between
High and Low Sides
PW > 150 ns
tDISTORT−HLH
−25
0
25
ns
Low Prop Delay Distortion between
High and Low Sides
PW > 150 ns
tDISTORT−HLL
−25
0
25
ns
Rise Time(HS) (see timing diagram)
CLOAD = 1 nF,
10% to 90% of Output Change
tRISE−H
13
ns
Fall Time(HS) (see timing diagram)
CLOAD = 1 nF,
90% to 10% of Output Change
tFALL−H
8
ns
Rise Time(LS) (see timing diagram)
CLOAD = 1 nF,
10% to 90% of Output Change
tRISE−L
13
ns
Fall Time(LS) (see timing diagram)
CLOAD = 1 nF,
90% to 10% of Output Change
tFALL−L
8
ns
Deadtime, HO Delays
VLIN/HIN = 0 V and 3.3 V
tDT1
340
ns
Deadtime, LO Delays
VLIN/HIN = 0 V and 3.3 V
tDT2
350
ns
tMDT
10
ns
Deadtime Matching
Minimum Pulse Width Filtering Time
tMIN1, tMIN2
TA = 25°C
10
40
ns
UVLO Fall Delay (HO and LO)
tUV1
1300
ns
UVLO Rise Delay (HO and LO)
tUV2
1100
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Values based on design and/or characterization.
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6
NCV57200
VIH
VIL
HIN/LIN
tMIN
tFALL
tRISE
90%
tPD−ON
tMIN
tPD−OFF
HO/LO
10%
Figure 3. Propagation Delay, Rise and Fall Time
VCC
HIN/
LIN
Clamping
Circuit
Figure 4. Input Pin Structure
HIN/LIN
VUVLOx−OUT−ON
VUVLOx−OUT−OFF
VCC / VBB
tUV
tUV
VUVLOx−OUT−ON
VUVLOx−OUT−OFF
HO/LO
Figure 5. UVLO
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7
NCV57200
Figure 6. Deadtime, Interlock and Output Minimum Pulse Width
HIN
tMIN1
tMIN2
tDT1
tDT2
tMIN1
LIN
tMIN2
Figure 7. Input Circuit
ORDERING INFORMATION
Device
Package
Shipping†
NCV57200DR2G
SOIC−8 (Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NCV57200
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
(Pb−Free)
IC
4.0
0.155
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
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9
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
NCV57200
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
www.onsemi.com
10
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
NCV57200
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