NCV7342MW3R2G

NCV7342 High Speed Low Power CAN Transceiver Description The NCV7342 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7342 is an addition to the CAN high−speed transceiver family complementing NCV734x CAN stand−alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. Due to the wide common−mode voltage range of the receiver inputs and other design features, the NCV7342 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. www.onsemi.com 8 1 1 DFN8 MW SUFFIX CASE 506DG SOIC−8 D SUFFIX CASE 751AZ MARKING DIAGRAMS 8 Features • Compatible with the ISO 11898−2, ISO 11898−5 Standards • High Speed (up to 1 Mbps) • VIO Pin on NCV7342−3 Version Allowing Direct Interfacing with • • • • • Quality • Wettable Flank Package for Enhanced Optical Inspection • NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable NV7342−x ALYWG G 1 NV7342−x= Specific Device Code x = 0 or 3 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENTS TxD GND VCC RxD 8 1 2 3 4 TxD 1 GND 2 VCC 3 RxD 4 NV7342−x ALYWG G • • • • • • • 3 V to 5 V Microcontrollers VSPLIT Pin on NCV7342−0 Version for Bus Common Mode Stabilization Very Low Current Consumption in Standby Mode with Wake−up via the Bus Excellent Electromagnetic Susceptibility (EMS) Level Over Full Frequency Range. Very Low Electromagnetic Emissions (EME) Low EME Also Without Common Mode (CM) Choke Bus Pins Protected Against >15 kV System ESD Pulses Transmit Data (TxD) Dominant Time−out Function Bus Dominant Time−out function in Standby Mode Under All Supply Condition the Chip Behaves Predictably No Disturbance of the Bus Lines with an Unpowered Node Thermal Protection Bus Pins Protected Against Transients in an Automotive Environment Bus Pins Short Circuit Proof to Supply Voltage and Ground These are Pb−Free Devices 1 NV7342−x ALYW G G 7 6 5 STB CANH CANL VSPLIT (−0) VIO (−3) 8 STB 7 CANH EP Flag 6 CANL 5 VIO (Top Views) Typical Applications ORDERING INFORMATION • Automotive • Industrial Networks See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 4 1 Publication Order Number: NCV7342/D NCV7342 Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol VCC VUVVcc Max Unit Power supply voltage Parameter Conditions Min 4.5 Typ 5.5 V Undervoltage detection voltage on pin VCC (NCV7342−3 only) 3.5 4.5 V ICC Supply current Dominant; VTxD = 0 V Recessive; VTxD = VIO 75 10 mA ICCS Supply current in standby mode including VIO current TJ v 100°C, (Note 1) 15 mA VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V VCANH,L DC voltage between CANH and CANL pin 0 < VCC < 5.5 V −50 +50 V VESD Electrostatic discharge voltage IEC 61000−4−2 at pins CANH and CANL −15 15 kV VO(dif)(bus_dom) Differential bus output voltage in dominant state 45 W < RLT < 65 W 1.5 3 V CM−range Input common−mode range for comparator Guaranteed differential receiver threshold and leakage current −35 +35 V Cload Load capacitance on IC outputs 15 pF tpd_dr Propagation delay TxD to RxD dominant to recessive transition See Figure 8 Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 100 230 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition See Figure 8 Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 120 230 ns 150 °C TJ Junction temperature −40 1. Not tested in production. Guaranteed by design and prototype evaluation. www.onsemi.com 2 NCV7342 BLOCK DIAGRAMS VCC 3 VCC NCV7342−0 7 Thermal TxD VCC Timer 5 VCC 8 STB VSPLIT VSPLIT Mode & Driver Wake−up Control 6 CANL Control 4 Wake−up RxD CANH Shutdown 1 COMP Filter 2 GND COMP RB 20121109 Figure 1. NCV7342−0 Block Diagram www.onsemi.com 3 NCV7342 VIO VCC 3 5 VIO NCV7342−3 7 Thermal CANH Shutdown 1 TxD Timer VIO 8 STB Mode & Driver Wake−up Control 6 CANL Control 4 Wake−up RxD COMP Filter 2 GND COMP RB 20121109 Figure 2. NCV7342−3 Block Diagram www.onsemi.com 4 NCV7342 TYPICAL APPLICATION VBAT 5V−reg 3V−reg VIO VIO VCC 3 5 RLT = 60 W 7 CANH STB 8 Micro CLT = 4.7 nF CAN BUS NCV7342−3 RxD Controller 4 TxD 6 1 CANL RLT = 60 W 2 GND GND RB20120816 Figure 3. Application Diagram NCV7342−3 VBAT IN OUT 5V−reg VCC VCC 3 STB 8 RxD 4 TxD NCV7342−0 Micro Controller 7 5 1 RB20120816 6 RLT = 60 W CANH CANL RLT = 60 W 2 GND CLT = 4.7 nF VSPLIT GND Figure 4. Application Diagram NCV7342−0 Table 2. PIN FUNCTION DESCRIPTION Pin Name 1 TxD Description Transmit data input; Low input Ù dominant driver; internal pull−up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter Ù Low output 5 5 VIO VSPLIT Input/Output pins supply voltage. On NCV7342−3 only Common−mode stabilization output. On NCV7342−0 only 6 CANL Low−level CAN bus line (Low in dominant mode) 7 CANH High−level CAN bus line (High in dominant mode) 8 STB EP Exposed Pad Standby mode control input Connect to GND or left floating www.onsemi.com 5 CAN BUS NCV7342 FUNCTIONAL DESCRIPTION monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake−up request is detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of tdwakerd. The RxD pin is driven Low by the transceiver to inform the controller of the wake−up request. NCV7342 has two versions which differ from each other only by function of pin 5. NCV7342−0: Pin 5 is common mode stabilization output VSPLIT. (see Figure 4) This version is full replacement of NCV7340. NCV7342−3: Pin 5 is VIO pin, which is supply pin for transceiver digital inputs/output (supplying pins TxD, RxD, STB) The VIO pin should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller, the I/O levels between microcontroller and transceiver are properly adjusted. This adjustment allows communication between 3 V microcontroller and the transceiver. (See Figure 3) VIO Supply Pin The VIO pin (available only on NCV7342−3 version) should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the I/O levels between microcontroller and transceiver are properly adjusted. See Figure 3. Pin VIO also provides the internal supply voltage for low−power differential receiver of the transceiver. This allows detection of wake−up request even when there is no supply voltage on Pin VCC. Operating Modes NCV7342 provides two modes of operation as illustrated in Table 3. These modes are selectable through pin STB. Split Circuit The VSPLIT pin (available on NCV7342−0 version) is operational only in normal mode. In standby mode this pin is floating. The VSPLIT can be connected as shown in Figure 4 or, if it’s not used, can be left floating. Its purpose is to provide a stabilized DC voltage of 0.5 · VCC to the bus reducing possible steps in the common−mode signal, therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 · VCC voltage. Table 3. OPERATING MODES Pin RxD Pin STB Mode Low Normal Bus dominant Bus recessive High Standby Wake−up request detected No wake−up request detected Low High Normal Mode In normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME. Wake−up When a valid wake−up (dominant state longer than tWake) is received during the standby mode, the RxD pin is driven Low after tdwakerd. The wake−up detection is not latched: RxD returns to High state after tdwakedr when the bus signal is released back to recessive – see Figure 5. Standby Mode In standby mode both the transmitter and receiver are disabled and a very low−power differential receiver >tWake 1 MW 0.45 0.55 VCC ISPLIT(i) VSPLIT leakage current Standby mode −5 +5 mA ISPLIT(lim) VSPLIT limitation current Normal mode 1.3 5 mA 2.8 5.5 V 14 mA VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version VIO Supply voltage on pin VIO IIOS Supply current on pin VIO in standby mode TJ v 100°C (Note 11) 10. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 11. Not tested in production. Guaranteed by design and prototype evaluation. 12. In case VIO > VCC, the limit is VIO + 0.3 V www.onsemi.com 10 NCV7342 Table 6. CHARACTERISTICS VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 10); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO. Symbol Parameter Conditions Min Typ Max Normal mode Dominant; VTxD = 0 V Recessive; VTxD = VIO 0.30 0.29 0.70 0.44 1.10 0.68 Unit VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version IIONM VUVDVIO Supply current on pin VIO Undervoltage detection voltage on VIO pin mA 1.3 2.7 V 200 °C THERMAL SHUTDOWN TJ(SD) Shutdown junction temperature junction temperature rising 160 180 TIMING CHARACTERISTICS (See Figure 7 and 8) td(TxD−BUSon) Delay TxD to bus active Ci = 100 pF between CANH to CANL 60 ns td(TxD−BUSoff) Delay TxD to bus inactive Ci = 100 pF between CANH to CANL 30 ns td(BUSon−RxD) Delay bus active to RxD CRxD = 15 pF 60 ns td(BUSoff−RxD) Delay bus inactive to RxD CRxD = 15 pF 70 ns tpd_dr Propagation delay TxD to RxD dominant to recessive transition See Figure 8 Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 100 230 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition See Figure 8 Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 120 230 ns td(stb−nm) Delay standby mode to normal mode 47 ms 0.5 2.1 5 ms Valid bus wake−up event, CRxD = 15 pF 1 3.5 10 ms Delay to flag end of wake event (dominant to recessive transition) See Figure 5 Valid bus wake−up event, CRxD = 15 pF 0.5 2.6 6 ms tWake(RxD) Minimum pulse width on RxD See Figure 5 5 ms tWake CRxD = 15 pF 0.5 tdom(TxD) TxD dominant time for time out VTxD = 0 V 1.3 5 ms tdom(bus) Bus dominant time out Standby mode 1.3 5 ms tWake Dominant time for wake−up via bus tdwakerd Delay to flag wake event (recessive to dominant transitions) See Figure 5 tdwakedr ms 10. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 11. Not tested in production. Guaranteed by design and prototype evaluation. 12. In case VIO > VCC, the limit is VIO + 0.3 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 11 NCV7342 MEASUREMENT SET−UPS AND DEFINITIONS +5 V 100 nF VIO VCC 3 5 CANH 7 TxD 1 nF NCV7342 1 Transient Generator RxD 1 nF 4 6 CANL 2 8 15 pF RB20121608 GND STB Figure 6. Test Circuit for Automotive Transients +5 V 100 nF VIO 47 uF VCC 5 3 CANH 7 NCV7342 TxD 1 100 pF RL RxD 4 6 CANL 2 8 15 pF STB RB20120816 GND Figure 7. Test Circuit for Timing Characteristics www.onsemi.com 12 NCV7342 recessive TxD recessive dominant 50% 50% CANH CANL 0.9 V Vi(dif) = VCANH − VCANL 0.5 V 0.3 x VCC* RxD td(TxD−BUSon) 0.7 x VCC* td(TxD−BUSoff) td(BUSon−RxD) tpd_rd tpd_dr *On NCV7342−3 VCC is replaced by VIO td(BUSoff−RxD) RB20130429 Figure 8. Transceiver Timing Diagram DEVICE ORDERING INFORMATION Part Number Description NCV7342D10R2G High Speed CAN Transceiver with Standby and VSPLIT pin NCV7342D13R2G High Speed CAN Transceiver with Standby and VIO pin NCV7342MW3R2G High Speed CAN Transceiver with Standby and VIO pin Package Shipping† SOIC 150 8 GREEN (Matte Sn, JEDEC MS−012) (Pb−Free) 3000 / Tape & Reel DFN 8 Wettable Flank (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 13 NCV7342 PACKAGE DIMENSIONS SOIC−8 CASE 751AZ ISSUE B 0.10 C D NOTES 4&5 45 5 CHAMFER D h NOTE 6 D A 8 H 2X 5 0.10 C D E E1 NOTES 4&5 L2 1 0.20 C D L C DETAIL A 4 8X B NOTE 6 TOP VIEW b 0.25 M C A-B D NOTES 3&7 DETAIL A A2 NOTE 7 0.10 C A e A1 NOTE 8 SIDE VIEW SEATING PLANE C c END VIEW SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE. 5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT­ TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER­ MOST EXTREMES OF THE PLASTIC BODY AT DATUM H. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 A2 b c D E E1 e h L L2 MILLIMETERS MIN MAX --1.75 0.10 0.25 1.25 --0.31 0.51 0.10 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.25 0.41 0.40 1.27 0.25 BSC RECOMMENDED SOLDERING FOOTPRINT* 8X 0.76 8X 1.52 7.00 1 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 14 NCV7342 PACKAGE DIMENSIONS DFN8, 3x3, 0.65P CASE 506DG ISSUE A PIN ONE REFERENCE 2X 0.10 C ALTERNATE TERMINAL CONSTRUCTION E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW A3 0.05 C A SIDE VIEW C A1 SEATING PLANE 2.56 ÇÇÇÇÇÇ ÇÇÇÇÇÇ D2 DETAIL A 1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 3.00 BSC 2.30 2.50 3.00 BSC 1.50 1.70 0.65 BSC 0.30 TYP 0.35 0.45 RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 4 8X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DETAIL A ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ 0.10 C 2X L A B D 4 L 8X 0.60 3.30 1.70 ÇÇÇÇÇÇ ÇÇÇÇÇÇ E2 1 K 8 5 e/2 e 8X 0.65 PITCH b 0.10 C A B 0.05 C 8X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NOTE 3 BOTTOM VIEW ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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