NCV7356
CAN Transceiver, Single Wire
The NCV7356 is a physical layer device for a single wire data link
capable of operating with various Carrier Sense Multiple Access
with Collision Resolution (CSMA/CR) protocols such as the Bosch
Controller Area Network (CAN) version 2.0. This serial data link
network is intended for use in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor and/or
dedicated logic devices which use the network.
The network shall be able to operate in either the normal data rate
mode or a high−speed data download mode for assembly line and
service data transfer operations. The high−speed mode is only intended
to be operational when the bus is attached to an off−board service
node. This node shall provide temporary bus electrical loads which
facilitate higher speed operation. Such temporary loads should be
removed when not performing download operations.
The bit rate for normal communications is typically 33 kbit/s, for
high−speed transmissions like described above a typical bit rate of 83
kbit/s is recommended. The NCV7356 features undervoltage lockout,
timeout for faulty blocked input signals, output blanking time in case
of bus ringing and a very low sleep mode current.
The devi c e is compl i a nt wit h GMW3089V2. 4
General Motors Corporation specification.
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MARKING DIAGRAMS
8
8
SOIC−8
D SUFFIX
CASE 751
•
14
January, 2017 − Rev. 13
NCV7356G
AWLYWW
1
SOIC−14
D SUFFIX
CASE 751A
1
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
TxD 1
Fully Compatible with J2411 Single Wire CAN Specification
60 mA (max) Sleep Mode Current
Operating Voltage Range 5.0 to 27 V
Up to 100 kbps High−Speed Transmission Mode
Up to 40 kbps Bus Speed
Selective BUS Wake−Up
Logic Inputs Compatible with 3.3 V and 5 V Supply Systems
Control Pin for External Voltage Regulators (14 Pin Package Only)
Standby to Sleep Mode Timeout
Low RFI Due to Output Wave Shaping
Fully Integrated Receiver Filter
Bus Terminals Short−Circuit and Transient Proof
Loss of Ground Protection
Protection Against Load Dump, Jump Start
Thermal Overload and Short Circuit Protection
ESD Protection of 4.0 kV on CANH Pin (2.0 kV on Any Other Pin)
Undervoltage Lock Out
Bus Dominant Timeout Feature
Internally Fused Leads in SO−14 Package
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2017
1
14
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
•
•
V7356
ALYW
G
1
1
8 GND
MODE0 2
7 CANH
MODE1 3
6 LOAD
RxD 4
5 VBAT
(Top View)
GND 1
14 GND
TxD 2
13 NC
MODE0 3
12 CANH
MODE1 4
11 LOAD
RxD
10 VBAT
5
NC 6
9
INH
GND 7
8
GND
(Top View)
ORDERING INFORMATION
Package
Shipping†
NCV7356D1G
SOIC−8
(Pb−Free)
98 Units / Rail
NCV7356D1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
NCV7356D2G
SOIC−14
(Pb−Free)
55 Units / Rail
NCV7356D2R2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCV7356/D
NCV7356
VBAT
NCV7356
−IIL_TxD
5 V Supply
and
References
Biasing and
VBAT Monitor
Reverse
Current
Protection
RC−OSC
3.6 V (max)*
Pull−Up
Voltage
Wave Shaping
CAN Driver
TxD
CANH
Time Out
Feedback
Loop
RL
Input Filter
MODE0
LOAD
MODE
CONTROL
MODE1
Receive
Comparator
Loss of
Ground
Detection
RxD
RxD Blanking
Time Filter
Reverse
Current
Protection
GND
*Not tested in production, guaranteed by design.
Figure 1. 8−Pin Package Block Diagram
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2
NCV7356
VBAT
INH
NCV7356
−IIL_TxD
5 V Supply
and
References
Biasing and
VBAT Monitor
Reverse
Current
Protection
RC−OSC
3.6 V (max)*
Pull−Up
Voltage
Wave Shaping
CAN Driver
TxD
CANH
Time Out
Feedback
Loop
RL
Input Filter
MODE0
LOAD
MODE
CONTROL
MODE1
Receive
Comparator
Loss of
Ground
Detection
RxD
RxD Blanking
Time Filter
Reverse
Current
Protection
GND
*Not tested in production, guaranteed by design.
Figure 2. 14−Pin Package Block Diagram
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3
NCV7356
PACKAGE PIN DESCRIPTION
SOIC−8
SOIC−14
Symbol
Description
1
2
TxD
2
3
MODE0
Operating mode select input 0.
3
4
MODE1
Operating mode select input 1.
4
5
RxD
Receive data from CAN to microprocessor.
5
10
VBAT
Battery input voltage.
Transmit data from microprocessor to CAN.
6
11
LOAD
Resistor load (loss of ground detection low side switch).
7
12
CANH
Single wire CAN bus pin.
8
1, 7, 8, 14
GND
−
6, 13
NC
No Connection (Note 1)
−
9
INH
Control pin for external voltage regulator (high voltage high side switch) (14 pin package only)
Ground
1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package.
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4
NCV7356
Electrical Specification
All voltages are referenced to ground (GND). Positive
currents flow into the IC. The maximum ratings given in
the table below are limiting values that do not lead to a
permanent damage of the device but exceeding any of these
limits may do so. Long term exposure to limiting values
may affect the reliability of the device.
MAXIMUM RATINGS
Rating
Symbol
Condition
Min
Max
Unit
VBAT
−
−0.3
18
V
Load Dump; t < 500 ms
−
40
V (peak)
Jump Start; t < 1.0 min
−
27
V
Supply Voltage, Normal Operation
Short−Term Supply Voltage, Transient
VBAT.LD
Transient Supply Voltage
VBAT.TR1
ISO 7637/1 Pulse 1 (Note 2)
−50
−
V
Transient Supply Voltage
VBAT.TR2
ISO 7637/1 Pulses 2 (Note 2)
−
100
V
Transient Supply Voltage
VBAT.TR3
ISO 7637/1 Pulses 3A, 3B
−200
200
V
VBAT < 27 V
−20
CANH Voltage
VCANH
V
40
VBAT = 0 V
−40
Transient Bus Voltage
VCANHTR1
ISO 7637/1 Pulse 1 (Note 3)
−50
−
V
Transient Bus Voltage
VCANHTR2
ISO 7637/1 Pulses 2 (Note 3)
−
100
V
Transient Bus Voltage
VCANHTR3
ISO 7637/1 Pulses 3A, 3B (Note 3)
−200
200
V
Via RT > 2.0 kW
−40
40
V
DC Voltage on Pin LOAD
VLOAD
DC Voltage on Pins TxD, MODE1, MODE0, RxD
VDC
−
−0.3
7.0
V
VESDBUS
Human Body Model
(with respect to VBAT and GND)
Eq. to Discharge 100 pF with 1.5 kW
−4000
4000
V
ESD Capability of Any Other Pin
(Note 4)
VESD
Human Body Model
Eq. to Discharge 100 pF with 1.5 kW
−2000
2000
V
Maximum Latchup Free Current at Any Pin
ILATCH
−
−500
500
mA
Storage Temperature
TSTG
−
−55
150
°C
Junction Temperature
TJ
−
−40
150
°C
260
°C
ESD Capability of CANH
(Note 4)
Peak Reflow Soldering Temperature: Pb−Free, 60 s to 150 s above 217°C (Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 mF blocking capacitor.
3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.
4. ESD measured per Q100−002 (EIA/JESD22−A114−A).
5. For additional information, please see or download the ON Semiconductor Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
TYPICAL THERMAL CHARACTERISTICS
Test Condition, Typical Value
Min Pad Board
1, Pad Board
Unit
Junction−to−Lead (psi−JL7, YJL8) or Pins 6−7
57 (Note 6)
51 (Note 7)
°C/W
Junction−to−Ambient (RqJA, qJA)
187 (Note 6)
128 (Note 7)
°C/W
Junction−to−Lead (psi−JL8, YJL8)
30 (Note 8)
30 (Note 9)
°C/W
Junction−to−Ambient (RqJA, qJA)
122 (Note 8)
84 (Note 9)
°C/W
Parameter
SOIC−8
SOIC−14
6.
7.
8.
9.
1 oz copper, 53 mm2 coper area, 0.062″ thick FR4.
1 oz copper, 716 mm2 coper area, 0.062″ thick FR4.
1 oz copper, 94 mm2 coper area, 0.062″ thick FR4.
1 oz copper, 767 mm2 coper area, 0.062″ thick FR4.
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5
NCV7356
ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
VBATuv
−
3.5
−
4.8
V
Not High Speed Mode
−
5.0
6.0
mA
High Speed Mode
−
−
8.0
GENERAL
Undervoltage Lock Out
Supply Current, Recessive,
All Active Modes
IBATN
VBAT = 18 V,
TxD Open
Normal Mode Supply Current,
Dominant
IBATN
(Note 11)
VBAT = 27 V, MODE0 = MODE1 = H,
TxD = L, RL = 200 W
−
30
35
mA
High−Speed Mode Supply Current,
Dominant
IBATN
(Note 11)
VBAT = 16 V, MODE0 = H, MODE1 = L,
TxD = L, RL = 75 W
−
70
75
mA
Wake−Up Mode Supply Current,
Dominant
IBATW
(Note 11)
VBAT = 27 V,
MODE0 = L, MODE1 = H,
TxD = L, RL = 200 W
−
60
75
mA
IBATS
VBAT = 13 V, TA = 85°C,
TxD, RxD, MODE0,
MODE1 Open
−
30
60
mA
Thermal Shutdown (Note 11)
TSD
−
155
−
180
°C
Thermal Recovery (Note 11)
TREC
−
126
−
150
°C
Bus Output Voltage
Voh
RL > 200 W, Normal Mode
6.0 V < VBAT < 27 V
4.4
−
5.1
V
Bus Output Voltage
Low Battery
Voh
RL > 200 W, Normal High−Speed Mode
5.0 V < VBAT < 6.0 V
3.4
−
5.1
V
Bus Output Voltage
High−Speed Mode
Voh
RL > 75 W, High−Speed Mode
8.0 V < VBAT < 16 V
4.2
−
5.1
V
HV Fixed Wake−Up
Output High Voltage
VohWuFix
Wake−Up Mode, RL > 200 W,
11.4 V < VBAT < 27 V
9.9
−
12.5
V
HV Offset Wake−Up
Output High Voltage
VohWuOffset
Wake−Up Mode, RL > 200 W,
5.0 V < VBAT < 11.4 V
VBAT –1.5
−
VBAT
V
Vol
Recessive State or Sleep Mode,
RL = 6.5 kW
−0.20
−
0.20
V
−ICAN_SHORT
VCANH = 0 V, VBAT = 27 V, TxD = 0 V
50
−
350
mA
Bus Leakage Current
During Loss of Ground
ILKN_CAN
(Note 12)
Loss of Ground, VCANH = 0 V
−50
−
10
mA
Bus Leakage Current, Bus Positive
ILKP_CAN
TxD High
−10
−
10
mA
Vih
Normal, High−Speed Mode, HVWU
6.0 v VBAT v 27 V
2.0
2.1
2.2
V
Vihlb
Normal, VBAT = 5.0 V to 6.0 V
1.6
1.7
2.2
V
Fixed Wake−Up from Sleep
Input High Voltage Threshold
VihWuFix
(Note 11)
Sleep Mode, VBAT > 10.9 V
6.6
−
7.9
V
Offset Wake−Up from Sleep
Input High Voltage Threshold
VihWuOffset
(Note 11)
Sleep Mode
VBAT −4.3
−
VBAT −3.25
V
Voltage on Switched Ground Pin
VLOAD_1mA
ILOAD = 1.0 mA
−
−
0.1
V
Voltage on Switched Ground Pin
VLOAD
ILOAD = 5.0 mA
−
−
0.5
V
Voltage on Switched Ground Pin
VLOAD_LOB
ILOAD = 7.0 mA, VBAT = 0 V
−
−
1.0
V
Load Resistance During Loss of
Battery
RLOAD_LOB
VBAT = 0
RL −10%
−
RL +35%
W
Sleep Mode Supply Current (Note 10)
CANH
Recessive State
Output Voltage
Bus Short Circuit Current
Bus Input Threshold
Bus Input Threshold Low Battery
LOAD
10. Characterization data supports IBATS < 65 mA with conditions VBAT = 18 V, TA = 125°C
11. Thresholds not tested in production, guaranteed by design.
12. Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD.
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6
NCV7356
ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
High Level Input Voltage
Vih
6.0 < VBAT < 27 V
2.0
−
−
V
Low Level Input Voltage
Vil
6.0 < VBAT < 27 V
−
−
0.8
V
−IIL_TXD
TxD = L, MODE0 and 1 = H
5.0 < VBAT < 27 V
10
−
50
mA
10
−
50
kW
TXD, MODE0, MODE1
TxD Pullup Current
MODE0 and 1 Pulldown Resistor
RMODE_pd
RXD
Low Level Output Voltage
Vol_rxd
IRxD = 2.0 mA
−
−
0.4
V
High Level Output Leakage
Iih_rxd
VRxD = 5.0 V
−10
−
10
mA
Irxd
VRxD = 5.0 V
−
−
70
mA
Voh_INH
IINH = −180 mA
VBAT −0.8
VBAT −0.5
VBAT
V
IINH_lk
MODE0 = MODE1 = L, INH = 0 V
−5.0
−
5.0
mA
RxD Output Current
INH (14 Pin Package Only)
High Level Output Voltage
Leakage Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
35
30
30
VBAT, SUPPLY CURRENT
35
25
20
15
10
25
20
15
10
5
5
0
5
10
15
VBAT
20
0
−40
25
VBAT = 27 V
−20
Figure 3. Normal Mode Supply Current
Dominant vs. VBAT
SLEEP MODE SUPPLY CURRENT (mA)
VBAT, SUPPLY CURRENT
TYPICAL CHARACTERISTICS
0
20
40
60
80
TEMPERATURE (°C)
Figure 4. Normal Mode Supply Current
Dominant vs. Temperature
60
50
40
30
20
10
0
−40
−20
0
100
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 5. Sleep Mode Supply Current vs. Temperature
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7
120
NCV7356
TIMING MEASUREMENT LOAD CONDITIONS
Normal and High Voltage Wake−Up Mode
min load / min tau
3.3 kW / 540 pF
min load / max tau
3.3 kW / 1.2 nF
max load / min tau
200 W / 5.0 nF
max load / max tau
200 W / 20 nF
High−Speed Mode
Additional 140 W tool resistance
to ground in parallel
Additional 120 W tool resistance
to ground in parallel
ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.)
AC CHARACTERISTICS (See Figures 6, 7, and 8)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
tTr
Min and Max Loads per Timing
Measurement Load Conditions
2.0
−
6.3
ms
tTWUr
Min and Max Loads per Timing
Measurement Load Conditions
2.0
−
18
ms
tTf
Min and Max Loads per Timing
Measurement Load Conditions
1.8
−
10
ms
tTWU1f
Min and Max Loads per Timing
Measurement Load Conditions
3.0
−
13.7
ms
Transmit Delay in High−Speed Mode,
Bus Rising Edge (Notes 13, 18)
tTHSr
Min and Max Loads per Timing
Measurement Load Conditions
0.1
−
1.5
ms
Transmit Delay in High−Speed Mode,
Bus Falling Edge (Notes 17, 19)
tTHSf
Min and Max Loads per Timing
Measurement Load Conditions
0.04
−
3.0
ms
tDR
CANH High to Low Transition
0.3
−
1.0
ms
Transmit Delay in Normal and Wake−Up Mode,
Bus Rising Edge (Notes 13, 14)
Transmit Delay in Wake−Up Mode to VihWU,
Bus Rising Edge (Notes 13, 15)
Transmit Delay in Normal Mode,
Bus Falling Edge (Notes 16, 17)
Transmit Delay in Wake−Up Mode,
Bus Falling Edge (Notes 16, 17)
Receive Delay, All Active Modes (Note 20)
tRD
CANH Low to High Transition
0.3
−
1.0
ms
Input Minimum Pulse Length,
All Active Modes (Note 18)
tmpDR
tmpRD
CANH High to Low Transition
CANH Low to High Transition
0.1
0.1
−
−
1.0
1.0
ms
Wake−Up Filter Time Delay
tWUF
See Figure 7
10
−
70
ms
trb
See Figure 8
0.5
−
6.0
ms
Normal and High−Speed Mode
−
17
−
ms
Wake−Up Mode
−
17
−
ms
Receive Delay, All Active Modes (Note 20)
Receive Blanking Time, After TxD L−H Transition
TxD Timeout Reaction Time
ttout
TxD Timeout Reaction Time
ttoutwu
Delay from Normal to High−Speed and
High Voltage Wake−Up Mode
tdnhs
−
−
−
30
ms
Delay from High−Speed and High Voltage
Wake−Up to Normal Mode
tdhsn
−
−
−
30
ms
Delay from Normal to Standby Mode
Delay from Sleep to Normal Mode
Delay from Sleep to High Voltage Mode
Delay from Standby to Sleep Mode (Note 21)
tdsby
VBAT = 6.0 V to 27 V
−
−
500
ms
tdsnwu
VBAT = 6.0 V to 27 V
−
−
50
ms
tdshv
VBAT = 6.0 V to 27 V
−
−
50
ms
tdsleep
VBAT = 6.0 V to 27 V
100
250
500
ms
13. Minimum signal delay time is measured from the TxD voltage threshold to CANH = 1.0 V. t load should be min per the Timing Measurement
Load Conditions table.
14. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. t load
should be max per the Timing Measurement Load Conditions table.
15. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 9.2 V. Vihwumax = Vihwufix,
max + Vgoff = 7.9 V + 1.3 V = 9.2 V. t load should be max per the Timing Measurement Load Conditions table.
16. Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. t load
should be min per the Timing Measurement Load Conditions table.
17. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 1 V. t load should be max per the Timing Measurement
Load Conditions table.
18. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. t load should be max per the Timing Measurement
Load Conditions table.
19. Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. t load should be min per the Timing Measurement
Load Conditions table.
20. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising
(Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising
and falling edges is 50 V/ms. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V.
For HVWU mode testing the high level on bus is VBAT − 2 V. Relaxation of this non−critical parameter from 0.15 ms to 0.10 ms may be addressed
in future revisions of GMW3089.
21. Tested on 14 Pin package only.
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8
NCV7356
BUS LOADING REQUIREMENTS
Characteristic
Number of System Nodes
Network Distance Between Any Two ECU Nodes
Symbol
Min
Typ
Max
Unit
−
2
−
32
−
Bus Length
−
−
60
m
Node Series Inductor Resistance (If required)
Rind
−
−
3.5
W
Ground Offset Voltage
Vgoff
−
−
1.3
V
Vgofflowbat
−
0.1 x VBAT
0.7
V
Device Capacitance (Unit Load)
Cul
135
150
300
pF
Network Total Capacitance
Ctl
396
−
19000
pF
Device Resistance (Unit Load)
Rul
6435
6490
6565
W
Device Resistance (Min Load)
Rmin
2000
−
−
W
Rtl
200
−
4596
W
Network Time Constant (Note 22)
t
1.0
−
4.0
ms
Network Time Constant in High−Speed Mode
t
−
−
1.5
ms
Rload
75
−
135
W
Ground Offset Voltage, Low Battery
Network Total Resistance
High−Speed Mode Network Resistance to GND
22. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum
value is selected to ensure proper communication modes. Not all combinations of R and C are possible.
TIMING DIAGRAMS
VTxD
50%
t
tTr
tTf
VCANH
t
tRD
tDR
VRxD
50%
t
Figure 6. Input/Output Timing
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9
NCV7356
TIMING DIAGRAMS
VCANH
Vih + Vgoff
t
tWU
tWU
tWUF
VRxD
wake−up
interrupt
tWU < tWUF
t
Figure 7. Wake−Up Filter Time Delay
VTxD
50%
t
VCANH
Vih
t
VRxD
50%
t
tRB
Figure 8. Receive Blanking Time
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NCV7356
FUNCTIONAL DESCRIPTION
TxD Input Pin
disabled in this mode. Bus transmitter drive circuits for
those nodes which are required to communicate in
high−speed mode are able to drive reduced bus resistance
in this mode.
TxD Polarity
• TxD = logic 1 (or floating) on this pin produces an
undriven or recessive bus state (low bus voltage)
• TxD = logic 0 on this pin produces either a bus normal
High Voltage Wake−Up Mode
or a bus high voltage dominant state depending on the
transceiver mode state (high bus voltage)
If the TxD pin is driven to a logic low state while the sleep
mode (Mode 0 = 0 and Mode 1 = 0) is activated, the
transceiver can not drive the CANH pin to the dominant
state.
The transceiver provides an internal pull−up current on
the TxD pin (only in active modes [High−Speed Mode,
High Voltage Wake−Up, and Normal Mode]) which will
cause the transmitter to default to the bus recessive state
when TxD is not driven. The internal current source
circuitry limits the voltage pull−up level to be compatible
with 3.3 V logic. The TxD pull−up current source is not
active in Sleep Mode.
TxD input signals are standard CMOS logic levels.
This bus includes a selective node awake capability,
which allows normal communication to take place among
some nodes while leaving the other nodes in an undisturbed
sleep state. This is accomplished by controlling the signal
voltages such that all nodes must wake−up when they
receive a higher voltage message signal waveform. The
communication system communicates to the nodes
information as to which nodes are to stay operational
(awake) and which nodes are to put themselves into a non
communicating low power “sleep” state. Communication
at the lower, normal voltage levels shall not disturb the
sleeping nodes.
Normal Mode
Transmission bit rate in normal communication is
33 Kbits/s. In normal transmission mode the NCV7356
supports controlled waveform rise and overshoot times.
Waveform trailing edge control is required to assure that
high frequency components are minimized at the
beginning of the downward voltage slope. The remaining
fall time occurs after the bus is inactive with drivers off and
is determined by the RC time constant of the total bus load.
Timeout Feature
In case of a faulty blocked dominant TxD input signal,
the CANH output is switched off automatically after the
specified TxD timeout reaction time to prevent a dominant
bus.
The transmission is continued by next TxD L to H
transition without delay.
RxD Output Pin
MODE0 and MODE1 Pins
Logic data as sensed on the single wire CAN bus.
The transceiver provides a weak internal pulldown
current on each of these pins which causes the transceiver
to default to sleep mode when they are not driven. The
mode input signals are standard CMOS logic level for
3.3 V and 5 V supply voltages. See Electrical
Characteristics table for timing limitations for mode
changes.
MODE0
MODE1
RxD Polarity
• RxD = logic 1 on this pin indicates a bus recessive
state (low bus voltage)
• RxD = logic 0 on this pin indicates a bus normal or
high voltage bus dominant state
RxD in Sleep Mode
RxD does not pass signals to the microprocessor while in
sleep mode until a valid wake−up bus voltage level is
received or the MODE0 and MODE 1 pins are not 0, 0
respectively. When the valid wake−up bus voltage signal
awakens the transceiver, the RxD pin signals an interrupt
(logic 0). If there is no mode change within 250 ms (typ),
the transceiver re−enters the sleep mode.
When not in sleep mode all valid bus signals will be sent
out on the RxD pin.
RxD will be placed in the undriven or off state when in
sleep mode.
Mode
L
L
Sleep Mode
H
L
High−Speed Mode
L
H
High Voltage Wake−Up
H
H
Normal Mode
Sleep Mode
Transceiver is in low power state, waiting for wake−up
via high voltage signal or by mode pins change to any state
other than 0,0. In this state, the CANH pin is not in the
dominant state regardless of the state of the TxD pin.
RxD Typical Load
Resistance: 2.7 kW
Capacitance: < 25 pF
High−Speed Mode
This mode allows high−speed download with bit rates up
to 100 Kbit/s. The output wave shapingaping circuit is
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11
NCV7356
mode and can operate higher 75 W loads for High−Speed
Mode. The minimum output driver capability is 50 mA, but
output shorts to ground can reach 350mA.
Normal CANH output voltages are between 4.4 V and
5.1 V. These amplitudes increase to between 9.9 V and 12.5 V
for selective system IC selection in Wake−Up Mode.
The CANH pin also acts as a bus read amplifier. The Bus
Wake−Up from Sleep Input Voltage Threshold is between
6.6 V and 7.9 V, but to maintain normal communication,
the threshold is 2.1 V.
Bus LOAD Pin
Bus LOAD Pin Description
The bus LOAD pin provides a network load impedance
program point for the CAN bus. The value of the resistor
between the CANH and LOAD pins can be adjusted to
provide adequate impedance for the bus loading
requirements as dictated by the Single Wire CAN
Specification (J2411).
The resistor between CANH and LOAD pins provides a
pull down impedance for the CANH pin. The CANH driver
is a pull−up amplifier with no sink capability.
The bus LOAD pin also provides the detection circuitry
for loss of ground detection to insure there are no loading
effects on the bus should the ground connection be lost to
the NCV7356 device. During a system loss of ground
event, CANH with the 6.49 kW resistor between CANH and
LOAD will affect the bus with only between −50 mA and
10 mA of current (Bus Leakage Current During Loss of
Ground).
Wave Shaping in Normal and High Voltage Wake−Up
Mode
Wave shaping is incorporated into the transmitter to
minimize EMI radiated emissions. An important
contributor to emissions is the rise and fall times during
output transitions at the “corners” of the voltage waveform.
The resultant waveform is one half of a sin wave of
frequency 50−65 kHz at the rising waveform edge and one
quarter of this sin wave at falling or trailing edge.
Resistor ground connection with internal open−on−loss−
of−ground protection
Wave Shaping in High−Speed Mode
Wave shaping control of the rising and falling waveform
edges are disabled during high−speed mode. EMI
emissions requirements are waived during this mode. The
waveform rise time in this mode is less than 1.0 ms.
When the ECU experiences a loss of ground condition,
this pin is switched to a high impedance state.
The ground connection through this pin is not interrupted
in any transceiver operating mode including the sleep
mode. The ground connection only is interrupted when
there is a valid loss of ground condition.
This pin provides the bus load resistor with a path to
ground which contributes less than 0.1 V to the bus offset
voltage when sinking the maximum current through one
unit load resistor. This path exists in all operating modes,
including the sleep mode.
The transceiver’s maximum bus leakage current
contribution to Vol from the LOAD pin when in a loss of
ground state is 50 mA over all operating temperatures and
3.5 < VBAT < 27 V.
Short Circuits
If the CAN BUS pin is shorted to ground for any duration
of time, the current is limited as specified in the Electrical
Characteristics Table until an overtemperature shutdown
circuit disables the output high side drive source transistor
preventing damage to the IC.
Loss of Ground
In case of a valid loss of ground condition, the LOAD pin
is switched into high impedance state. The CANH
transmission is continued until the undervoltage lock out
voltage threshold is detected.
VBAT Input Pin
Loss of Battery
Vehicle Battery Voltage
In case of loss of battery (VBAT = 0 or open) the
transceiver does not disturb bus communication. The
maximum reverse current into the power supply system
(VBAT) doesn’t exceed 500 mA.
The transceiver is fully operational as described in the
Electrical Characteristics Table over the range 6.0 V <
VBAT < 18 V as measured between the GND pin and the
VBAT pin.
For 5.0 V < VBat < 6.0 V, the bus operates in normal
mode with reduced dominant output voltage and reduced
receiver input voltage. High voltage wake−up is not
possible (dominant output voltage is the same as in normal
or high−speed mode).
The transceiver operates in normal mode when 18 V <
VBat < 27 V at 85°C for one minute.
INH Pin (14 pin package only)
The INH pin is a high−voltage highside switch used to
control the ECU’s regulated microcontroller power supply.
After power−on, the transceiver automatically enters an
intermediate standby mode, the INH output will go high
(up to VBAT) turning on the external voltage regulator. The
external regulator provides power to the ECU. If there is no
mode change within 250 ms (typ), the transceiver re−enters
the sleep mode and the INH output goes to logic 0
(floating).
When the transceiver has detected a valid wake−up
condition (bus HVWU traffic which exceeds the wake−up
filter time delay) the INH output will become high (up to
CAN BUS
Input/Output Pin
The CANH pin is composed of a pull−up amplifier (no
sink capability) for driving the single−wire CAN bus. It is
designed to drive a 200 W load when operating in normal
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12
NCV7356
VBAT) again and the same procedure starts as described
after power−on. In case of a mode change into any active
mode, the sleep timer is stopped and INH stays high (up to
VBAT). If the transceiver enters the sleep mode, INH goes
to logic 0 (floating) after 250 ms (typ) when no wake−up
signal is present.
HVWU Mode
MODE0
MODE1
low
high
MODE0/1 => High
High−Speed Mode
MODE0&1 => Low
MODE0
MODE1
high
low
VBATon
Normal Mode
MODE0
MODE1
high
high
MODE0/1 => High
(If VCC_ECU on)
VBAT standby
after 250 ms
−> no mode change
−> no valid wake−up
MODE0/1
RxD
CAN
low
high/low(1)
float
wake−up
request
from Bus
Sleep Mode
(1)
MODE0/1
CAN
low
float
low after HVWU, high after VBAT on & VCCECU present
Figure 9. State Diagram, 8 Pin Package
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13
NCV7356
HVWU Mode
MODE0
MODE1
INH
low
high
VBAT
MODE0/1 => High
High−Speed Mode
MODE0
MODE1
INH
high
low
VBAT
MODE0&1 => Low
VBATon
Normal Mode
MODE0
MODE1
INH
high
high
VBAT
MODE0/1 => High
(If VCC_ECU on)
VBAT standby
MODE0/1 INH
after 250 ms
−> no mode change
−> no valid wake−up
low
VBAT
RxD
CAN
high/low(1)
float
wake−up
request
from Bus
Sleep Mode
(1)
MODE0/1
INH/CAN
low
floating
low after HVWU, high after VBAT on & VCCECU present
Figure 10. State Diagram, 14 Pin Package
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14
NCV7356
MRA4004T3
*
VBAT
VBAT_ECU
+
Voltage Regulator
VBAT
+5 V
100 nF
ECU Connector to
Single Wire CAN Bus
100 pF
+
2.7 kW
VBAT
1k
5
47 mH
4
CAN Controller
RxD
7
CANH
NCV7356
MODE0
MODE1
TxD
6.49 kW
2
100 pF
3
6
LOAD
1
8
GND
*Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses)
Figure 11. Application Circuitry, 8 Pin Package
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15
ESD Protection −
NUP1105L
NCV7356
MRA4004T3
*
VBAT
VBAT_ECU
+
Voltage Regulator
INH
VBAT
+5 V
100 nF
ECU Connector to
Single Wire CAN Bus
100 pF
+
2.7 kW
VBAT
9
1k
10
47 mH
5
CAN Controller
RxD
12
CANH
NCV7356
MODE0
MODE1
TxD
6.49 kW
3
100 pF
4
11
LOAD
2
1, 7, 8, 14
GND
*Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses)
Figure 12. Application Circuitry, 14 Pin Package
www.onsemi.com
16
ESD Protection −
NUP1105L
NCV7356
SOIC−8 Thermal Information
Test Condition, Typical Value
Min Pad Board
(Note 23)
1, Pad Board
(Note 24)
Unit
Junction−to−Lead (psi−JL7, YJL8) or Pins 6−7
57
51
°C/W
Junction−to−Ambient (RqJA, qJA)
187
128
°C/W
Parameter
23. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4.
24. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4.
Package Construction
with and without Mold Compound
Various copper areas used
for heat spreading
Active Area (red)
Lead #1
Figure 13. Internal construction of the
package simulation.
Figure 14. Min pad is shown as the red traces.
1, pad includes the yellow area. Internal
construction is shown for later reference.
190
180
qJA (°C/W)
170
160
1.0 oz. Cu
150
140
130
2.0 oz. Cu
120
110
100
0
100
200
300
400
Copper Area
500
600
700
800
(mm2)
Figure 15. SOIC−8, qJA as a Function of the Pad Copper
Area Including Traces,
Board Material
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17
NCV7356
Table 1. SOIC−8 Thermal RC Network Models*
53 mm2
719 mm2
Copper Area
719 mm2
53 mm2
Cauer Network
Copper Area
Foster Network
C’s
C’s
Units
Tau
Tau
Units
5.86E−06
5.86E−06
W−s/C
1.00E−06
1.00E−06
sec
2.29E−05
2.29E−05
W−s/C
1.00E−05
1.00E−05
sec
6.98E−05
6.97E−05
W−s/C
1.00E−04
1.00E−04
sec
3.68E−04
3.68E−04
W−s/C
1.99E−04
1.99E−04
sec
3.75E−04
3.74E−04
W−s/C
1.00E−03
1.00E−03
sec
1.57E−03
1.56E−03
W−s/C
1.64E−02
1.64E−02
sec
2.05E−02
2.24E−02
W−s/C
5.60E−01
5.60E−01
sec
9.13E−02
7.35E−02
W−s/C
4.50E+00
4.50E+00
sec
2.64E−01
1.22E+00
W−s/C
7.61E+01
7.61E+01
sec
1.66E+01
9.74E+00
W−s/C
3.00E+01
3.00E+01
sec
R’s
R’s
R’s
R’s
0.22
0.22
C/W
1.30E−01
1.30E−01
C/W
0.50
0.50
C/W
2.82E−01
2.82E−01
C/W
1.30
1.30
C/W
8.91E−01
8.91E−01
C/W
1.80
1.79
C/W
0.17
0.18
C/W
0.95
0.96
C/W
1.88
1.88
C/W
7.43
7.37
C/W
7.15
7.24
C/W
31.19
31.59
C/W
19.80
16.27
C/W
59.97
47.70
C/W
30.1
54.7
C/W
75.79
28.63
C/W
14.1
23.3
C/W
4.41
6.15
C/W
109.0
21.3
C/W
*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network
are computed by the square root of time constant R(t) = 130 * sqrt(time(sec)). The constant is derived based on the active area of the device
with silicon and epoxy at the interface of the heat generation.
The Cauer networks generally have physical
significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Both Foster and Cauer networks can be easily implemented
using circuit simulating tools, whereas Foster networks
may be more easily implemented using mathematical tools
(for instance, in a spreadsheet program), according to the
following formula:
R(t) +
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18
n
−tńtaui Ǔ
Ri ǒ1−e
S
i+1
NCV7356
R1
Junction
R2
C1
R3
C2
Rn
Cn
C3
Ambient
(thermal ground)
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Figure 16. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC−product time constant; Amplitudes are the resistances
Ambient
(thermal ground)
Figure 17. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
1000
Cu Area = 53 mm2 1.0 oz.
Cu Area = 93 mm2 1.0 oz.
Rq (°C/W)
100
Cu Area = 719 mm2 1.0 oz.
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10
100
1000
Time (s)
Figure 18. SOIC−8 Single Pulse Heating Curve
1000
Rq (°C/W)
100 D = 0.50
0.20
0.10
10 0.05
0.02
1 0.01
0.1
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
Time (s)
Figure 19. SOIC−8 Thermal Duty Cycle Curves on 1, Spreader Test Board
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19
NCV7356
SOIC−14 Thermal Information
Test Condition, Typical Value
Min Pad Board
(Note 25)
1, Pad Board
(Note 26)
Unit
Junction−to−Lead (psi−JL8, YJL8)
30
30
°C/W
Junction−to−Ambient (RqJA, qJA)
122
84
°C/W
Parameter
25. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4.
26. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4.
Figure 21. Min pad is shown as the red traces.
1 inch pad includes the yellow area. Pin 1, 7, 8 and
14 are connected to flag internally to the package
and externally to the heat spreading area.
Figure 20. Internal construction of the package
simulation.
150
140
qJA (°C/W)
130
120
1.0 oz. Cu
110
100
Sim 1.0 oz.
Sim 2.0 oz.
2.0 oz. Cu
90
80
70
60
0
100
200
300
400
500
600
700
Copper Area (mm2)
Figure 22. SOIC−14, qJA as a Function of the Pad Copper Area Including Traces,
Board Material
www.onsemi.com
20
800
900
NCV7356
Table 2. SOIC−14 Thermal RC Network Models*
96 mm2
767 mm2
96 mm2
Copper Area
Cauer Network
767 mm2
Copper Area
Foster Network
C’s
C’s
Units
Tau
Tau
Units
3.12E−05
3.12E−05
W−s/C
1.00E−06
1.00E−06
sec
1.21E−04
1.21E−04
W−s/C
1.00E−05
1.00E−05
sec
3.53E−04
3.50E−04
W−s/C
1.00E−04
1.00E−04
sec
1.19E−03
1.19E−03
W−s/C
0.028
0.001
sec
4.86E−03
5.05E−03
W−s/C
0.001
0.009
sec
2.17E−02
7.16E−03
W−s/C
0.280
0.047
sec
8.94E−02
3.51E−02
W−s/C
2.016
0.875
sec
0.304
0.262
W−s/C
16.64
7.53
sec
1.71
2.43
W−s/C
59.47
68.4
sec
411
W−s/C
92.221
sec
R’s
R’s
R’s
R’s
0.041
0.041
°C/W
2.44E−02
2.44E−02
°C/W
0.095
0.279
0.096
°C/W
5.28E−02
5.28E−02
°C/W
0.281
°C/W
1.67E−01
1.67E−01
°C/W
1.154
0.995
°C/W
3.5
0.7
°C/W
5.621
6.351
°C/W
0.7
0.1
°C/W
13.180
1.910
°C/W
8.7
5.8
°C/W
23.823
21.397
°C/W
15.9
16.4
°C/W
53.332
27.150
°C/W
31.9
27.1
°C/W
24.794
25.276
°C/W
61.3
29.0
°C/W
0.218
°C/W
4.3
°C/W
*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network
are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device
with silicon and epoxy at the interface of the heat generation.
The Cauer networks generally have physical
significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Both Foster and Cauer networks can be easily implemented
R1
Junction
C1
R2
C2
using circuit simulating tools, whereas Foster networks
may be more easily implemented using mathematical tools
(for instance, in a spreadsheet program), according to the
following formula:
R(t) +
n
−tńtaui Ǔ
Ri ǒ1−e
S
i+1
R3
Rn
Cn
C3
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 23. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC−product time constant; Amplitudes are the resistances
Figure 24. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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21
Ambient
(thermal ground)
NCV7356
1000
Cu Area = 96 mm2 1.0 oz.
Rq (°C/W)
100
Cu Area = 767 mm2 1.0 oz.
10
Cu Area = 767 mm2 1.0 oz. 1S2P
1
0.1
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
10
100
1000
Time (s)
Figure 25. SOIC−14 Single Pulse Heating
1000
D = 0.50
Rq (°C/W)
100
0.20
0.10
0.05
10
0.01
1
Cu Area = 717 mm2 1.0 oz.
0.1
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
PULSE DURATION (sec)
Figure 26. SOIC−14 Thermal Duty Cycle Curves on 1, Spreader Test Board
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22
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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