NCV7356_07

NCV7356 Single Wire CAN Transceiver The NCV7356 is a physical layer device for a single wire data link capable of operating with various Carrier Sense Multiple Access with Collision Resolution (CSMA/CR) protocols such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or dedicated logic devices which use the network. The network shall be able to operate in either the normal data rate mode or a high−speed data download mode for assembly line and service data transfer operations. The high−speed mode is only intended to be operational when the bus is attached to an off−board service node. This node shall provide temporary bus electrical loads which facilitate higher speed operation. Such temporary loads should be removed when not performing download operations. The bit rate for normal communications is typically 33 kbit/s, for high−speed transmissions like described above a typical bit rate of 83 kbit/s is recommended. The NCV7356 is designed in accordance to the Single Wire CAN Physical Layer Specification GMW3089 V2.4 and supports many additional features like undervoltage lockout, timeout for faulty blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current. Features http://onsemi.com MARKING DIAGRAMS 8 1 SOIC−8 D SUFFIX CASE 751 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package NCV7356G AWLYWW 8 V7356 ALYW G 1 PIN CONNECTIONS TxD 1 8 GND 7 CANH 6 LOAD 5 VBAT (Top View) GND 1 TxD 2 MODE0 3 MODE1 4 RxD 5 NC 6 GND 7 (Top View) 14 GND 13 NC 12 CANH 11 LOAD 10 VBAT 9 8 INH GND • • • • • • • • • • • • • • • • • • • • MODE0 2 MODE1 3 RxD 4 Fully Compatible with J2411 Single Wire CAN Specification 60 mA (max) Sleep Mode Current Operating Voltage Range 5.0 to 27 V Up to 100 kbps High−Speed Transmission Mode Up to 40 kbps Bus Speed Selective BUS Wake−Up Logic Inputs Compatible with 3.3 V and 5 V Supply Systems Control Pin for External Voltage Regulators (14 Pin Package Only) Standby to Sleep Mode Timeout Low RFI Due to Output Wave Shaping Fully Integrated Receiver Filter Bus Terminals Short−Circuit and Transient Proof Loss of Ground Protection Protection Against Load Dump, Jump Start Thermal Overload and Short Circuit Protection ESD Protection of 4.0 kV on CANH Pin (2.0 kV on Any Other Pin) Undervoltage Lock Out Bus Dominant Timeout Feature NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes Pb−Free Packages are Available ORDERING INFORMATION Device NCV7356D1G Package Shipping† 98 Units / Rail 2500 Tape & Reel 55 Units / Rail 55 Units / Rail 2500 Tape & Reel SOIC−8 (Pb−Free) NCV7356D1R2G SOIC−8 (Pb−Free) NCV7356D2 NCV7356D2G NCV7356D2R2 NCV7356D2R2G SOIC−14 SOIC−14 (Pb−Free) SOIC−14 SOIC−14 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NCV7356/D © Semiconductor Components Industries, LLC, 2007 1 January, 2007 − Rev. 5 NCV7356 VBAT NCV7356 5 V Supply and References Biasing and VBAT Monitor Reverse Current Protection RC−OSC Wave Shaping CAN Driver TxD Time Out CANH Feedback Loop Input Filter MODE0 LOAD MODE CONTROL Receive Comparator Loss of Ground Detection MODE1 RxD RxD Blanking Time Filter Reverse Current Protection GND Figure 1. 8−Pin Package Block Diagram http://onsemi.com 2 NCV7356 VBAT INH NCV7356 5 V Supply and References Biasing and VBAT Monitor Reverse Current Protection RC−OSC Wave Shaping CAN Driver TxD Time Out CANH Feedback Loop Input Filter MODE0 LOAD MODE CONTROL Receive Comparator Loss of Ground Detection MODE1 RxD RxD Blanking Time Filter Reverse Current Protection GND Figure 2. 14−Pin Package Block Diagram http://onsemi.com 3 NCV7356 PACKAGE PIN DESCRIPTION SOIC−8 1 2 3 4 5 6 7 8 − − SOIC−14 2 3 4 5 10 11 12 1, 7, 8, 14 6, 13 9 Symbol TxD MODE0 MODE1 RxD VBAT LOAD CANH GND NC INH Description Transmit data from microprocessor to CAN. Operating mode select input 0. Operating mode select input 1. Receive data from CAN to microprocessor. Battery input voltage. Resistor load (loss of ground detection low side switch). Single wire CAN bus pin. Ground No Connection (Note 1) Control pin for external voltage regulator (high voltage high side switch) (14 pin package only) 1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package. http://onsemi.com 4 NCV7356 Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings given in the table below are limiting values that do not lead to a MAXIMUM RATINGS Rating Supply Voltage, Normal Operation Short−T erm Supply Voltage, Transient Symbol VBAT VBAT.LD Condition − Load Dump; t < 500 ms Jump Start; t < 1.0 min Transient Supply Voltage Transient Supply Voltage Transient Supply Voltage CANH Voltage VBAT.TR1 VBAT.TR2 VBAT.TR3 VCANH ISO 7637/1 Pulse 1 (Note 2) ISO 7637/1 Pulses 2 (Note 2) ISO 7637/1 Pulses 3A, 3B VBAT < 27 V VBAT = 0 V Transient Bus Voltage Transient Bus Voltage Transient Bus Voltage DC Voltage on Pin LOAD DC Voltage on Pins TxD, MODE1, MODE0, RxD ESD Capability of CANH VCANHTR1 VCANHTR2 VCANHTR3 VLOAD VDC VESDBUS ISO 7637/1 Pulse 1 (Note 3) ISO 7637/1 Pulses 2 (Note 3) ISO 7637/1 Pulses 3A, 3B (Note 3) Via RT > 2.0 kW − Human Body Model (with respect to VBAT and GND) Eq. to Discharge 100 pF with 1.5 kW Human Body Model Eq. to Discharge 100 pF with 1.5 kW − − − 60 s − 150 s above 183°C 60 s − 150 s above 217°C Min −0.3 − − −50 − −200 −20 −40 −50 − −200 −40 −0.3 −4000 40 − 100 200 40 7.0 4000 V V V V V V Max 18 40 27 − 100 200 Unit V V (peak) V V V V V permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. ESD Capability of Any Other Pin Maximum Latchup Free Current at Any Pin Storage Temperature Junction Temperature Lead Temperature Soldering Reflow: (SMD styles only) SOIC−14 SOIC−8 VESD ILATCH TSTG TJ Tsld −2000 −500 −55 −40 − − 2000 500 150 150 240 peak 260 peak V mA °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 mF blocking capacitor. 3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF. 4. ESD measured per Q100−002 (EIA/JESD22−A114−A). TYPICAL THERMAL CHARACTERISTICS Test Condition, Typical Value Parameter SOIC−8 Junction−to−Lead (psi−JL7, YJL8) or Pins 6−7 Junction−to−Ambient (RqJA, qJA) SOIC−14 Junction−to−Lead (psi−JL8, YJL8) Junction−to−Ambient (RqJA, qJA) 5. 6. 7. 8. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4. 30 (Note 7) 122 (Note 7) 30 (Note 8) 84 (Note 8) °C/W °C/W 57 (Note 5) 187 (Note 5) 51 (Note 6) 128 (Note 6) °C/W °C/W Min Pad Board 1, Pad Board Unit http://onsemi.com 5 NCV7356 ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic GENERAL Undervoltage Lock Out Supply Current, Recessive, All Active Modes Normal Mode Supply Current, Dominant High−Speed Mode Supply Current, Dominant Wake−Up Mode Supply Current, Dominant Sleep Mode Supply Current (Note 9) VBATuv IBATN VBAT = 18 V, TxD Open − Not High Speed Mode High Speed Mode 3.5 − − − − − − 5.0 − 30 70 60 4.8 6.0 8.0 35 75 75 mA mA mA V mA Symbol Condition Min Typ Max Unit IBATN (Note 10) IBATN (Note 10) IBATW (Note 10) IBATS VBAT = 27 V, MODE0 = MODE1 = H, TxD = L, Rload = 200 W VBAT = 16 V, MODE0 = H, MODE1 = L, TxD = L, Rload = 75 W VBAT = 27 V, MODE0 = L, MODE1 = H, TxD = L, Rload = 200 W VBAT = 13 V, TA = 85°C, TxD, RxD, MODE0, MODE1 Open − − − 30 60 mA Thermal Shutdown (Note 10) Thermal Recovery (Note 10) CANH Bus Output Voltage Bus Output Voltage Low Battery Bus Output Voltage High−Speed Mode HV Fixed Wake−Up Output High Voltage HV Offset Wake−Up Output High Voltage Recessive State Output Voltage Bus Short Circuit Current Bus Leakage Current During Loss of Ground Bus Leakage Current, Bus Positive Bus Input Threshold Bus Input Threshold Low Battery Fixed Wake−Up from Sleep Input High Voltage Threshold Offset Wake−Up from Sleep Input High Voltage Threshold LOAD Voltage on Switched Ground Pin Voltage on Switched Ground Pin Voltage on Switched Ground Pin Load Resistance During Loss of Battery TSD TREC 155 126 − − 180 150 °C °C Voh Voh Voh VohWuFix VohWuOffset Vol −ICAN_SHORT ILKN_CAN (Note 11) ILKP_CAN Vih Vihlb VihWuFix (Note 10) VihWuOffset (Note 10) RL > 200 W, Normal Mode 6.0 V < VBAT < 27 V RL > 200 W, Normal High−Speed Mode 5.0 V < VBAT < 6.0 V RL > 75 W, High−Speed Mode 8.0 V < VBAT < 16 V Wake−Up Mode, RL > 200 W, 11.4 V < VBAT < 27 V Wake−Up Mode, RL > 200 W, 5.0 V < VBAT < 11.4 V Recessive State or Sleep Mode, Rload = 6.5 kW VCANH = 0 V, VBAT = 27 V, TxD = 0 V Loss of Ground, VCANH = 0 V TxD High Normal, High−Speed Mode, HVWU 6.0 v VBAT v 27 V Normal, VBAT = 5.0 V to 6.0 V Sleep Mode, VBAT > 10.9 V Sleep Mode 4.4 3.4 4.2 9.9 VBAT –1.5 −0.20 50 −50 −10 2.0 1.6 6.6 VBAT −4.3 − − − − − − − − − 2.1 1.7 − − 5.1 5.1 5.1 12.5 VBAT 0.20 350 10 10 2.2 2.2 7.9 VBAT −3.25 V V V V V V mA mA mA V V V V VLOAD_1mA VLOAD VLOAD_LOB RLOAD_LOB ILOAD = 1.0 mA ILOAD = 5.0 mA ILOAD = 7.0 mA, VBAT = 0 V VBAT = 0 − − − RLOAD −10% − − − − 0.1 0.5 1.0 RLOAD +35% V V V W 9. Characterization data supports IBATS < 65 mA with conditions VBAT = 18 V, TA = 125°C 10. Thresholds not tested in production, guaranteed by design. 11. Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD. http://onsemi.com 6 NCV7356 ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.) Characteristic TXD, MODE0, MODE1 High Level Input Voltage Low Level Input Voltage TxD Pullup Current MODE0 and 1 Pulldown Resistor RXD Low Level Output Voltage High Level Output Leakage RxD Output Current INH (14 Pin Package Only) High Level Output Voltage Leakage Current Voh_INH IINH_lk IINH = −180 mA MODE0 = MODE1 = L, INH = 0 V VBAT −0.8 −5.0 VBAT −0.5 − VBAT 5.0 V mA Vol_rxd Iih_rxd Irxd IRxD = 2.0 mA VRxD = 5.0 V VRxD = 5.0 V − −10 − − − − 0.4 10 70 V mA mA Vih Vil −IIL_TXD RMODE_pd 6.0 < VBAT < 27 V 6.0 < VBAT < 27 V TxD = L, MODE0 and 1 = H 5.0 < VBAT < 27 V 2.0 − 10 10 − − − − − 0.8 50 50 V V mA kW Symbol Condition Min Typ Max Unit http://onsemi.com 7 NCV7356 TIMING MEASUREMENT LOAD CONDITIONS Normal and High Voltage Wake−Up Mode min load / min tau min load / max tau max load / min tau max load / max tau 3.3 kW / 540 pF 3.3 kW / 1.2 nF 200 W / 5.0 nF 200 W / 20 nF High−Speed Mode Additional 140 W tool resistance to ground in parallel Additional 120 W tool resistance to ground in parallel ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.) AC CHARACTERISTICS (See Figures 3, 4, and 5) Characteristic Transmit Delay in Normal and Wake−Up Mode, Bus Rising Edge (Notes 12, 13) Transmit Delay in Wake−Up Mode to VihWU, Bus Rising Edge (Notes 12, 14) Transmit Delay in Normal Mode, Bus Falling Edge (Notes 12, 13) Transmit Delay in Wake−Up Mode, Bus Falling Edge (Notes 12, 13) Transmit Delay in High−Speed Mode, Bus Rising Edge (Note 15) Transmit Delay in High−Speed Mode, Bus Falling Edge (Note 16) Receive Delay, All Active Modes (Note 17) Receive Delay, All Active Modes (Note 17) Input Minimum Pulse Length, All Active Modes (Note 17) Wake−Up Filter Time Delay Receive Blanking Time, After TxD L−H Transition TxD Timeout Reaction Time TxD Timeout Reaction Time Delay from Normal to High−Speed and High Voltage Wake−Up Mode Delay from High−Speed and High Voltage Wake−Up to Normal Mode Delay from Normal to Standby Mode Delay from Sleep to Normal Mode Delay from Standby to Sleep Mode (Note 18) Symbol tTr tTWUr tTf tTWU1f tTHSr tTHSf tDR tRD tmpDR tmpRD tWUF trb ttout ttoutwu tdnhs tdhsn tdsby tdsnwu tdsleep Condition Min and Max Loads per Timing Measurement Load Conditions Min and Max Loads per Timing Measurement Load Conditions Min and Max Loads per Timing Measurement Load Conditions Min and Max Loads per Timing Measurement Load Conditions Min and Max Loads per Timing Measurement Load Conditions Min and Max Loads per Timing Measurement Load Conditions CANH High to Low Transition CANH Low to High Transition CANH High to Low Transition CANH Low to High Transition See Figure 4 See Figure 5 Normal and High−Speed Mode Wake−Up Mode − − VBAT = 6.0 V to 27 V VBAT = 6.0 V to 27 V VBAT = 6.0 V to 27 V Min 2.0 2.0 1.8 3.0 0.1 0.04 0.3 0.3 0.1 0.1 10 0.5 − − − − − − 100 Typ − − − − − − − − − − − − 17 17 − − − − 250 Max 6.3 18 10 13.7 1.5 3.0 1.0 1.0 1.0 1.0 70 6.0 − − 30 30 500 50 500 Unit ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms 12. Minimum t loads measured from measured TxD voltage threshold to CANH = 1.0 V. 13. Maximum t load measured from measured TxD voltage threshold to CANH = 3.5 V @ VBAT = 27 V, CANH = 2.8 V @ VBAT = 5.0 V., CANH Threshold = VihMAX + Vgoff. 14. Maximum t load measured from measured TxD voltage threshold to CANH = 9.2 V. VihWUMAX = VihWUFIX, MAX + Vgoff = 7.9 V + 1.3 V = 9.2 V. 15. Minimum t loads measured from measured TxD voltage threshold to CANH = 1.0 V. Maximum t load measured from measured TxD voltage threshold to CANH = 3.5 V VihMAX + Vgoff = 2.2 V + 1.3 V = 3.5 V. 16. Minimum t loads measured from measured TxD voltage threshold to CANH = 3.5 V. VihMAX + Vgoff = 2.2 V + 1.3 V = 3.5 V. Maximum t loads measured from measured TxD voltage threshold to CANH = 1.0 V. 17. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising (Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising and falling edges is 50 V/ms. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V. For HVWU mode testing the high level on bus is VBAT − 2 V. Relaxation of this non−critical parameter from 0.15 ms to 0.10 ms may be addressed in future revisions of GMW3089. 18. Tested on 14 Pin package only. http://onsemi.com 8 NCV7356 BUS LOADING REQUIREMENTS Characteristic Number of System Nodes Network Distance Between Any Two ECU Nodes Node Series Inductor Resistance (If required) Ground Offset Voltage Ground Offset Voltage, Low Battery Device Capacitance (Unit Load) Network Total Capacitance Device Resistance (Unit Load) Device Resistance (Min Load) Network Total Resistance Network Time Constant (Note 19) Network Time Constant in High−Speed Mode High−Speed Mode Network Resistance to GND Symbol − Bus Length Rind Vgoff Vgofflowbat Cul Ctl Rul Rmin Rtl t t Rload Min 2 − − − − 135 396 6435 2000 200 1.0 − 75 Typ − − − − Max 32 60 3.5 1.3 0.7 300 19000 6565 − 4596 4.0 1.5 135 Unit − m W V V pF pF W W W ms ms W 0.1 x VBAT 150 − 6490 − − − − − 19. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum value is selected to ensure proper communication modes. Not all combinations of R and C are possible. TIMING DIAGRAMS VTxD 50% t tT VCANH Vihmax + Vgoffmax 1V t tR tD VRxD 50% t tF tDR Figure 3. Input/Output Timing http://onsemi.com 9 NCV7356 TIMING DIAGRAMS VCANH Vih + Vgoff t tWU tWU tWUF VRxD tWU < tWUF wake−up interrupt t Figure 4. Wake−Up Filter Time Delay VTxD 50% t VCANH Vih t VRxD 50% t tRB Figure 5. Receive Blanking Time http://onsemi.com 10 NCV7356 FUNCTIONAL DESCRIPTION TxD Input Pin TxD Polarity High Voltage Wake−Up Mode • TxD = logic 1 (or floating) on this pin produces an • TxD = logic 0 on this pin produces either a bus normal or a bus high voltage dominant state depending on the transceiver mode state (high bus voltage) If the TxD pin is driven to a logic low state while the sleep mode (Mode 0 = 0 and Mode 1 = 0) is activated, the transceiver can not drive the CANH pin to the dominant state. The transceiver provides an internal pullup current on the TxD pin which will cause the transmitter to default to the bus recessive state when TxD is not driven. TxD input signals are standard CMOS logic levels. Timeout Feature undriven or recessive bus state (low bus voltage) This bus includes a selective node awake capability, which allows normal communication to take place among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by controlling the signal voltages such that all nodes must wake−up when they receive a higher voltage message signal waveform. The communication system communicates to the nodes information as to which nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low power “sleep” state. Communication at the lower, normal voltage levels shall not disturb the sleeping nodes. Normal Mode In case of a faulty blocked dominant TxD input signal, the CANH output is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission is continued by next TxD L to H transition without delay. MODE0 and MODE1 Pins Transmission bit rate in normal communication is 33 Kbits/s. In normal transmission mode the NCV7356 supports controlled waveform rise and overshoot times. Waveform trailing edge control is required to assure that high frequency components are minimized at the beginning of the downward voltage slope. The remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time constant of the total bus load. RxD Output Pin The transceiver provides a weak internal pulldown current on each of these pins which causes the transceiver to default to sleep mode when they are not driven. The mode input signals are standard CMOS logic level for 3.3 V and 5 V supply voltages. MODE0 L H L H MODE1 L L H H Sleep Mode High−Speed Mode High Voltage Wake−Up Normal Mode Mode Logic data as sensed on the single wire CAN bus. RxD Polarity • RxD = logic 1 on this pin indicates a bus recessive • RxD = logic 0 on this pin indicates a bus normal or high voltage bus dominant state RxD in Sleep Mode state (low bus voltage) Sleep Mode Transceiver is in low power state, waiting for wake−up via high voltage signal or by mode pins change to any state other than 0,0. In this state, the CANH pin is not in the dominant state regardless of the state of the TxD pin. High−Speed Mode RxD does not pass signals to the microprocessor while in sleep mode until a valid wake−up bus voltage level is received or the MODE0 and MODE 1 pins are not 0, 0 respectively. When the valid wake−up bus voltage signal awakens the transceiver, the RxD pin signals an interrupt (logic 0). If there is no mode change within 250 ms (typ), the transceiver re−enters the sleep mode. When not in sleep mode all valid bus signals will be sent out on the RxD pin. RxD will be placed in the undriven or off state when in sleep mode. RxD Typical Load This mode allows high−speed download with bit rates up to 100 Kbit/s. The output wave shapingaping circuit is disabled in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in high−speed mode are able to drive reduced bus resistance in this mode. Resistance: 2.7 kW Capacitance: < 25 pF http://onsemi.com 11 NCV7356 Bus LOAD Pin Resistor ground connection with internal open−on−loss− of−ground protection Wave Shaping in High−Speed Mode When the ECU experiences a loss of ground condition, this pin is switched to a high impedance state. The ground connection through this pin is not interrupted in any transceiver operating mode including the sleep mode. The ground connection only is interrupted when there is a valid loss of ground condition. This pin provides the bus load resistor with a path to ground which contributes less than 0.1 V to the bus offset voltage when sinking the maximum current through one unit load resistor. This path exists in all operating modes, including the sleep mode. The transceiver’s maximum bus leakage current contribution to Vol from the LOAD pin when in a loss of ground state is 50 mA over all operating temperatures and 3.5 < VBAT < 27 V. VBAT Input Pin Vehicle Battery Voltage Wave shaping control of the rising and falling waveform edges are disabled during high−speed mode. EMI emissions requirements are waived during this mode. The waveform rise time in this mode is less than 1.0 ms. Short Circuits If the CAN BUS pin is shorted to ground for any duration of time, the current is limited as specified in the Electrical Characteristics Table until an overtemperature shutdown circuit disables the output high side drive source transistor preventing damage to the IC. Loss of Ground In case of a valid loss of ground condition, the LOAD pin is switched into high impedance state. The CANH transmission is continued until the undervoltage lock out voltage threshold is detected. Loss of Battery The transceiver is fully operational as described in the Electrical Characteristics Table over the range 6.0 V < VBAT < 18 V as measured between the GND pin and the VBAT pin. For 5.0 V < VBat < 6.0 V, the bus operates in normal mode with reduced dominant output voltage and reduced receiver input voltage. High voltage wake−up is not possible (dominant output voltage is the same as in normal or high−speed mode). The transceiver operates in normal mode when 18 V < VBat < 27 V at 85°C for one minute. CAN BUS Input/Output Pin Wave Shaping in Normal and High Voltage Wake−Up Mode In case of loss of battery (VBAT = 0 or open) the transceiver does not disturb bus communication. The maximum reverse current into the power supply system (VBAT) doesn’t exceed 500 mA. INH Pin (14 pin package only) Wave shaping is incorporated into the transmitter to minimize EMI radiated emissions. An important contributor to emissions is the rise and fall times during output transitions at the “corners” of the voltage waveform. The resultant waveform is one half of a sin wave of frequency 50−65 kHz at the rising waveform edge and one quarter of this sin wave at falling or trailing edge. The INH pin is a high−voltage highside switch used to control the ECU’s regulated microcontroller power supply. After power−on, the transceiver automatically enters an intermediate standby mode, the INH output will go high (up to VBAT) turning on the external voltage regulator. The external regulator provides power to the ECU. If there is no mode change within 250 ms (typ), the transceiver re−enters the sleep mode and the INH output goes to logic 0 (floating). When the transceiver has detected a valid wake−up condition (bus HVWU traffic which exceeds the wake−up filter time delay) the INH output will become high (up to VBAT) again and the same procedure starts as described after power−on. In case of a mode change into any active mode, the sleep timer is stopped and INH stays high (up to VBAT). If the transceiver enters the sleep mode, INH goes to logic 0 (floating) after 250 ms (typ) when no wake−up signal is present. http://onsemi.com 12 NCV7356 HVWU Mode MODE0 low MODE1 high MODE0/1 => High High−Speed Mode MODE0 high MODE0&1 => Low MODE1 low VBATon Normal Mode MODE0 high MODE0/1 => High (If VCC_ECU on) MODE1 high VBAT standby after 250 ms −> no mode change −> no valid wake−up MODE0/1 low RxD high/low(1) CAN float wake−up request from Bus Sleep Mode MODE0/1 low (1) CAN float low after HVWU, high after VBAT on & VCCECU present Figure 6. State Diagram, 8 Pin Package http://onsemi.com 13 NCV7356 HVWU Mode MODE0 low MODE1 high INH VBAT MODE0/1 => High High−Speed Mode MODE0 high MODE0&1 => Low MODE1 low INH VBAT VBATon Normal Mode MODE0 high MODE1 high INH VBAT MODE0/1 => High (If VCC_ECU on) VBAT standby after 250 ms −> no mode change −> no valid wake−up MODE0/1 INH low VBAT RxD high/low(1) CAN float wake−up request from Bus Sleep Mode MODE0/1 low (1) INH/CAN floating low after HVWU, high after VBAT on & VCCECU present Figure 7. State Diagram, 14 Pin Package http://onsemi.com 14 NCV7356 MRA4004T3 VBAT * + VBAT_ECU Voltage Regulator VBAT +5 V 100 nF ECU Connector to Single Wire CAN Bus + 2.7 kW 5 4 RxD CAN Controller 100 pF VBAT 1k 47 mH 7 CANH NCV7356 MODE0 MODE1 TxD 2 3 6 1 8 LOAD 6.49 kW 100 pF ESD Protection − NUP1105L GND *Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses) Figure 8. Application Circuitry, 8 Pin Package http://onsemi.com 15 NCV7356 MRA4004T3 VBAT * + VBAT_ECU Voltage Regulator INH VBAT +5 V 100 nF ECU Connector to Single Wire CAN Bus + 2.7 kW 9 5 RxD CAN Controller 100 pF VBAT 10 1k 47 mH 12 CANH NCV7356 MODE0 MODE1 TxD 3 4 11 2 1, 7, 8, 14 LOAD 6.49 kW 100 pF ESD Protection − NUP1105L GND *Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses) Figure 9. Application Circuitry, 14 Pin Package http://onsemi.com 16 NCV7356 SOIC−8 Thermal Information Test Condition, Typical Value Parameter Junction−to−Lead (psi−JL7, YJL8) or Pins 6−7 Junction−to−Ambient (RqJA, qJA) 20. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4. 21. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4. Package Construction with and without Mold Compound Various copper areas used for heat spreading Min Pad Board (Note 20) 57 187 1, Pad Board (Note 21) 51 128 Unit °C/W °C/W Active Area (red) Lead #1 Figure 10. Internal construction of the package simulation. Figure 11. Min pad is shown as the red traces. 1, pad includes the yellow area. Internal construction is shown for later reference. 190 180 170 qJA (°C/W) 160 150 140 130 120 110 100 0 100 200 300 400 500 (mm2) 600 700 800 2.0 oz. Cu 1.0 oz. Cu Copper Area Figure 12. SOIC−8, qJA as a Function of the Pad Copper Area Including Traces, Board Material http://onsemi.com 17 NCV7356 Table 1. SOIC−8 Thermal RC Network Models* 53 mm2 719 mm2 Copper Area 53 mm2 719 mm2 Copper Area Cauer Network C’s 5.86E−06 2.29E−05 6.98E−05 3.68E−04 3.75E−04 1.57E−03 2.05E−02 9.13E−02 2.64E−01 1.66E+01 R’s 0.22 0.50 1.30 1.80 0.95 7.43 31.19 59.97 75.79 4.41 C’s 5.86E−06 2.29E−05 6.97E−05 3.68E−04 3.74E−04 1.56E−03 2.24E−02 7.35E−02 1.22E+00 9.74E+00 R’s 0.22 0.50 1.30 1.79 0.96 7.37 31.59 47.70 28.63 6.15 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C Tau Foster Network Tau 1.00E−06 1.00E−05 1.00E−04 1.99E−04 1.00E−03 1.64E−02 5.60E−01 4.50E+00 7.61E+01 3.00E+01 R’s 1.30E−01 2.82E−01 8.91E−01 0.18 1.88 7.24 16.27 54.7 23.3 21.3 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units sec sec sec sec sec sec sec sec sec sec 1.00E−06 1.00E−05 1.00E−04 1.99E−04 1.00E−03 1.64E−02 5.60E−01 4.50E+00 7.61E+01 3.00E+01 R’s 1.30E−01 2.82E−01 8.91E−01 0.17 1.88 7.15 19.80 30.1 14.1 109.0 *Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 130 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Both Foster and Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) + S1 Ri 1−e−t taui i+ n http://onsemi.com 18 NCV7356 Junction C1 R1 C2 R2 C3 R3 Cn Ambient (thermal ground) Rn Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Figure 13. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Ambient (thermal ground) Each rung is exactly characterized by its RC−product time constant; Amplitudes are the resistances Figure 14. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) 1000 Cu Area = 53 mm2 1.0 oz. Cu Area = 93 mm2 1.0 oz. 100 Rq (°C/W) Cu Area = 719 mm2 1.0 oz. 10 1 0.1 0.000001 0.00001 0.0001 0.001 0.01 Time (s) 0.1 1 10 100 1000 Figure 15. SOIC−8 Single Pulse Heating Curve 1000 100 D = 0.50 Rq (°C/W) 0.20 0.10 10 0.05 0.02 1 0.01 Single Pulse 0.00001 0.0001 0.001 0.01 Time (s) 0.1 1 10 100 1000 0.1 0.000001 Figure 16. SOIC−8 Thermal Duty Cycle Curves on 1, Spreader Test Board http://onsemi.com 19 NCV7356 SOIC−14 Thermal Information Test Condition, Typical Value Parameter Junction−to−Lead (psi−JL8, YJL8) Junction−to−Ambient (RqJA, qJA) 22. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4. 23. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4. Min Pad Board (Note 22) 30 122 1, Pad Board (Note 23) 30 84 Unit °C/W °C/W Figure 18. Min pad is shown as the red traces. 1 inch pad includes the yellow area. Pin 1, 7, 8 and 14 are connected to flag internally to the package and externally to the heat spreading area. Figure 17. Internal construction of the package simulation. 150 140 130 qJA (°C/W) 120 110 100 90 80 70 60 0 100 200 300 400 500 600 700 800 900 Copper Area (mm2) 2.0 oz. Cu 1.0 oz. Cu Sim 1.0 oz. Sim 2.0 oz. Figure 19. SOIC−14, qJA as a Function of the Pad Copper Area Including Traces, Board Material http://onsemi.com 20 NCV7356 Table 2. SOIC−14 Thermal RC Network Models* 96 mm2 767 mm2 Copper Area 96 mm2 767 mm2 Copper Area Cauer Network C’s 3.12E−05 1.21E−04 3.53E−04 1.19E−03 4.86E−03 2.17E−02 8.94E−02 0.304 1.71 R’s 0.041 0.095 0.279 1.154 5.621 13.180 23.823 53.332 24.794 C’s 3.12E−05 1.21E−04 3.50E−04 1.19E−03 5.05E−03 7.16E−03 3.51E−02 0.262 2.43 411 R’s 0.041 0.096 0.281 0.995 6.351 1.910 21.397 27.150 25.276 0.218 °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Units W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C W−s/C R’s Tau Foster Network Tau 1.00E−06 1.00E−05 1.00E−04 0.001 0.009 0.047 0.875 7.53 68.4 92.221 R’s 2.44E−02 5.28E−02 1.67E−01 0.7 0.1 5.8 16.4 27.1 29.0 4.3 °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W 2.44E−02 5.28E−02 1.67E−01 3.5 0.7 8.7 15.9 31.9 61.3 Units sec sec sec sec sec sec sec sec sec sec 1.00E−06 1.00E−05 1.00E−04 0.028 0.001 0.280 2.016 16.64 59.47 *Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Both Foster and Cauer networks can be easily implemented Junction C1 R1 C2 R2 C3 R3 using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) + S1 Ri 1−e−t taui i+ Rn Cn Ambient (thermal ground) n Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Figure 20. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R1 R2 R3 Rn C1 C2 C3 Cn Ambient (thermal ground) Each rung is exactly characterized by its RC−product time constant; Amplitudes are the resistances Figure 21. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder) http://onsemi.com 21 NCV7356 1000 Cu Area = 96 mm2 1.0 oz. 100 Cu Area = 767 mm2 1.0 oz. Cu Area = 767 mm2 1.0 oz. 1S2P 1 Rq (°C/W) 10 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.01 Time (s) 0.1 1 10 100 1000 Figure 22. SOIC−14 Single Pulse Heating 1000 D = 0.50 100 0.20 0.10 0.05 0.01 1 Cu Area = 717 mm2 1.0 oz. Rq (°C/W) 10 0.1 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE DURATION (sec) Figure 23. SOIC−14 Thermal Duty Cycle Curves on 1, Spreader Test Board http://onsemi.com 22 NCV7356 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F DIM A B C D F G J K M P R −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 14X 14X 1.52 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 23 NCV7356 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* DIM A B C D G H J K M N S 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 24 NCV7356/D