NCV78663
Power Ballast and Dual LED
Driver for Automotive Front
Lighting
The NCV78663 is a single−chip and high efficient smart Power
ballast and Dual LED DRIVER designed for automotive front lighting
applications like high beam, low beam, daytime running light (DRL),
turn indicator, fog light, static cornering, and so on.
The NCV78663 is a best fit for high current LEDs and provides a
complete solution to drive two strings up to 60 V, by means of two
internal independent buck switch channels, with a minimum of
external components.
For each channel, the output current and voltage can be customized
according to the application requirements. Diagnostic feature for
automotive front lighting is provided on−chip.
The device integrates a voltage booster controller, realizing a unique
input current filter with a limited number of externals.
The NCV78663 can be used in stand−alone mode or together with a
companion microcontroller allowing maximum flexibility. Depending
on the voltage and current of the connected LED string, the LED
ballast parameters can be adapted by writing the SPI settings in the
device, as such that no hardware changes are required.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Chip Boost−Buck Solution
Two Independent LED Strings Up to 60 V
High Overall Efficiency
Minimum of External Components
Active Input Filter with Low Current Ripple from Battery
Integrated Switched Mode Buck Current Regulator
Two Integrated Buck Switches with 1.4 A Peak Current Capability
Integrated Boost Controller
Programmable Input Current Limitation
Average Current Regulation Through the LEDs
High Operating Switching Frequencies to Reduce Inductor Sizes
Integrated PWM Dimming with Wide Frequency Range
Low EMC Emission for LED Switching and Dimming
SPI Interface for Optional External mC and Dynamic Control of
System Parameters
This is a Pb−Free Device
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MARKING
DIAGRAM
NCV78663−0
AWLYYWWG
SSOP36 EP
CASE 940AB
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 36 of this data sheet.
Typical Applications
•
•
•
•
•
•
•
High Beam
Low Beam
DRL
Position or Park light
Turn Indicator
Fog Light
Static Cornering
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 1
1
Publication Order Number:
NCV78663/D
NCV78663
VDRIVE
VBB
VBOOST
VREG10V
VDD
VBOOSTM3V
VREGM3V
VBOOST_AUXSUP
Buck regulator X 2
VREG3V
IBCKxSENSE+
OTP
I sense
ROM
IBCKxSENSE−
VINBCKx
POWER STAGE
VGATE
Driver
BOOST PREDRV
IBSTSENSE+
LBCKSWx
VDD
IBSTSENSE−
V REF
ILIM detector
DIAGx
Fixed Toff Time
VLEDx
3V output
LEDCTRLx
40V input
V BOOST
SPI bus
V BB
5V in / OD out
VDD
BIAS
VDD
OSC4M
8
VDD
ADC
VLED1
MUX
VLED2
‘
TEMPdet
VDD
OSC16M
VDD
BGAP
VDD
Channel
selector
POR3V
Figure 1. Internal Block Diagram
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2
Buffer
VTEMP1
Buffer
VTEMP2
NCV78663
PACKAGE AND PIN DESCRIPTION
GNDP
VGATE
VDRIVE
VBB
NC
LEDCTRL1
LEDCTRL2
DIAG1
DIAG2
VDD
GND
TEST1
TEST2
NC
SCLK
SCS
SDI
SDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
IBSTSENSE+
IBSTSENSE−
VBOOSTM3V
VBOOST
NC
IBCK1SENSE+
IBCK1SENSE−
VINBCK1
LBCKSW1
LBCKSW2
VINBCK2
IBCK2SENSE−
IBCK2SENSE+
NC
VLED1
VLED2
VTEMP/AGP1
VTEMP/AGP2
SSOP36
Figure 2. Pin Connections
Table 1. PIN DESCRIPTION
Pin#
Pin Name
IO Type
Function
1
GNDP
ground
Power ground
2
VGATE
MV out
Booster MOSFET gate pre−driver
3
VDRIVE
MV supply
10 V supply
4
VBB
HV supply
Battery supply
5
N.C.
6
LEDCTRL1
HV IO
LED string 1 enable
7
LEDCTRL2
HV IO
LED string 2 enable
8
DIAG1
LV out
LED string 1 diagnostic output
LED string 2 diagnostic output
Not used (can be connected to GND)
9
DIAG2
LV out
10
VDD
LV supply
11
GND
Ground
12
TEST1
LV in
Test (not used in application, must connected to GND)
13
TEST2
LV in
Test (not used in application, must connected to GND)
14
N.C.
3 V logic supply
Ground
Not used (can be connected to GND)
15
SCLK
MV in
SPI clock
16
SCS (CSB)
MV in
SPI chip select (chip select bar)
17
SDI
MV in
SPI data input
18
SDO
MV
open−drain
19
VTEMP/AGP2
LV in
LED string 2 temperature feedback input
20
VTEMP/AGP1
LV in
LED string 1 temperature feedback input
21
VLED2
HV in
LED string 2 forward voltage input
22
VLED1
HV in
LED string 1 forward voltage input
23
N.C.
24
IBCK2SENSE+
HV in
Buck 2 positive sense input
25
IBCK2SENSE−
HV in
Buck 2 negative sense input
26
VINBCK2
HV in
Buck 2 high voltage supply
27
LBCKSW2
HV out
Buck 2 switch output
28
LBCKSW1
HV out
Buck 1 switch output
SPI data output
Not used (can be connected to GND)
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NCV78663
Table 1. PIN DESCRIPTION
Pin#
Pin Name
IO Type
29
VINBCK1
HV in
Buck 1 high voltage supply
Function
30
IBCK1SENSE−
HV in
Buck 1 negative sense input
31
IBCK1SENSE+
HV in
Buck 1 positive sense input
32
N.C.
33
VBOOST
HV supply
34
VBOOSTM3V
HV IO
VBOOST−3V output
35
IBSTSENSE−
LV IO
Battery current negative feedback input
36
IBSTSENSE+
LV IO
Battery current positive feedback input
Not used (can be connected to GND)
L_boost
FET_boost
Cboost_IN
High voltage feedback input
C_boost _OUT
VBOOST
VBOOSTM3V
VDRIVE
IBSTSENSE−
VGATE
VBB
IBSTSENSE+
Rboost _sense
IBCK1SENSE +
VINBCK 1
LBCKSW 1
VDD
ON Semiconductor
LEDCTRL1
LED driver
Front Lighting
NCV78663
1A
RF1
VLED1
T
VTEMP /AGP1
Optional temp sensing network
IBCK2SENSE+
Light ECU
DIAG2
C_buck_1
L_buck_1
LED−string 1
LBCKSW 1
LEDCTRL2
DIAG1
R_buck_1_sense
IBCK1SENSE−
R_buck_2_sense
IBCK2SENSE−
VINBCK 2
L_buck_2
CAN
Or
LIN
SPI_SCLK
Optional
mC
LED−string 2
1A
SPI_SDO
RF2
SPI_SCS
TST1 TST2
C_buck_2
LBCKSW 2
SPI_SDI
VLED2
GND
GNDP
T
VTEMP /AGP2
Optional temp sensing network
Signal GND :
Power GND :
Figure 3. NCV78663 Application Circuit
1. As reported in the application diagram, the device pins TEST1 and TEST2 must be connected to ground.
2. For details about PCB layout, please refer to the dedicated section.
3. RF1 and RF2 resistors typical value is 2.2 kW and minimum required value is 1 kW. It is recommended not to exceed a value of 22 kW in
order not to alter the VLED sampled value.
SPI MASTER
(MCU/LOGIC)
CAN
Or
LIN
MASTER_VDD
(Note 3)
SLAVE_VDD
RSDO
Master In Slave Output (MISO)
MASTER_CLK
SDO
(Note 4)
SCLK
Master Out Slave Input (MOSI)
(Note 4)
SDI
MASTER_CSB
(Note 4)
SCSB
MASTER_GND
NCV78663
SPI BLOCK
(SLAVE)
SLAVE_GND
Figure 4. Details on NCV78663 Connection Diagram for SPI (Optional)
4. RSDO external resistor typical value is 1 kW. An additional capacitor to ground (typically 47 pF) may be used in case of application noise
observed.
5. External capacitors or RC may be added to these SPI lines for stable communication in case of application noise. The selection of these
components must be done so that the resulting waveforms are respecting the limits reported in Table 23.
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NCV78663
OPERATING CONDITIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Min
Max
Unit
VBB
−0.3
60
V
VBOOST
−0.3
68
V
Logic Supply voltage
VDD
−0.3
3.6
V
Low voltage I/O pins (Note 8)
IOLV
−0.3
VDD + 0.3
V
VDRIVE
−0.3
12
V
Battery Supply voltage (Note 6)
LED supply voltage (Note 7)
Gate driver supply voltage (Note 9)
GNDP voltage
Input current sense voltage
GNDP_V
−0.3
0.3
V
IBSTSENSE+,
IBSTSENSE−
−1.0
3.6
V
IOMV
−0.3
7.0
V
LBCKSW1,
LBCKSW2
−2.0
VBOOST
V
DV_IO
VBOOSTM3V
VBOOST
V
Tstrg
−50
135
°C
1.4
A
+2
kV
Medium voltage IO pins (Note 10)
Buck switch low side
Relative voltage IO pins (Note 11)
Storage Temperature
Buck switch output current (Note 12)
I_LBCKSW
Electrostatic discharge on component level (Note 13)
VESD
−2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
6. Absolute maximum rating for pins: VBB, LEDCTRL1, LEDCTRL2.
7. Absolute maximum rating for pins: VBOOST, VBOOSTM3V, IBCK1SENSE+, IBCK1SENSE−, VINBCK1, VLED1, IBCK2SENSE+,
IBCK2SENSE−, VINBCK2, VLED2.
8. Absolute maximum rating for pins: TEST1, TEST2, VTEMP1, VTEMP2, DIAG1, DIAG2.
9. Absolute maximum rating for pins: VDRIVE, VGATE.
10. Absolute maximum rating for pins: SCLK, SCS, SDI, SDO.
11. Relative maximum rating for pins: VINBCK1, VINBCK2, IBCK1SENSE+, IBCK2SENSE+, IBCK1SENSE−, IBCK2SENSE−
12. Peak value.
13. Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA/JESD22−A114).
Table 3. RECOMMENDED OPERATING CONDITIONS
Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the
device outside the operating ranges described in this section is not warranted. Operating outside the recommended operating ranges
for extended time may affect device reliability. A mission profile (Note 14) is a substantial part of the operation conditions, hence the
Customer must contact ON Semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application.
Characteristic
Battery Supply Voltage
Symbol
Min
Max
Unit
VBB
5
40
V
Battery Supply Current (Note 15)
IBB
20
mA
Logic Supply Output Current
IDD
10
mA
5V Tolerant IO pins
DIG_IO_V
0
5.5
V
VTEMP/AGPx pins
VTEMPAGP_V
0.3
VDD
V
10
mA
Gate Driver Supply Current (Note 16)
Idrive
Ambient Temperature
Junction Temperature
TA
−40
125
°C
TJ
−45
170
°C
VBB Voltage during OTP Zapping
VBB_ZAP
13
40
V
OTP zap Ambient Temperature
TA_zap
10
30
°C
1.2
A
Buck Switch Output Current (Note 17)
I_LBCKSW
14. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,
the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the
device is operated by the customer, etc.
15. VBB = 13 V; Idrive = 10 mA
16. VBB = 13 V; Idrive = Q_gate x f_boost
17. Average value
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NCV78663
Table 4. THERMAL RESISTANCE
Characteristic
Thermal resistance junction to exposed pad
Package
Symbol
Max
Unit
SSOP36
qJCbot
3.49
KW−1
ELECTRICAL CHARACTERISTICS
NOTE:
Unless differently specified, all device Min & Max parameters boundaries are given for the full supply operating range and the
junction temperature (TJ) range (-40;160) (°C).
Table 5. VBB: BATTERY SUPPLY INPUT
Characteristic
Nominal Operating Supply
Range
Device Current
Consumption
Symbol
Conditions
VBB
IBB_0
Min
Typ
Max
Unit
40
V
6
10
mA
5
buck regulators off, gate drive off,
outputs unloaded
Table 6. VDRIVE: 10 V SUPPLY FOR BOOST FET GATE DRIVE CIRCUIT
Characteristic
VDRIVE regulator output
voltage
Symbol
Conditions
Min
Typ
Max
Unit
VDRIVE
VBB > 11 V: VDRIVE generated from
VREG10V
9
10
11
V
VBB < 10 V: VDRIVE generated from
VBOOST_AUXSUP*
MAX(
5.5;
VBB −
1.65)
7.8
15
mA
VBB > 11 V: VDRIVE generated from
VREG10V
36
185
mA
VBB < 10 V: VDRIVE generated from
VBOOST_AUXSUP
15
190
mA
DC output current capability
Iout_VDRIVE
Output current limitation
ILIM_VDRIVE
Typical VDRIVE external
decoupling capacitor
C_VDRIVE
V
0.47
ESR
mF
200
mW
*Boost regulator must be active.
Table 7. VDD: 3 V LOW VOLTAGE ANALOG DIGITAL SUPPLY
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VDD regulator output voltage
VDD
VDRIVE > 4.5 V
2.9
3
3.1
V
DC output current capability
Iout_VDD
VDRIVE > 4.5 V
10
mA
Output current limitation
Ilim_VDD
VDRIVE > 4.5 V
200
mA
10
mF
200
mW
Typical VDD external
decoupling capacitor
C_VDD
40
0.22
0.47
ESR
POR Toggle level on VDD
rising
POR3V_H
1.43
2.3
2.54
V
POR Toggle level on VDD
falling
POR3V_L
1.26
2.0
2.14
V
POR Hysteresis
POR3V_ Hyst
0.25
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6
V
NCV78663
Table 8. VBOOSTM3V: HIGH SIDE AUXILIARY SUPPLY
Characteristic
VBSTM3 regulator output
voltage
Output current limitation
Typical VBSTM3 decoupling
capacitor
Symbol
Conditions
Min
Typ
Max
Unit
VBSTM3
Referenced to VBOOST
−3.6
−3.3
−2.9
V
200
mA
4.7
mF
200
mW
Ilim_VBOOSTM3V
C_VBSTM3
Referenced to VBOOST
ESR
Referenced to VBOOST
0.47
Table 9. OSC4M: SYSTEM OSCILLATOR CLOCK
Characteristic
System oscillator frequency
Symbol
Conditions
Min
Typ
Max
Unit
FOSC4M
After trimming
3.5
4.0
4.5
MHz
Max
Unit
Table 10. ADC FOR MEASURING VBOOST, VBB, VLED1, VLED2, VTEMP/AGP1, VTEMP/AGP2
Characteristic
Symbol
Conditions
Min
Typ
ADC Resolution
ADC_res
Integral Nonlinearity (INL)
ADC_INL
−1.5
+1.5
LSB
Differential Nonlinearity (DNL)
ADC_DNL
−2.0
+2.0
LSB
ADC_GAINERROR
−3.25
3.25
%
ADC_OFFSET
−2
2
LSB
Full path gain error for
measurements via VBB,
VLEDx, VTEMP, VBOOST
Offset at output of ADC
Time for 1 SAR conversion
8
Bits
ADCConv
8
ms
ADCFS_VBB
40
V
ADCFS_VLED
80
V
ADC full scale for VTEMP
ADCFS_VTEMP
3
V
ADC full scale for Vboost
ADCFS_VBOOST
80
V
ADC full scale for VBB
measurement
ADC full scale for VLED
VLEDx input impedance
VTEMP/AGPx input impedance
ADC_VLED_INZ
355
500
710
kW
ADC_VTAGP_INZ
1.2
3
4.5
MW
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NCV78663
Table 11. BOOSTER
Name
Booster
output
range
Symbol
VBOOST
Normal Regulation Window
(Note 18)
SHUTDOWN
SPI/OTP
SETTING
NREGL
TRGT
NREGH
MAX
Range 0
[0000]
19.5
24.5
30
49
Range 1
[0001]
22
27
32.5
49
Range 2
[0010]
24
29.5
35
49
Range 3
[0011]
27
32
38
49
Range 4
[0100]
29
35
40.5
49
Range 5
[0101]
31.5
37
43.0
49
Range 6
[0110]
34
40
45.5
59
Range 7
[0111]
36.5
42
48
59
Range 8
[1000]
39.0
45
51
59
Range 9
[1001]
41.5
47
53.5
59
Range 10
[1010]
44
50
56
59
Range 11
[1011]
46
52
57.5
59
Range 12
[1100]
48
54.5
60.5
62
Range 13
[1101]
49
57
65.0
67
Range 14
[1110]
52
59.5
65.5
67
Range 15
[1111]
57.5
62
66.5
67
Conditions
Unit
V
18. For further details about the booster table and definitions, please refer to the related section contained in this datasheet.
Table 11. BOOSTER (continued)
Booster Oscillator Frequency [2:0]
Name
Booster
oscillator
frequency
Booster PWM
frequency
Symbol
OSC16M
FPWMBOOST
Conditions
SPI/OTP Setting
FPWMBOOST = 180 kHz
[011]
FPWMBOOST = 203 kHz
[010]
13
FPWMBOOST = 227 kHz
[001]
14.5
FPWMBOOST = 250 kHz
[000]
FPWMBOOST = 273 kHz
[111]
FPWMBOOST = 297 kHz
[110]
19
FPWMBOOST = 320 kHz
[101]
20.5
FPWMBOOST = 344 kHz
[100]
22
= f_OSC16M / 64
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8
Min
Typ
Max
Unit
+12%
MHz
11.5
−12%
16
17.5
OSC16M is programmable in SPI/OTP
NCV78663
Table 11. BOOSTER (continued)
Boost_ctrl_rate [2:0]
Symbol
Name
Booster control
rate
OTP Setting Only
Typ
[011]
86
[010]
144
[001]
240
[000]
Boost_ctrl_rate
Min
[111]
−12.5%
400
667
[110]
1111
[101]
31
[100]
52
Max
Unit
+12.5%
ms
Table 12. BOOSTER PRE−DRIVER
Name
Symbol
High−side switch
impedance
Low−side switch
impedance
Min
Typ
Max
Unit
RONHI
2.5
4
W
RONLO
2.5
4
W
Min
Typ
Max
Unit
Table 13. BOOSTER − CURRENT LIMITATION
Name
Symbol
Current limitation
threshold voltage
VLIMTH
Over full operating range
78
100
122
mV
VLIMTH_hot
At TJ = 160 °C
85
100
115
mV
VLIMHYS
5
10
20
mV
CMVSENSE
−1
1
V
Threshold
voltage
hysteresis
Sense voltage
common mode
range
Table 14. ON−CHIP TEMPERATURE SENSOR
Name
Symbol
Min
Typ
Max
Unit
Thermal shut−down level
(junction temperature)
TSD
163
169
175
°C
Thermal warning level
(junction temperature)
TW
TSD −
5
°C
Table 15. BUCK REGULATOR − SWITCH
Name
On resistance
Symbol
Min
RDS(on)
Typ
Max
Unit
0.82
1.0
W
3
A
Overcurrent
detection
OCD
1.4
Switching slope
Trise
3
V/ns
Tfall
3
V/ns
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NCV78663
Table 16. BUCK REGULATOR − CURRENT REGULATION
Name
Symbol
Current sense
comparator threshold
voltage setpoint
(= end of the BUCK
ON−phase) MIN
value
VThreshold_MIN
Current sense
comparator threshold
voltage setpoint
(= end of the BUCK
ON−phase) MAX
value
VThreshold_MAX
Current comparator
threshold voltage
setpoint step (internal
DAC resolution)
Delta VThreshold
Name
Symbol
SPI/OTP
SETTING
Min
Typ
Max
Smallest Toff x VLED
constant
Toff_V_1
[0000]
9.9
12.4
14.9
Toff_V_2
[0001]
19.8
24.5
29.2
Toff_V_3
[0010]
39.6
45.9
52.2
Toff_V_4
[0011]
57
66.6
76.2
Toff_V_5
[0100]
76.4
88
99.6
Toff_V_6
[0101]
96.2
110
123.8
Toff_V_7
[0110]
116.8
132
147.2
Toff_V_8
[0111]
135.8
154
172.2
Toff_V_9
[1000]
154.5
176
197.5
Toff_V_10
[1001]
173.2
198
222.8
Toff_V_11
[1010]
191.8
220
248.2
Toff_V_12
[1011]
210.6
242
273.4
Toff_V_13
[1100]
229.1
264
298.9
Toff_V_14
[1101]
248
286
324
Toff_V_15
[1110]
266.4
308
349.6
Toff_V_16
[1111]
283.3
330
376.2
Mid range off−time
(trimmed @ VLED =
55 V)
Longest off−time
Min
Typ
Max
Unit
Programmable with 7−bit resolution
internal DAC
(bit code 0 = [0 0 0 0 0 0 0])
25
30
35
mV
Programmable with 7−bit resolution
internal DAC
(bit code 127 = [1 1 1 1 1 1 1])
370
411
451
mV
3
Value on the right
represents
[VLED * Toff_i]
VLED = 55 V and
TJ = 155°C
VLED > 5.4 V
Off−time = f (VLED)
Toff_V_i
mV
Unit
ms x V
Toff_i * VLED = CONST
ms x V
6V < VLED < 55 V and Tj is fixed
CONST
− 8.5%
Toff_i * VLED
= CONST
CONST
+ 8.5%
ms x V
10V < VLED < 55 V and Tj is fixed
CONST
− 7%
Toff_i * VLED
= CONST
CONST
+ 7%
ms x V
−45°C OCD
See Section Buck
Regulator − Switch
DIAGx*
Disabled
Y
Y
SRx.[0]*
*...x = ...1 or ...2
** See Table 28
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NCV78663
PCB LAYOUT RECOMMENDATIONS
The areas which are most critical for a layout point of view
are highlighted in the following picture:
This section contains instructions for the NCV78663 PCB
layout application design. Although this guide does not
claim to be exhaustive, these directions can help the
developer to reduce application noise impact and insuring
the best system operation.
Figure 18. NCV78663: Application Critical Areas at PCB Level
Booster Current Limitation Circuit: AREA (A)
C. The MOSFET’s dissipation area should be
stretched in a direction away from the sense
resistor to minimize resistivity changes due to
heating;
D. Possibly reduce to the least the distance between
Rboost_sense and the NCV78663 boost limitation
comparator’s inputs (IBSTSENSE+ and
IBSTSENSE−);
E. If the current sense measurement tracks are
interrupted by series resistors or jumpers (once as
a maximum) their value should be matched and
low ohmic (pair of 0 W to 47 W max) to avoid
errors due to the comparator input bias currents;
F. Avoid using the board GND as one of the
measurement terminals as this would also
introduce errors.
The booster limitation circuit relies on a low voltage
comparator, which triggers with respect to the sense voltage
across the external resistor Rboost_sense. In order to
maximize power efficiency, the threshold voltage is set to a
rather low value by design (typical 100 mV, see Table 13)
and this area may be affected by the MOSFET switching
noise if no specific care is taken. The following
recommendations are given:
A. Use a four terminals current sense method as
depicted in the figure below. The measurement
PCB tracks should run in parallel and as close as
possible to each other, trying to have the same
length. The number of vias along the measurement
path should be minimized;
B. Place Rboost_sense sufficiently close to the
MOSFET source terminal;
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34
NCV78663
Figure 19. Four Wires Sensing Method for Boost Current Limitation Comparator
Buck Current Comparators: AREAs (B1) and (B2)
Vboost Related Tracks: AREA (C)
The blocks (B1) and (B2) control the buck peak currents
by means, respectively, of the external sense resistors
Rbuck_1_sense and R_buck_2_sense. As the regulation is
performed with a comparator, the considerations explained
in the previous section “Booster Current Limitation Circuit:
AREA (A)” remain valid.
In particular, the use of a four terminals current sense
method is required, this time applied on (IBCK1xSENSE+,
IBCKxSENSE−). The sensing PCB tracks should be kept as
short as possible, with the sense resistors close to the device,
but preferably outside of its PCB heating area in order to
limit measurement errors produced by temperature drifts.
The three NCV78663 device pins VBOOST,
IBCK1SENSE+ and IBCK2SENSE+ must be at the same
individual voltage potential to guarantee proper functioning
of the internal buck current comparator (whose supply rails
are Vboost and VboostM3V). In order to achieve this target,
it is suggested to make a PCB star track connection between
these three points close to the device pins. The width of the
tracks should be large enough (>40 mils) and their length as
balanced as possible (ideally all equal).
Figure 20. PCB Star Connection Between Vboost, IBCK1SENSE+ and IBCK2SENSE+ (simplified drawing)
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35
NCV78663
GND Connection: AREA (D)
between the signal GND (all low power related functions)
and the power GND (related to all power switching areas).
The device exposed pad should be connected to the GND
plane for dissipation purposes.
The NCV78663 GND and GNDP pins must be connected
together. It is suggested to perform this connection directly
close to the device, behaving also as the cross-junction
ORDERING INFORMATION
Package
Shipping†
NCV78663DQ0G
SSOP36 EP
(Pb−Free)
47 Units / Rail
NCV78663DQ0R2G
SSOP36 EP
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
36
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP36 EP
CASE 940AB
ISSUE A
DATE 19 JAN 2016
SCALE 1:1
0.20 C A-B
D
4X
36
E1
1
X = A or B
e/2
E
DETAIL B
36X
0.25 C
18
e
36X
B
b
0.25
TOP VIEW
A
H
X
19
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN 1
REFERENCE
D
DETAIL B
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED BETWEEN 0.10 AND 0.25 FROM THE TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. DIMENSIONS D AND E1 SHALL BE
DETERMINED AT DATUM H.
6. THIS CHAMFER FEATURE IS OPTIONAL. IF
IT IS NOT PRESENT, A PIN ONE IDENTIFIER
MUST BE LOACATED WITHIN THE INDICATED AREA.
T A
M
S
B
S
NOTE 6
h
A2
DETAIL A
c
h
0.10 C
36X
SIDE VIEW
A1
END VIEW
SEATING
PLANE
C
D2
M1
DIM
A
A1
A2
b
c
D
D2
E
E1
E2
e
h
L
L2
M
M1
MILLIMETERS
MIN
MAX
--2.65
--0.10
2.15
2.60
0.18
0.30
0.23
0.32
10.30 BSC
5.70
5.90
10.30 BSC
7.50 BSC
3.90
4.10
0.50 BSC
0.25
0.75
0.50
0.90
0.25 BSC
0_
8_
5_
15 _
GENERIC
MARKING DIAGRAM*
M
GAUGE
PLANE
E2
L2
C
SEATING
PLANE
36X
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AWLYYWWG
L
DETAIL A
SOLDERING FOOTPRINT
BOTTOM VIEW
5.90
4.10
36X
1.06
10.76
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
0.50
PITCH
36X
0.36
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON46215E
SSOP36 EXPOSED PAD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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