NCV78723MW2R2G

High Efficiency Buck Dual LED Driver with Integrated Current Sensing for Automotive Front Lighting NCV78723 The NCV78723 is a single-chip and high efficient Buck Dual LED Driver designed for automotive front lighting applications like high beam, low beam, DRL (daytime running light), turn indicator, fog light, static cornering, etc. The NCV78723 is in particular designed for high current LEDs and provides a complete solution to drive 2 LED strings of up-to 60 V. It includes 2 independent current regulators for the LED strings and required diagnostic features for automotive front lighting with a minimum of external components – the chip doesn’t need any external sense resistor for the buck current regulation. The available output current and voltages can be customized per individual LED string. When more than 2 LED channels are required on 1 module, then 2, 3 or more devices NCV78723 can be combined; also with NCV78713 device – the derivative of the NCV78723 incorporating Buck Single LED Driver. Thanks to the SPI programmability, one single hardware configuration can support various application platforms. www.onsemi.com 1 24 1 QFN24 CASE 485CS 24 QFNW24 CASE 484AF MARKING DIAGRAM 1 ON N78723−0 AWLYYWWG G Features • • • • • • • • • • • • • • Single Chip Buck Topology 2 LED Strings up-to 60 V High Current Capability up to 1.6 A DC per Output High Overall Efficiency Minimum of External Components Integrated High Accuracy Current Sensing Integrated Switched Mode Buck Current Regulator Average Current Regulation through the LEDs High Operating Frequencies to Reduce Inductor Sizes Low EMC Emission for LED Switching and Dimming SPI Interface for Dynamic Control of System Parameters Fail Safe Operating (FSO) Mode, Stand-Alone Mode These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 1 ON N78723−2 FAWLYYWWG G N78723−0 N78723−2 F A WL YY WW G = Specific Device Code = Specific Device Code = Fab Indicator = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 31 of this data sheet. Typical Applications • • • • • • • High Beam Low Beam DRL Position or Park Light Turn Indicator Fog Static Cornering © Semiconductor Components Industries, LLC, 2015 January, 2020 − Rev. 4 1 Publication Order Number: NCV78723/D NCV78723 TYPICAL APPLICATION SCHEMATIC VBOOST C_M3V VBOOSTM3V VBOOST LED-String 1 VINBCK1 LBCKSW1 L_BCK_1 D_1 LBCKSW1 External VCC of MCU R_LED_1 VLED1 ON Semiconductor LED Driver 2-Channel Buck NCV78723 VDD VINBCK2 VDD Supply C_DD C_LED_1 LED-String 2 LBCKSW2 R_SDO LBCKSW2 RSTB C_BCK_2 L_BCK_2 D_2 R_LED_2 VLED2 LEDCTRL1 mC C_BCK_1 C_LED_2 LEDCTRL2 SCLK SDI SDO EXPOSED PAD GND TEST2 TEST1 TEST CSB Figure 1. Typical Application Schematic Table 1. EXTERNAL COMPONENTS Component Function Typical Value Unit L_BCK_x Buck Regulator Coil (see Buck Regulator Chapter for Details) 47 mH C_BCK_x Buck Regulator Output Capacitor (see Buck Regulator Chapter for Details) 220 nF (see Table 6 − VBOOSTM3V) nF 470 nF 1 nF Min. 1 kW 1 kW C_M3V C_DD Capacitor for M3V Regulator VDD Decoupling Capacitor C_LED_x Optional VLEDx Pin Filter Capacitor (Note 2) R_LED_x VLEDx Pin Serial Resistor (Notes 2 and 3) R_SDO D_x SPI Pull-Up Resistor Buck Regulator Free-Wheeling Diode e.g. MBRS2H100T3G 1. Pin TEST has to be connected to ground. TEST1 and TEST2 pins can be connected to ground or left floating. 2. C_LED_x is optional. If used, time constant of the C_LED_x and R_LED_x filter has to be lower than minimal LEDCTRLx ON time in PWM dimming for proper VLED measurement. 3. R_LED_x is necessary to ensure Absolute Maximum Ratings of IVLEDx current (see Table 3). www.onsemi.com 2 NCV78723 BLOCK DIAGRAM Buck VBOOST VDD OTP Bandgap Vref VBOOSTM3V Current Sense CMP POR CTRL Digital control Bias OSC LEDCTRL1 LEDCTRL2 VBOOSTM3V Regulator VINBCK1 Predriver LBCKSW1 Current Sense CMP 5 V Input VINBCK2 RSTB CTRL SDI SCLK CSB Predriver 5 V Input/ OD Output LBCKSW2 SDO TEST TEST1 VLED2 LV IOs Temp VLED1 TEST2 ADC MUX Dividers EXPOSED PAD GND Figure 2. Block Diagram www.onsemi.com 3 VBOOST, VDD, VLEDx NCV78723 NC VINBCK1 NC LEDCTRL1 21 20 19 LBCKSW1 23 22 VLED1 SELF PROT PDMOS 12 6 LEDCTRL2 GND 11 5 NC TEST2 10 4 VINBCK2 VBOOST 9 3 NC VBOOSTM3V 8 2 LBCKSW2 TEST1 SELF PROT PDMOS 7 1 VLED2 TEST 24 ESD SCHEMATIC Figure 3. ESD Schematic www.onsemi.com 4 18 VDD 17 SDI 16 SCLK 15 CSB 14 SDO 13 RSTB NCV78723 PACKAGE AND PIN DESCRIPTION 24 23 22 21 20 19 VLED1 LBCKSW1 GND/NC VINBCK1 GND/NC LEDCTRL1 VDD 18 SDI 17 SCLK 16 VBOOST CSB 15 5 TEST2 SDO 14 6 GND RSTB 13 1 TEST 2 TEST1 3 VBOOSTM3V 4 VLED2 LBCKSW2 GND/NC VINBCK2 GND/NC LEDCTRL2 NCV78723 7 8 9 10 11 12 Figure 4. Pin Connections Table 2. PIN DESCRIPTION Pin No. Pin Name Description I/O Type 1 TEST Test Pin LV In 2 TEST1 Test Pin LV IN/OUT HV Tolerant 3 VBOOSTM3V VBOOSTM3V Regulator Output Pin HV OUT (Supply) 4 VBOOST Booster Input Voltage Pin HV Supply 5 TEST2 Test Pin LV IN/OUT HV Tolerant 6 GND Ground Ground 7 VLED2 LED String 2 Forward Voltage Sense Input HV IN 8 LBCKSW2 Buck 2 Switch Output HV OUT 9, 11, 20, 22 GND/NC GND/NC Connection in Application NC 10 VINBCK2 Buck 2 High Voltage Supply HV Supply 12 LEDCTRL2 LED String 2 Enable MV IN 13 RSTB External Reset Signal MV IN 14 SDO SPI Data Output MV Open-Drain 15 CSB SPI Chip Select (Chip Select Bar) MV IN 16 SCLK SPI Clock MV IN 17 SDI SPI Data Input MV IN 18 VDD 3 V Logic Supply LV Supply 19 LEDCTRL1 LED String 1 Enable MV IN 21 VINBCK1 Buck 1 High Voltage Supply HV Supply 23 LBCKSW1 Buck 1 Switch Output HV OUT 24 VLED1 LED String 1 Forward Voltage Sense Input HV IN www.onsemi.com 5 NCV78723 Table 3. ABSOLUTE MAXIMUM RATINGS Characteristic VBOOST Supply Voltage VINBCKx Supply Voltage (Note 4) VBOOSTM3V Supply Voltage (Note 5) VLED Sense Voltage Logic Supply Voltage (Note 6) Medium Voltage IO Pins (Note 7) Test Pins (Note 8) Symbol Minimum Maximum Unit VBOOST −0.3 +68 V VINBCKx Max of VBOOSTM3V − 0.3, −0.3 Min of VBOOST + 0.3, 68 V VBOOSTM3V Max of VBOOST − 3.6, −0.3 Min of VBOOST + 0.3, 68 V VLEDx −0.3 Min of VBOOST + 0.3, 68 V VDD −0.3 3.6 V IOMV −0.3 7.0 V TESTx −0.3 Min of VBOOST + 0.3, 68 V LBCKSWx −2.0 VINBCKx + 0.3 V VLED Sink/Source Current IVLEDx −30 30 mA Storage Temperature (Note 9) TSTRG −50 150 °C The Exposed Pad (Note 10) EXPAD GND − 0.3 GND + 0.3 V VESD_HBM VESD_CDM −2 −500 +2 +500 kV V Buck Switch Low Side (Note 4) Electrostatic Discharge on Component Level (Note 11) Human Body Model Charge Device Model Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. V(VINBCKx − LBCKSWx) < 70 V, the driver in off state. 5. The VBOOSTM3V regulator in off state. 6. Absolute maximum rating for pins: VDD, TEST. Also valid for relative difference VBOOST − VBOOSTM3V. 7. Absolute maximum rating for pins: SCLK, CSB, SDI, SDO, LEDCTRL1, LEDCTRL2, RSTB. The mC interface pins (the IOMV pins) accept 5 V while the device is in the power-off mode (VDD = 0 V). 8. Absolute maximum rating for pins: TEST1, TEST2. 9. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C. 10. The exposed pad must be hard wired to GND pin in an application to ensure both electrical and thermal connection. 11. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC*Q100*002 (EIA/JESD22*A114) ESD Charge Device Model tested per EIA/JESD22*C101 Latch-up Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78 Operating ranges define the limits for functional operation and parametric characteristics of the device. A mission profile (Note 12) is a substantial part of the operation conditions; hence the Customer must contact ON Semiconductor in order to mutually agree in writing on the allowed missions profile(s) in the application. Table 4. RECOMMENDED OPERATING RANGES Characteristic Boost Supply Voltage N78723−0 Device N78723−2 Device VINBCKx Supply Voltage (Note 13) Low Voltage Supply Buck Switch Output Current Symbol Min VBOOST Typ +8 +6 Max +67 +67 Unit V VINBCKx VBOOST − 0.1 VBOOST VBOOST + 0.1 V VDD 3.05 3.3 3.6 V 1.9 A I_LBCKSW Functional Operating Junction Temperature Range (Note 14) TJF −40 155 °C Parametric Operating Junction Temperature Range (Note 15) TJP −40 150 °C EXPOSED_PAD GND − 0.1 GND + 0.1 V The Exposed Pad Connection (Note 16) GND Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 12. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time, the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the device is operated by the customer, etc. No more than 100 cumulated hours in life time above TTW. 13. Hard connection of VINBCKx to VBOOST on PCB. 14. The circuit functionality is not guaranteed outside the functional operating junction temperature range. Also please note that the device is verified on bench for operation up to 170°C but that the production test guarantees 155°C only. 15. The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range. 16. The exposed pad must be hard wired to GND pin in an application to ensure both electrical and thermal connection. www.onsemi.com 6 NCV78723 Table 5. THERMAL RESISTANCE Characteristic Thermal Resistance Junction to Exposed Pad (Note 17) Package Symbol Min Typ Max Unit QFN24 5x5 Rthjp − 5 − °C/W 17. Includes also typical solder thickness under the Exposed Pad (EP). Table 6. ELECTRICAL CHARACTERISTICS (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Min Typ Max Unit I_VDD − − 6 mA POR Toggle Level on VDD Rising POR3V_H 2.7 − 3.05 V POR Toggle Level on VDD Falling POR3V_L 2.45 − 2.8 V POR3V_HYST 0.01 0.2 0.75 V OTP_UV 13 − 15 V OTP_UV_HYST 0.01 0.2 0.75 V −3.6 −3.3 −3.0 V Characteristic Symbol Condition VDD: 3 V LOW VOLTAGE ANALOG AND DIGITAL SUPPLY The VDD Current Consumption POR Hysteresis OTP UV Toggle Level on VBOOST OTP UV Toggle Level Hysteresis VBOOSTM3V: HIGH SIDE AUXILIARY SUPPLY VBSTM3 Regulator Output Voltage DC Output Current Consumption N78723−0 Device VBSTM3 Referenced to VBOOST M3V_IOUT mA N78723−2 Device − 5 − 5 28 (Note 18) 22.5 (Note 19) Output Current Limitation M3V_ILIM − − 200 mA VBSTM3 External Decoupling Cap. CVBSTM3V Referenced to VBOOST 0.3 − 2.2 mF VBSTM3 Ext. Decoupling Cap. ESR CVBSTM3V_ESR Referenced to VBOOST − − 200 mW VBOOST POR Level on N78723−2 Device (Note 20) M3V_VBSTPOR 3.5 − 5.5 V 8 10 12 MHz − 8 − OSC10M: SYSTEM OSCILLATOR CLOCK System Oscillator Frequency FOSC10M ADC FOR MEASURING VBOOST, VDD, VLED1, VLED2, TEMP ADC Resolution Nonlinearity Integral (INL) Differential (DNL) ADC_RES ADC_INL ADC_DNL Full Path Gain Error for Measurements of VDD, VLEDx, VBOOST ADC_GAINER Offset at Output of ADC ADC_OFFSET Time for 1 SAR Conversion ADC_CONV ADC Full Scale for VDD Measurement ADCFS_VDD Best Fitting Straight Line Method Full Conversion of 8 Bits Bits LSB −1.5 −2.0 − − +1.5 +2.0 −3.25 − 3.25 % −2 − 2 LSB 6.67 8 10 ms 3.87 4 4.13 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 18. VBOOST = 68 V, VLED1,2 = 34 V, fBUCK = 2 MHz, maximum total gate charge for both activated BUCK channels QGATE = 14 nC. 19. VBOOST = 68 V, VLED1,2 = 34 V, fBUCK = 1.61 MHz, maximum total gate charge for both activated BUCK channels QGATE = 14 nC. 20. On N78723−2 device, the Buck switch is switched off when VBOOST drops below M3V_VBSTPOR level. When VBOOST returns back above M3V_VBSTPOR level, normal operation is restored. www.onsemi.com 7 NCV78723 Table 6. ELECTRICAL CHARACTERISTICS (continued) (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Characteristic Symbol Condition Min Typ Max Unit The VLED Range Code is “00” The VLED Range Code is “01” The VLED Range Code is “10” The VLED Range Code is “11” 67.725 48.375 38.700 29.025 70 50 40 30 72.275 51.625 41.300 30.975 V 67.725 70 72.275 V ADC FOR MEASURING VBOOST, VDD, VLED1, VLED2, TEMP ADC Full Scale for VLEDx Measurement ADCFS_VLED00 ADCFS_VLED01 ADCFS_VLED10 ADCFS_VLED11 ADC Full Scale for VBOOST Measurement ADCFS_VBST ADC Full Scale for Temp. Measurement N78723−0 Device N78723−2 Device ADCFS_TEMP TSD Threshold Level °C 193.5 190 200 200 206.5 210 ADC_TSD ADC Measurement of Junction Temperature 163 169 175 °C Temperature Measurement Accuracy at Hot ADC_TEMPHOT t = 125°C −8 − 8 °C Temperature Measurement Accuracy at Cold ADC_TEMPCOLD t = −40°C −15 − 15 °C 210 280 − − 650 790 VLEDx Input Impedance N78723−0 Device N78723−2 Device VLED_RES kW BUCK REGULATOR − SWITCH On Resistance, Range 1 On Resistance at Hot, Range 1 On Resistance, Range 2 On Resistance at Hot, Range 2 On Resistance, Range 3 On Resistance at Hot, Range 3 On Resistance, Range 4 On Resistance at Hot, Range 4 Rdson1 At Room-Temperature, I(VINBCKx) = 0.18 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 5.2 W Rdson1_hot At Tj = 150 °C, I(VINBCKx) = 0.18 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 7.2 W Rdson2 At Room-Temperature, I(VINBCKx) = 0.375 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 2.6 W Rdson2_hot At Tj = 150 °C, I(VINBCKx) = 0.375 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 3.6 W Rdson3 At Room-Temperature, I(VINBCKx) = 0.75 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 1.3 W Rdson3_hot At Tj = 150 °C, I(VINBCKx) = 0.75 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 1.8 W Rdson4 At Room-Temperature, I(VINBCKx) = 1.5 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 0.65 W Rdson4_hot At Tj = 150 °C, I(VINBCKx) = 1.5 A, V(BOOST − VINBCKx) ≤ 0.2 V − − 0.9 W Switching Slope – ON Phase (Note 21) TRISE − 3 − V/ns Switching Slope – OFF Phase (Notes 21 and 22) TFALL − 3 − V/ns 23.905 28.125 32.344 mA BUCK REGULATOR − CURRENT REGULATION Current Sense Threshold Level, Range 1, Min Value ITHR1_000 [BUCKx_VTHR = 00000000] End of the BUCK ON-Phase Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 21. When DRV_SLOW_EN bit is 1 on N78723−2 device, the switching slopes are typically by 30% slower. 22. Falling switching slope depends on used current (range, current sense threshold level) and free-wheeling diode capacitance. www.onsemi.com 8 NCV78723 Table 6. ELECTRICAL CHARACTERISTICS (continued) (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Characteristic Symbol Condition Min Typ Max Unit BUCK REGULATOR − CURRENT REGULATION Current Sense Threshold Level, Range 1, Spec. Value ITHR1_110 [BUCKx_VTHR = 01101110] End of the BUCK ON-Phase. Min. Value for Specified Precision − 112.5 − mA Current Sense Threshold Level, Range 1, Max Value ITHR1_255 [BUCKx_VTHR = 11111111] End of the BUCK ON-Phase − 224.15 − mA Current Sense Threshold Level, Range 2, Min Value ITHR2_000 [BUCKx_VTHR = 00000000] End of the BUCK ON-Phase 47.813 56.25 64.688 mA Current Sense Threshold Level, Range 2, Spec. Value ITHR2_110 [BUCKx_VTHR = 01101110] End of the BUCK ON-phase. Min. Value for Specified Precision − 225 − mA Current Sense Threshold Level, Range 2, Max Value ITHR2_255 [BUCKx_VTHR = 11111111] End of the BUCK ON-Phase − 448.3 − mA Current Sense Threshold Level, Range 3, Min Value ITHR3_000 [BUCKx_VTHR = 00000000] End of the BUCK ON-Phase 95.625 112.5 129.375 mA Current Sense Threshold Level, Range 3, Spec. Value ITHR3_110 [BUCKx_VTHR = 01101110] End of the BUCK ON-Phase. Min. Value for Specified Precision − 450 − mA Current Sense Threshold Level, Range 3, Max Value ITHR3_255 [BUCKx_VTHR = 11111111] End of the BUCK ON-phase − 896.6 − mA Current Sense Threshold Level, Range 4, Min Value ITHR4_000 [BUCKx_VTHR = 00000000] End of the BUCK ON-Phase 191.25 225 258.75 mA Current Sense Threshold Level, Range 4, Spec. Value ITHR4_110 [BUCKx_VTHR = 01101110] End of the BUCK ON-Phase. Min. Value for Specified Precision − 900 − mA Current Sense Threshold Level, Range 4, Max Value ITHR4_255 [BUCKx_VTHR = 11111111] End of the BUCK ON-Phase − 1791.75 − mA Current Sense Threshold Increase per Code, Range 1 dITHR1 8 Bit, Linear Increase − 0.77 − mA Current Sense Threshold Increase per Code, Range 2 dITHR2 8 Bit, Linear Increase − 1.54 − mA Current Sense Threshold Increase per Code, Range 3 dITHR3 8 Bit, Linear Increase − 3.08 − mA Current Sense Threshold Increase per Code, Range 4 dITHR4 8 Bit, Linear Increase − 6.15 − mA Current Threshold Accuracy Only with Trimming Constant for the Highest Range (Note 23) N78723−0 N78723−2 ITHR_ERR_DD Specified for BUCKx_VTHR ≥ 01101110, without the Delta of the Trimming Code and without Temp. Compensation Current Threshold Accuracy without Temperature Compensation (Note 23) N78723−0 N78723−2 ITHR_ERR_D Current Threshold Accuracy (Note 23) N78723−0 N78723−2 ITHR_ERR Specified for BUCKx_VTHR ≥ 01101110, with the Delta of the Trimming Code and without Temp. Compensation Specified for BUCKx_VTHR ≥ 01101110, the Delta of the Trimming Code and Temp. Compensation % −8 −9 − − +8 +9 % −6 −7 − − +6 +7 % −3 −4 − − +3 +4 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 23. Measured as comparator DC threshold value, without comparator delay and switch falling slope. www.onsemi.com 9 NCV78723 Table 6. ELECTRICAL CHARACTERISTICS (continued) (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Characteristic Symbol Condition Min Typ Max Unit −10 − +10 mV BUCK REGULATOR − CURRENT REGULATION Offset of Peak Current Comparator on N78723−2 Device CMP_OFFSET Over-Current Detection Level, Range 1 OCDR1 Typ. 1.5 × ITHR1_255 286 − 388 mA Over-Current Detection Level, Range 2 OCDR2 Typ. 1.5 × ITHR2_255 573 − 776 mA Over-Current Detection Level, Range 3 OCDR3 Typ. 1.5 × ITHR3_255 1148 − 1553 mA Over-Current Detection Level, Range 4 OCDR4 Typ. 1.5 × ITHR4_255 2295 − 3105 mA Time Constant for Longest Off Time TC_00 [BUCKx_TOFF = 00000] − 50 − ms·V Time Constant for Shortest Off Time TC_31 [BUCKx_TOFF = 11111] − 5 − ms·V TOFF Time Relative Error TOFF_ERR TC = TOFF × VLED @ VLED > 2 V, TOFF > 350 ns −10 − +10 % TOFF Time Absolute Error TOFF_ERR_ABS TC = TOFF × VLED @ VLED > 2 V, TOFF ≤ 350 ns −35 − +35 ns Time Constant Decrease per Code dTC 5 Bits, Exponential Decrease − 7.16 − % Detection Level of VLED to be Too Low VLED_LMT 1.62 1.8 1.98 V TOFF Time for Low VLED Voltages N78723−0 Device N78723−2 Device (Note 24) TC_LOW The Zero-cross Detection Threshold Level (Note 25) VLED < VLED_LMT ms 78 72 105 105 120 140 TC_ZCD −0.125 − −0.005 V The Zero-cross Detection Filter Time TC_ZCD_FT 20 − 350 ns OpenLEDx Detection Time TON_OPEN 40 50 60 ms Buck Minimum TON Time TON_MIN For VINBCKx – LBCKSWx < 2.4 V, No Failure at LBCKSWx Pin 50 − 250 ns Delay from BUCKx ISENS Comparator Input Voltage Balance to BUCKx Switch Going OFF ISENSCMP_DEL ISENS Cmp. Over-Drive ramp > 1 mV/10 ns − 70 − ns 5 V TOLERANT DIGITAL INPUTS (SCLK, CSB, SDI, LEDCTRL1, LEDCTRL2, RSTB) High-Level Input Voltage VINHI 2 − − V Low-Level Input Voltage VINLO − − 0.8 V Pull Resistance (Note 26) LED PWM Propagation Delay (Note 27) Sampling Resolution RSTB Debouncer Time RPULL 40 − 160 kW 4.4 5.5 6.95 ms LEDCTRL_SR − 100 125 ns RSTB_DEB − 100 200 ns BUCKx_SW_DEL Activation Time of the BUCKx Switch from the LEDCTRLx Pin Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 24. Unless zero-cross detection stops the TOFF time on N78723−2 device. 25. The voltage at LBCKSWx pin when the comparator toggles, rising edge. 26. Pull down resistor (RPD) for RSTB, LEDCTRLx, SDI and SCLK, pull up resistor (RPU) for CSB to VDD. 27. Jitter is present due to the internal resynchronization. www.onsemi.com 10 NCV78723 Table 6. ELECTRICAL CHARACTERISTICS (continued) (All Min and Max parameters are guaranteed over full junction temperature (TJP) range (−40°C; 150°C), unless otherwise specified) Characteristic Symbol Condition Min Typ Max Unit 5 V TOLERANT OPEN-DRAIN DIGITAL OUTPUT (SDO) Low-Voltage Output Voltage VOUTLO IOUT = −10 mA (Current Flows into the Pin) − − 0.4 V Equivalent Output Resistance RDSON Low-Side Switch − 10 40 W SDO Pin Leakage Current SDO_ILEAK − − 2 mA SDO Pin Capacitance SDO_C − − 10 pF CLK to SDO Propagation Delay SDO_DL − − 60 ns Low-Side Switch Activation/ Deactivation Time; @ 1 kW to 5 V, 100 pF to GND, for Falling Edge V(SDO) Goes below 0.5 V 3 V DIGITAL INPUTS (TEST, TEST1, TEST2) High-Level Input Voltage VIN3HI 2.3 − − V Low-Level Input Voltage VIN3LO − − 0.8 V − − 60 kW Pull Resistance RPD3 Pull-Down Resistance SPI INTERFACE CSB Setup Time tCSS 0.5 − − ms CSB Hold Time tCSH 0.25 − − ms SCLK Low Time tWL 0.5 − − ms SCLK High Time tWH 0.5 − − ms Data-In (DIN) Setup Time, Valid Data before Rising Edge of CLK tSU 0.25 − − ms Data-In (DIN) Hold Time, Hold Data after Rising Edge of CLK tH 0.275 − − ms Output (DOUT) Disable Time (Note 28) tDIS 0.08 − 0.32 ms Output (DOUT) Valid (Note 28) tV1→0 − − 0.32 ms Output (DOUT) Valid (Note 29) tV0→1 − − 0.32 + t(RC) ms Output (DOUT) Hold Time tHO 0.01 − − ms CSB High Time tCS 1 − − ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 28. SDO low-side switch activation time. 29. Time depends on the SDO load and pull-up resistor. tCS Initial State of SCLK after CSB Falling Edge is Don’t Care, It Can be Low or High VIH CSB VIL tCSS tWH tWL tCSH VIH SCLK DIN VIL VIH DOUT VIL ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ tSU tH VIL VIH HI−Z DIN15 DOUT15 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ DIN14 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ tHO tV DOUT14 DIN13 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ DOUT13 Figure 5. SPI Communication Timing www.onsemi.com 11 DIN1 DOUT1 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ DIN0 ÉÉÉ ÉÉÉ ÉÉÉ tDIS DOUT0 HI−Z NCV78723 TYPICAL CHARACTERISTICS 2000 Accuracy (±3%/±6%/±8%) Guaranteed from VTHR Code 110 [dec] 1791.15 mA at VTHR = 255 in Range 4 1600 1400 +6.15 mA/step in Range 4 1200 ITHR = 4 1000 896.6 mA at VTHR = 255 in Range 3 225 mA at VTHR = 0 in Range 4 800 +3.08 mA/step in Range 3 112.5 mA at VTHR = 0 in Range 3 ITHR = 3 600 400 56.25 mA at VTHR = 0 in Range 2 ITHR = 2 448.3 mA at VTHR = 255 in Range 2 +1.54 mA/step in Range 2 224.15 mA at VTHR = 255 in Range 1 200 0 0 32 64 96 110 ITHR = 1 128 +0.77 mA/step in Range 1 160 192 224 256 28.125 mA at VTHR = 0 in Range 1 Buck VTHR Code (−) Figure 6. Buck Peak Current vs. Ranges and VTHR Code 120 Buck RDSON Relative to Value at 1505C (%) Buck Current Threshold (mA) 1800 100 80 60 40 20 0 −60 −40 −20 0 20 40 60 80 100 120 140 Temperature (5C) Figure 7. Typical Temperature Behavior of Buck Switch RDSON Relative to the Value at 1505C www.onsemi.com 12 160 NCV78723 TYPICAL CHARACTERISTICS 5.20 52.0 TOFF ⋅ VLED = 5 ms ⋅ V TOFF V VLED (ms V V) TOFF V VLED (ms V V) 5.15 5.10 5.05 5.00 51.0 TOFF ⋅ VLED = 50 ms ⋅ V 50.0 49.0 4.95 4.90 −40 0 40 80 48.0 −40 120 0 Temperature (5C) 40 80 120 Temperature (5C) Figure 8. Typical Temperature Dependency of TOFF V VLED Constant (Shortest TOFF V VLED = 5 ms V V and Longest TOFF V VLED = 50 ms V V) 140 120 −40°C Delay (ns) 100 25°C 80 150°C 60 40 20 0 0.001 0.01 0.1 1 Slope (A/ms) (for Range 4*) * In lower ranges, the same current slope (A/s) translates into a higher voltage slope (V/s) at the input of the comparator, because of the higher RDSON. Resulting equations for all ranges: Range 4: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope [A/ms, Range 4]) + 46 Range 3: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 2 [A/ms, Range 4]) + 46 Range 2: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 4 [A/ms, Range 4]) + 46 Range 1: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 8 [A/ms, Range 4]) + 46 Figure 9. Typical Comparator Delay vs. Slope www.onsemi.com 13 10 NCV78723 DETAILED OPERATING DESCRIPTION Supply Concept in General Two voltages have to be supplied to the NCV78723 chip – low voltage VDD logic supply and high voltage VBOOST for providing energy to the buck regulators. More detailed description follows. Buck Current Regulation Principle Each buck controls the individual inductor peak current (IBUCKpeak) and incorporates a constant ripple (DIBUCKpkpk) control circuit to ensure also stable average current through the LED string, independently from the string voltage. The buck average current is in fact described by the formula: VDD Supply The VDD supply is the low voltage digital and analog supply for the chip. NCV78723 does not contain internal VDD regulator and this voltage is supposed to be provided externally by a dedicated voltage regulator that fulfills specified voltage and current needs or can be supplied from the NCV78702/NCV78703 VDD pin. The Power-On-Reset circuit (POR) monitors the VDD voltage and RSTB pin to control the out-of-reset and reset entering state. At power-up, the chip will exit from reset state when VDD > POR3V_H and RSTB pin is in “log. 1”. No SPI communication is possible in reset state. DI BUCK I BUCK AVG + I BUCK peak * pkpk (eq. 1) 2 This is graphically exemplified by Figure 10. Buck Peak Current Buck Current Buck Average Current Buck Current Ripple = TOFF_V_BUCK / LBUCK TOFF time VBOOST Supply Figure 10. Buck Regulator Controlled Average Current The VBOOST supply voltage is the main high voltage supply for the chip. The voltage is supposed to be provided by booster chip such as NCV78702/NCV78703 or NCV878763 in an application. VINBCKx pins have to be connected by low impedance track to this supply to ensure proper buck performance. The VBOOST voltage is monitored by under-voltage comparator to check sufficient zapping voltage at VBOOST pin during OTP programming operation. The parameter IBUCKpeak is programmable through the device by means of the internal registers for range selection BUCKx_ISENS_THR[1:0] and code BUCKx_VTHR[7:0]. The formula that defines the total ripple current over the buck inductor is also hereby reported: DI BUCK pkpk VBOOSTM3V Supply + ^ The VBOOSTM3V is the high side auxiliary supply for the gate drive of the buck regulators’ integrated high-side P-MOSFET switches. This supply receives energy directly from the VBOOST pin. T OFF @ ǒV LED ) V DIODEǓ L BUCK T OFF @ V LED L BUCK + ^ (eq. 2) T OFF_V LED_i SPI L BUCK In the formula above, TOFF represents the buck switch off time, VLED is the LED voltage feedback sensed at the NCV78723 VLEDx pin and LBUCK is the buck inductance value. The parameter TOFF_VLED_iSPI is programmable by SPI (BUCKx_TOFF[4:0] register), with values related to Table 6 − Buck Regulator – Current Regulation. In order to achieve a constant ripple current value, the device varies the TOFF time inversely proportional to the VLED sensed at the device pin, according to the selected factor TOFF_VLED_iSPI. As a consequence to the constant ripple control and variable off time, the buck switching frequency depends on the boost voltage and LED voltage in the following way: Internal Clock Generation – OSC10M An internal RC clock named OSC10M is used to run all the digital functions in the chip. The clock is trimmed in the factory prior to delivery. Its accuracy is guaranteed under full operating conditions and is independent from external component selection (refer to Table 6 − OSC10M: System Oscillator Clock for details). All timings depend on OSC10M accuracy. Buck Regulator General f BUCK + The NCV78723 contains two high-current integrated buck current regulators, which are the sources for the LED strings. The bucks are powered from the external booster regulator. + www.onsemi.com 14 ǒVBOOST * VLEDǓ V BOOST ǒV BOOST * V LEDǓ V BOOST @ @ 1 + T OFF V LED T OFF_V LED_i SPI (eq. 3) NCV78723 The LED average current in time (DC) is equal to the buck time average current. Therefore, to achieve a given LED current target, it is sufficient to know the buck peak current and the buck current ripple. A rule of thumb is to count a minimum of 50% ripple reduction by means of the capacitor CBUCK and this is normally obtained with a low cost ceramic component ranging from 100 nF to 470 nF (such values are typically used at connector sides anyway, so this is included in a standard BOM). The following figure reports a typical example waveform: Figure 11. LED Current AC Components Filtered Out by Output Impedance (Oscilloscope Snapshot) The use of CBUCK is a cost effective way to improve EMC performances without the need to increase the value of VBOOST Supply VBOOSTM3V CM3V LBUCK, which would be certainly a far more expensive solution. VBOOST VBOOSTM3V Reg. POWER STAGE VINBCKx Driver LBCKSWx ISENSE/OC L D Digital Control LED String C VLEDx Constant Ripple Control Figure 12. Buck Regulator Circuit Diagram Buck Offset Compensation of the polarity change, the peak current is toggling between two threshold values, one high value and one low, as shown in the picture below. The related sub-harmonic frequency (half the buck switching frequency) will appear in the spectrum. This has to be taken into account from EMC point of view. The use of the offset cancellation is very effective in case of high precision levels for low currents. The N78723−2 device features a peak current offset compensation that can be disabled by the corresponding BUCKx_OFF_CMP_DIS SPI bit. When this bit is “0” (offset compensation is enabled), the offset changes polarity each buck period, so that the average effect over time on the peak current is minimized (ideally zero). As a consequence Figure 13. Buck Offset Compensation Feature www.onsemi.com 15 NCV78723 SW Compensation of the Buck Current Accuracy In order to ensure buck current accuracy as specified in Table 6 − Buck Regulator – Current Regulation, set of constants trimmed during manufacturing process is available. Microcontroller should use them in the following way: To Reach ±8% (±9% for N78723−2) Accuracy (±6% for Range 4) Over Whole Temperature Operating Range: All ranges: BUCKx_ISENS_TRIM[6:0] = BUCKx_ISENS_RNG[6:0] BUCKx_ISENS_RNG[6:0] is trimming constant for the highest current range (Range 4) at hot temperature. BUCKx_ISENS_RNG[6:0] constant is loaded into BUCKx_ISENS_TRIM[6:0] register automatically after the reset of the device. To Reach ±6% (±7% for N78723−2) Accuracy Over Whole Temperature Operating Range: BUCKx_ISENS_Dx[3:0] registers, meaning delta of the trimming constant with respect to the higher current range at hot temperature, have to be used. Trimming constant for the particular range at hot temperature can be then calculated as: Range 4: BUCKx_R4_trim_hot = BUCKx_ISENS_RNG[6:0], Range 3: BUCKx_R3_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0], Range 2: BUCKx_R2_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0] + BUCKx_ISENS_D2[3:0], Range 1: BUCKx_R1_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0] + BUCKx_ISENS_D2[3:0] + BUCKx_ISENS_D1[3:0], where: delta of the trimming constant BUCKx_ISENS_Dx[3:0] is signed, coded as two’s complement. Range of this constant is decadic , binary . Calculated trimming constant has to be then written into trimming SPI register: BUCKx_ISENS_TRIM[6:0] = BUCKx_Ry_trim_hot To Reach ±3% (±4% for N78723−2) Accuracy Over Whole Temperature Operating Range: In addition to BUCKx_ISENS_Dx[3:0] registers, the BUCK_ISENS_TCx[3:0] registers, meaning temperature coefficients for the appropriate ranges, have to be used. When TC_VERSION = 0, trimming value for a certain temperature should be calculated as: Range 4: BUCKx_R4_trim = BUCKx_R4_trim_hot + kL3 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 3: BUCKx_R3_trim = BUCKx_R3_trim_hot + kL2 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 2: BUCKx_R2_trim = BUCKx_R2_trim_hot + kL1 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 1: BUCKx_R1_trim = BUCKx_R1_trim_hot + kL0 · (Tj – Thot) + kQ · (Tj – Thot) 2, When TC_VERSION = 1, trimming value for a certain temperature should be calculated as: Range 4: BUCK2_R4_trim = BUCK2_R4_trim_hot + kL3 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 3: BUCK2_R3_trim = BUCK2_R3_trim_hot + kL3 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 2: BUCK2_R2_trim = BUCK2_R2_trim_hot + kL2 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 1: BUCK2_R1_trim = BUCK2_R1_trim_hot + kL2 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 4: BUCK1_R4_trim = BUCK1_R4_trim_hot + kL1 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 3: BUCK1_R3_trim = BUCK1_R3_trim_hot + kL1 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 2: BUCK1_R2_trim = BUCK1_R2_trim_hot + kL0 · (Tj – Thot) + kQ · (Tj – Thot) 2, Range 1: BUCK1_R1_trim = BUCK1_R1_trim_hot + kL0 · (Tj – Thot) + kQ · (Tj – Thot) 2, where: buck temperature coefficient BUCK_ISENS_TCx[3:0] is signed, coded as two’s complement. Range of this constant is decadic , binary , kLx is linear coefficient for each current range calculated: kLx = (BUCK_ISENS_TCx[3:0] – kQ · (170°C)2)/(−170°C) [code/°C] when TC_VERSION = 0 kLx is linear coefficient for each current range calculated: kLx = (BUCK_ISENS_TCx[3:0] – kQ · (200°C)2)/(−200°C) [code/°C] when TC_VERSION = 1 kQ is quadratic constant for all current ranges: kQ = 2.18 · 10−4 [code/(°C)2] Tj is junction temperature in °C calculated from VTEMP[7:0] SPI register value according to the equation defined in chapter ADC: Device Temperature ADC: VTEMP Thot temperature is constant equal to 125°C when TC_VERSION = 0 Thot temperature is constant equal to 155°C when TC_VERSION = 1. www.onsemi.com 16 NCV78723 Calculated trimming constant has to be then written into trimming SPI register: BUCKx_ISENS_TRIM[6:0] = BUCKx_Ry_trim Note: The BUCKx_ISENS_TRIM[6:0] SPI register allows compensation of the peak current app. in range ±40 % from actual value according to the following equation: IBUCKx = (ITHRx_000 + dITHRx · BUCKx_VTHR[7:0]) · (1 + 0.4 · ((BUCKx_ISENS_TRIM[6:0] − 63)/63)), where: ITHRx_000 is current for VTHR code 0 in ITHRx range (see Table 6 − Buck Regulator – Current Regulation), dITHRx code step in range ITHRx (see Table 6 − Buck Regulator – Current Regulation). Paralleling the Bucks for Higher Current Capability logic status of the LEDCTRLx pins. The only difference is the controlled phase shift of typical 5.5 ms (Table 6 − 5 V Tolerant Digital Inputs) that allows synchronized measurements of the VLEDx pins via the ADC (see dedicated section for more details). As the phase shift is applied both to rising edges and falling edges, with a very limited jitter, the PWM duty cycle is not affected. Apart from the phase shift and the system clock OSC10M, there is no limitation to the PWM duty cycle values or resolutions at the bucks, which is a copy of the reference provided at the inputs. Different buck channels can be paralleled at the module output (after the buck inductors) for higher current capability on a unique channel, summing up together the individual DC currents. Buck Overcurrent Protection Being a current regulator, the NCV78723 buck is by nature preventing overcurrent in all normal situations. However, in order to protect the system from overcurrent even in case of failures, protection mechanism is available. This protection is based on internal sensing over the buck switch: when the peak current rises above the maximum limit (OCDRx level, see see Table 6 − Buck Regulator – Current Regulation), an internal counter starts to increment at each period, until the count written in BUCKx_OC_OCCMP_THR[1:0] + 1 is attained. The count is reset if the current drops below OCDRx level or the buck channel is disabled and also at each dimming cycle. From the moment the count is reached onwards, the buck is kept continuously off, until the SPI error flag OCLEDx is read. After reading the flag, the buck channel “x” is automatically re-enabled and will try to regulate the current again. ZOOM: Buck Inductor Switching Current DIM_DUTY = DIM_TON / DIM_T = DIM_TON ⋅ F DIM_TON DIM_T Figure 14. Buck Current Digital or PWM Dimming ADC General The built-in analog to digital converter (ADC) is an 8-bit successive approximation register (SAR). This embedded peripheral can be used to provide the following measurements to the external Micro Controller Unit (MCU): • VBOOST Voltage: Sampled at the VBOOST Pin • VDD Voltage: Sampled at the VDD Pin • VLED1ON, VLED2ON Voltages • VLED1 and VLED2 Voltages • VTEMP Measurement (Chip Temperature) Dimming The NCV78723 supports both analog and digital dimming (or so called PWM dimming). Analog dimming is performed by controlling the LED amplitude current during operation. This can be done by means of changing the peak current level and/or the TOFF_VLED_iSPI constants by SPI commands (see Buck Regulator section). In this section, we only describe PWM dimming as this is the preferred method to maintain the desired LED color temperature for a given current rating. In PWM dimming, the LED current waveform frequency is constant and the duty cycle is set according to the required light intensity. In order to avoid the beats effect, the dimming frequency should be set at “high enough” values, typically above 300 Hz. PWM dimming is controlled externally by means of LEDCTRLx inputs. The internal NCV78723 ADC state machine samples all the above channels automatically, taking care for setting the analog MUX and storing the converted values in memory. The external MCU can read out all ADC measured values via the SPI interface, in order to take application specific decisions. Please note that none of the MCU SPI commands interfere with the internal ADC state machine sample and conversion operations: the MCU will always get the last available data at the moment of the register read. The state machine sampling and conversion scheme is represented in the figure below. Digital Dimming The two independent control inputs LEDCTRLx handle the dimming signals for the related channel “x”. In digital dimming, the buck activation is transparently linked to the www.onsemi.com 17 NCV78723 default selection is given to channel “1”. Then an internal flag keeps priority tracking, toggling at each time between channels pre-selection. Therefore, up to two dimming periods will be required to obtain a full measurement update of the two channels. This is not considered however a limitation, as typical periods for dimming signals are in the order of 1 ms period, thus allowing very fast failure detection. A flow chart referring to the ADC interrupts is also displayed. VDD Sample & Convert VBOOST Sample & Convert VTEMP Sample & Convert Update LED_SEL_DUR Count; When Counter Ripples, Trigger VLEDx Interrupt for Once VBOOST Sample & Convert Interrupts Enabled? Figure 15. ADC Sample and Conversion Main Sequence YES VLEDx Synchronization Signal? NO YES NO VLEDx Sample & Convert Referring to the figure above, the typical rate for a full SAR plus digital conversion per channel is 8 ms (Table 6 − ADC for Measuring VBOOST, VDD, VLED1, VLED2, TEMP). For instance, each new VBOOST ADC converted sample occurs at 16 ms typical rate, whereas for both the VDD and VTEMP channel the sampling rate is typically 32 ms, that is to say a complete cycle of the depicted sequence. This time is referred to as TADC_SEQ. If the SPI setting LED_SEL_DUR[8:0] is not zero, then interrupts for the VLEDx measurements are allowed at the points marked with a rhombus, with a minimum cadence corresponding to the number of the elapsed ADC sequences (forced interrupt). In formulas: T VLEDx_INT_Forced + LED_SEL_DUR[8 : 0] @ T ADC_SEQ Toggle Channel “x” Selection In Case of Interrupt on Second Channel do Not Serve Immediately and Complete the ADC Sequence First Proceed to Next Step in the ADC Sequence Figure 16. ADC VLEDx Interrupt Sequence (eq. 4) All NCV78723 ADC registers data integrity is protected by ODD parity on the bit 8 (that is to say the 9th bit if counting from the LSbit named “0”). Please refer to the SPI map section for further details. In general, prior to the forced interrupt status, the VLEDxON ADC interrupts are generated when a falling edge on the control line for the buck channel “x” is detected by the device. In case of digital dimming, this interrupt start signal corresponds to the LEDCTRLx falling edge together with a controlled phase delay (Table 6 − 5 V Tolerant Digital Inputs). The purpose of the phase delay is to allow completion the ongoing ADC conversion before starting the one linked to the VLEDx interrupt: if at the moment of the conversion LEDCTRLx pin is logic high, then the updated registers are VLEDxON[7:0] and VLEDx[7:0]; otherwise, if LEDCTRLx pin is logic low, the only register refreshed is VLEDx[7:0]. This mechanism is handled automatically by the NCV78723 logic without need of intervention from the user, thus drastically reducing the MCU cycles and embedded firmware and CPU cycles overhead that would be otherwise required. To avoid loss of data linked to the ADC main sequence, one LED channel is served at a time also when interrupt requests from both channels are received in a row and a full sequence is required to go through to enable a new interrupt VLEDx. In addition, possible conflicts are solved by using a defined priority (channel pre-selection). Out of reset, the Logic Supply Voltage ADC: VDD The logic supply voltage is sampled at VDD pin. The (8-bit) conversion ratio is 4/255 (V/dec) = 0.0157 (V/dec) typical. The converted value can be found in the SPI register VDD[7:0], protected with ODD parity bit. Boost Voltage ADC: VBOOST This measurement refers to the boost voltage at the VBOOST pin, with an 8 bit conversion ratio of 70/255 (V/dec) = 0.274 (V/dec) typical, result can be found inside the SPI register VBOOST[7:0]. The value is protected by ODD parity bit. This measurement can be used by the MCU for diagnostics and booster control loop monitoring. Device Temperature ADC: VTEMP By means of the VTEMP measurement, the MCU can monitor the device junction temperature (TJ) over time. The conversion formula is: T J + (VTEMP[7 : 0] * 50.5)ń0.805 www.onsemi.com 18 (eq. 5) NCV78723 VTEMP[7:0] is the value read out directly from the related 8bit-SPI register (please refer to the SPI map). The value is also used internally by the device for the thermal warning and thermal shutdown functions. More details on these two can be found in the dedicated sections in this document. The value is protected by ODD parity bit. LED String Voltages ADC: VLEDx, VLEDxON The voltage at the pins VLEDx (1, 2) is measured. There are 4 ranges available, that can be selected by means of ADC_VLEDx_RNG_SEL[1:0] register, to obtain higher resolution for LED voltage measurement. Conversion ratios in dependency on selected range are: 0x0: 70/255 (V/dec) = 0.274 (V/dec); 0x1: 50/255 (V/dec) = 0.196 (V/dec); 0x2: 40/255 (V/dec) = 0.157 (V/dec); 0x3: 30/255 (V/dec) = 0.118 (V/dec). • • This information, found in registers VLEDxON[7:0] and VLEDx[7:0], can be used by the MCU to infer about the LED string status, for example, individual shorted LEDs. As for the other ADC registers, the values are protected by ODD parity. Please note that in the case of constant LEDCTRLx inputs and no dimming (in other words dimming duty cycle equals to 0% or 100%) the VLEDx interrupt is forced with a rate equal to TVLEDx_INT_forced, given in the ADC general section. This feature can be exploited by MCU embedded algorithm diagnostics to read the LED channels voltage even when in OFF state, before module outputs activation (module startup pre-check). • Diagnostics The NCV78723 features a wide range of embedded diagnostic features. Their description follows. Please also refer to the previous SPI section for more details. • Diagnostic Description • Thermal • Warning: this mechanism detects a user-programmable junction temperature which is in principle close, but lower, to the chip maximum allowed, thus providing the information that some action (power de-rating) is required to prevent overheating that would cause Thermal Shutdown. A typical power de-rating technique consists in reducing the output dimming duty cycle in function of the temperature: the higher the temperature above the thermal warning, the lower the duty cycle. The thermal warning flag (TW) is given in status register 0x14 and is latched. When VTEMP[7:0] raises to or above THERMAL_WARNING_THR[7:0] threshold, the TW flag is set. At power up the default thermal warning threshold is typically 159°C (SPI code 179). Thermal Shutdown: this safety mechanism intends to protect the device from damage caused by overheating, by disabling the both buck channels. The diagnostic is displayed per means of the TSD bit in status register 0x14 • • • (latched). Once occurred, the thermal shutdown condition is exited when the temperature drops below the thermal warning level, thus providing hysteresis for thermal shutdown recovery process. Outputs are re-enabled automatically if BUCKx_TSD_AUT_RCRV_EN = 1, or they are re-enabled by rising edge on BUCKx_EN if BUCKx_TSD_AUT_RCRV_EN = 0. The application thermal design should be made as such to avoid the thermal shutdown in the worst case conditions. The thermal shutdown level is not user programmable and is factory trimmed (see ADC_TSD in Table 6 − Buck Regulator – Switch). SPI Error: in case of SPI communication errors the SPIERR bit in status register 0x14 is set. The bit is latched. For more details, please refer to section “SPI protocol: Framing and Parity Error”. Open LEDx String: individual open LED diagnostic flags indicate whether the “x” string is detected open. The detection is based on a counter overflow of typical 50 ms when the related channel is activated. Both OPENLED1 and OPENLED2 flags (latched) are contained in status register 0x13. Please note that the open detection does not disable the buck channel(s). Short LEDx String: a short circuit detection is available independently for each LED channel per means of the flag SHORTLEDx (latched, status register 0x13). The detection is based on the voltage measured at the VLEDx pins via a dedicated internal comparator: when the voltage drops below the VLED_LMT minimum threshold (typical 1.8 V, see Table 6 − Buck Regulator – Current Regulation) the related flag is set. Together with the detection, a fixed TOFF is used. On N78723−2 device, TOFF time is terminated immediately when the inductor current reaches zero. This improves the dimming behavior via external short switches (pixel control). Overcurrent on Channel x: this diagnostics protects the LEDx and the buck channel x electronics from overcurrent. As the overcurrent is detected, the OCLEDx flag (latched, status register 0x13) is raised and the related buck channel is disabled. More details about the detection mechanisms and parameters are given in section “Buck Overcurrent Protection”. Buckx Status: register BUCKx_STATUS shows the actual status of Buckx output. When BUCKx_STATUS is 1, the corresponding output regulates current to the LED. LEDCTRLx Pin Status: SPI registers LED1VAL resp. LED2VAL indicate the actual logic level of the debounced LEDCTRLx pins. These signals follow the output of 200 ns digital debouncers implemented on LEDCTRLx pins. Buckx Running at Minimum TON Time: register BUCKx_MIN_TON (latched) indicates that minimal TON time is detected on the corresponding channel. It is clear by read flag. This information can be used for www.onsemi.com 19 NCV78723 • detection of transition period during which the BUCKx output current decreases due to the change of BUCKx_VTHR code or BUCKx_ISENS_THR range. Buckx TON Time Duration: SPI register BUCKx_TON_DUR[7:0] reflects the last measured Buckx TON time (1LSB = 200 ns) on the corresponding channel. When Buckx runs with TON time < typ. 200 ns, the BUCKx_TON_DUR[7:0] SPI register returns value 0x00. When Buckx is stopped, the • BUCKx_TON_DUR[7:0] register keeps the last measured TON time. HW Reset: the out of reset condition is reported through the HWR bit (latched). This bit is set only at each Power On Reset (POR) and indicates the device is ready to operate. A short summary table of the main diagnostic bits related to the LED outputs follows. Table 7. LED OUTPUT DIAGNOSTIC SUMMARY Diagnose Flag Description Detection Level LED Output Latched TW Thermal Warning SPI Register Programmable Not Disabled (If No TSD, otherwise Disabled) Yes TSD Thermal Shutdown Factory Trimmed Disabled (Automatically Re-Enabled when Temp Falls below TW and BUCKx_TSD_AUT_RCVR_EN = 1) Yes SPIERR SPI Error (See SPI Section) Not Disabled Yes OPENLEDx LED String Open Circuit Buck on Time > TON_OPEN Not Disabled Yes SHORTLEDx LED String Short Circuit VLEDx < VLED_LMT Not Disabled (Fixed Buck TOFF or Zero Cross TOFF Applied when output is On) Yes OCLEDx LED String Overcurrent Ibuckx > OCDR{1..4} Disabled Yes Mode = RESET (0) Transition Priority (0) − Highest (1) (2) (3) − Lowest TSD = 1 (1) OFF LED is Off OCLED = 1 or BUCKx_EN = 0 (2) OCLED = 0 and BUCKx_EN = 1 (2) DIMMING NORMAL Mode: LED is On if LEDCTRLx = 1 FSO/STANDALONE Mode: LED is On BUCKx_TSD_AUT_RCVR_EN = 1 or Rising Edge on BUCKx_EN Detected (3) TSD = 1 (1) RECOVERY (BUCKx_TSD_AUT_RCVR_EN = 1 or Rising Edge on BUCKx_EN Detected) and (OCLED = 1 or BUCKx_EN = 0) (2) TSD = 1 (1) LED is Off TSD LED is Off VTEMP < THERMAL_WARNING_THR(1) Figure 17. LED Dimming State Diagram www.onsemi.com 20 NCV78723 Functional Mode Description Overview of all functional modes is in accordance to the state diagram on Figure 18. Individual states are described below. Transition Condition (Priority Level) Action Executed when Transition is Performed Transition Priority: (0) − Highest (1) (2) − Lowest POR (0) RESET SPI Disabled Dimming Disabled HWR:=1 RSTB = 0 (1) RSTB = 1 (1) INIT SPI Disabled Dimming Disabled OTP Refresh Ongoing RSTB = 0 and (FSO_MD = 000 or 001 or 110 or 111) (1) RSTB = 0 (1) 150 ms Timeout Expired (2) SPI Pre-Load from OTPs when FSO_MD = 001 or 100 or 101 or 110 or 111 (FSO_MD = 110 or 111) and OTP_CUST_LOCK = 1 (2) SPI Pre-Load from OTPs FSO:=1 NORMAL SPI Enabled Dimming: LEDCTRLx RSTB = 0 and (FSO_MD = 010 or 011 or 100 or 101) and OTP_CUST_LOCK = 1 (2) SPI Pre-Load from OTPs FSO:=1 FSO_MD = 000 or 001 (2) RSTB = 1 or (FSO_MD = 000 or 001) (1) FSO SPI Enabled when FSO_MD = 010 or 100 Dimming: BUCKx_EN Figure 18. Functional Modes State Diagram www.onsemi.com 21 STANDALONE SPI Disabled when FSO_MD = 110 Dimming: BUCKx_EN NCV78723 Reset BUCKx_ISENS_TRIM[6:0] register is preloaded from corresponding BUCKx_ISENS_RNG[6:0] register. In FSO (entered via falling edge on RSTB pin) and Stand-Alone modes, BUCK1_EN & BUCK2_EN are controlled from SPI register map (SPI registers are updated from OTP’s after entrance into these modes). BUCK1_EN and BUCK2_EN are supposed to be set ‘1’ for the BUCKx operation in the FSO/stand-alone mode. When control registers are pre-loaded from OTP’s after POR and FSO mode is not entered (valid for FSO_MD[2:0] = 100 or 101), BUCK1_EN and BUCK2_EN are kept inactive (‘0’) until the first valid SPI operation is finished to avoid potential activation of buck regulators immediately after POR (to prevent undefined state of LEDCTRLx pins in case MCU leaves POR later than NCV78723). In FSO and Stand-Alone modes, the logic level at LEDCTRLx pins is ignored and digital PWM dimming with LEDCTRLx pins is not available. The outputs can be dimmed only by means of BUCKx_EN register. A falling edge on RSTB pin may trigger either entrance into FSO mode or reset in dependency on FSO_MD[2:0] register value. Please refer to Table 8 and Figure 18 for more details. Once FSO mode is entered via falling edge on RSTB pin, reset function of RSTB pin is blocked until FSO mode is exited. FSO mode can be exited by the rising edge on RSTB pin or by writing FSO_MD[2:0] = 000 or 001 (possible only in FSO modes, where SPI control register update is allowed: FSO_MD[2:0] = 011 or 101). In stand-alone mode (FSO_MD[2:0] = 110 or 111), RSTB has always reset functionality. During entrance into FSO mode, value of FSO_MD[2:0] SPI register (preloaded from OTP at power-up only) is latched into internal register and all FSO related functions are then controlled according to it. Purpose is to avoid the reset of the device when FSO mode is active and FSO_MD[2:0] is changed to value corresponding to stand-alone mode, where RSTB pin has reset functionality. The internal register is cleared after POR or when FSO mode is exited. Asynchronous reset is caused either by POR (POR always causes asynchronous reset − transition to reset state) or by falling edge on RSTB pin (in normal/stand-alone mode, when FSO_MD[2:0] = 000 or 001 or 110 or 111). Init and Normal Mode Normal mode is entered through Init state after internal delay of 150 ms. In Init state, OTP refresh is performed. If OTP bits for FSO_MD[2:0] register and OTP Lock Bit are programmed, transition to FSO/SA mode is possible. FSO/Stand-Alone Mode FSO (Fail-Safe Operation)/Stand-Alone modes can be used for two main purposes: • Default power-up operation of the chip (Stand-Alone functionality without external microcontroller or preloading of the registers with default content for default operation before microcontroller starts sending SPI commands for chip settings) • Fail-Safe functionality (chip functionality definition in fail-safe mode when the external microcontroller functionality is not guaranteed) FSO/stand-alone function is controlled according to Table 8. Entrance into FSO/Stand-alone mode is possible only after customer OTP zapping when OTP Lock Bit is set. After FSO mode activation, the FSO bit in status register is set. FSO register is cleared by read register. When FSO/Stand-Alone mode is activated, content of the following SPI registers is preloaded from OTP memory: BUCK1_VTHR[7:0], BUCK1_ISENS_THR[1:0], BUCK2_VTHR[7:0], BUCK2_ISENS_THR[1:0], BUCK1_TOFF[4:0], BUCK2_TOFF[4:0], BUCK1_EN, BUCK2_EN, FSO_MD[2:0], BUCK1_TSD_AUT_RCVR_EN, BUCK2_TSD_AUT_RCVR_EN, BUCKx_OC_OCCMP_THR[1:0]]. www.onsemi.com 22 NCV78723 RSTB in Normal or Stand-Alone Mode PORB (Internal) RSTB Normal Mode (SPI Possible) Power-Up Reset Mode (No SPI) Normal Mode Reset Mode Possible OTP Pre-Load Possible OTP Pre-Load RSTB iN FSO Mode PORB (Internal) RSTB Normal Mode (SPI Possible) Power-Up OTP Pre-Load FSO Mode (SPI Possible/No SPI) OTP Pre-Load Normal Mode FSO Mode OTP Pre-Load Figure 19. RSTB Pin Functionality in Normal, Stand-Alone and FSO Modes Table 8. FSO MODES FSO_MD[2:0] Description 000b = 0 FSO Mode Disabled, Registers are Loaded with Safe Value = 0x00h after POR, Default • After the reset, control registers are loaded with 0x00h value. • Entrance into FSO mode is not possible unless dedicated SPI write command to change FSO_MD[2:0] value is sent • RSTB pin has reset functionality • LEDCTRLx pins are functional (buck enable/disable, digital PWM dimming available) 001b = 1 FSO Mode Disabled, Registers are Loaded with Data from OTP Memory after POR • After the reset, control registers are loaded with data stored in OTP memory (device’s OTP memory has to be programmed, OTP Lock Bit has to be set). It reduces number of SPI transfers needed to configure the device after the reset. • Entrance into FSO mode is not possible • RSTB pin has reset functionality • LEDCTRLx pins are functional (buck enable/disable, digital PWM dimming available) 010b = 2 FSO Entered after Falling Edge on RSTB Pin, Registers (except FSO_MD[2:0]) are Loaded with Safe Value = 0x00h after POR • After FSO mode activation, control registers are loaded with data stored in OTP memory. • SPI register update (SPI write/read operation) in FSO mode is disabled (SPI write operation is blocked; clearing of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set). • RSTB pin serves to enter/exit FSO mode. • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). 011b = 3 FSO Entered after Falling Edge on RSTB Pin, Registers (except FSO_MD[2:0]) are Loaded with Safe Value = 0x00h after POR • After FSO mode activation, control registers are loaded with data stored in OTP memory. • SPI register update (SPI write/read operation) in FSO mode is enabled • FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001 • RSTB pins serves to enter/exit FSO mode. • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). 100b = 4 FSO Entered after Falling Edge on RSTB Pin, Registers are Loaded with Data from OTP Memory after POR • After FSO mode activation, control registers are loaded with data stored in OTP memory. • SPI register update (SPI write/read operation) in FSO mode is disabled (SPI write operation is blocked; clearing of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set). • RSTB pin serves to enter/exit FSO mode. • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). www.onsemi.com 23 NCV78723 Table 8. FSO MODES (continued) FSO_MD[2:0] Description 101b = 5 FSO Entered after Falling Edge on RSTB Pin, Registers are Loaded with Data from OTP Memory after POR • After FSO mode activation, control registers are loaded with data stored in OTP memory. • SPI register update (SPI write/read operation) in FSO mode is enabled • FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001 • RSTB pin serves to enter/exit FSO mode. • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). 110b = 6 SA (Stand-Alone)/FSO Entered after POR (RSTB Pin Rising Edge), Registers are Loaded with Data from OTP Memory • After FSO/SA mode activation, control registers are loaded with data from OTP memory • SPI register update (SPI write/read operation) in SA/FSO mode is disabled (SPI write operation is blocked; clearing of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set). • RSTB pin has reset functionality • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). 111b = 7 SA (Stand-Alone)/FSO Entered after POR (RSTB Pin Rising Edge), Registers are Loaded with Data from OTP Memory • After SA/FSO mode activation, control registers are loaded with data from OTP memory • SPI register update (SPI write/read operation) in SA/FSO mode is enabled • FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001 • RSTB pin has reset functionality • LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM dimming not available). SPI Interface General A slave or chip select line (CSB) allows individual selection of a slave SPI device in a time multiplexed multiple-slave system. The CSB line is active low. If an NCV78723 is not selected, SDO is in high impedance state and it does not interfere with SPI bus activities. Since the NCV78723 always clocks data out on the falling edge and samples data in on rising edge of clock, the MCU SPI port must be configured to match this operation. The implemented SPI allows connection to multiple slaves by means of star connection (CSB per slave) or by means of daisy chain. An SPI star connection requires a bus = (3 + N) total lines, where N is the number of Slaves used, the SPI frame length is 16 bits per communication. The serial peripheral interface (SPI) is used to allow an external microcontroller (MCU) to communicate with the device. NCV78723 acts always as a slave and it cannot initiate any transmission. The operation of the device is configured and controlled by means of SPI registers, which are observable for read and/or write from the master. The NCV78723 SPI transfer size is 16 bits. During an SPI transfer, the data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCLK) synchronizes shifting and sampling of the information on the two serial data lines: SDO and SDI. The SDO signal is the output from the Slave (NCV78723), and the SDI signal is the output from the Master. SCB1 SCB2 MCU (SPI Master) SCBN MCU (SPI Master) NCV78723 Dev#1 (SPI Slave) MOSI MISO SDO 1 SDI2 NCV78723 Dev#2 (SPI Slave) SDO 2 SDIN NCV78723 Dev#N (SPI Slave) SDON NCV78723 Dev#1 (SPI Slave) NCV78723 Dev#2 (SPI Slave) NCV78723 Dev#N (SPI Slave) Figure 20. SPI Star vs. Daisy Chain Connection SPI Daisy Chain Mode SPI daisy chain connection bus width is always four lines independently on the number of slaves. However, the SPI transfer frame length will be a multiple of the base frame length so N × 16 bits per communication: the data will be interpreted and read in by the devices at the moment the CSB rises. A diagram showing the data transfer between devices in daisy chain connection is given further: CMDx represents www.onsemi.com 24 NCV78723 Device in the same time replies to the master (on the SDO): • If the previous command was a write and no SPI error had occurred, a copy of the command, address and data written fields, • If the previous command was a read, the response frame summarizes the address used and an overall diagnostic check (copy of the main detected errors, see Figures 22 and 23 for details), • In case of previous SPI error or after power-on-reset, only the MSB bit will be 1, followed by zeros. the 16-bit command frame on the data input line transmitted by the Master, shifting via the chips’ shift registers through the daisy chain. The chips interpret the command once the chip select line rises. CS Commands in the Shift Registers are Executed on Rising Edge of CS SCLK 16 Cycles 16 Cycles 16 Cycles DIN1 CMD1 CMD2 CMD3 x CMD1 CMD2 x x x x DOUT1 DIN2 DOUT2 DIN3 DOUT3 1 If parity bit in the frame is wrong, device will not perform command and flag will be set. CMD1 The frame protocol for the read operation: x Figure 21. SPI Daisy Chain Data Shift between Slaves. The Symbol ‘x’ Represents the Previous Content of the SPI Shift Register Buffer Read; CMD = ‘0’ High Low The NCV78723 default power up communication mode is “star”. In order to enable daisy chain mode, a multiple of 16 bits clock cycles must be sent to the devices, while the SDI line is left to zero. NOTE: SDI SDO To come back to star mode the NOP register (address 0x0000) must be written with all ones, with the proper data parity bit and parity framing bit: see SPI protocol for details about parity and write operation. C A A A A A M P 4 3 2 1 0 D S P I E R R B U C K O C L E D 2 L E D 1 T S D T W Low D D D D D D D D D D 9 8 7 6 5 4 3 2 1 0 SCLK Low Figure 23. SPI Read Frame Referring to the previous picture, the read frame coming from the master (into the SDI) is composed from the following fields: • Bit[15] (MSB): CMD bit = 0 for read operation, • Bits[14:10]: 5 bits READ ADDRESS field, • Bit[10]: frame parity bit. It is ODD parity formed by the negated XOR of all other bits in the frame, • Bits [8:0]: 9 bits zeroes field. High Low SDO SCLK C A A A A D D D D D D D D D D P M 3 2 1 0 9 8 7 6 5 4 3 2 1 0 D S P I E R R C A A A A D D D D D D D D D D M 3 2 1 0 9 8 7 6 5 4 3 2 1 0 D S P I E R R C A A A A A 0 1 1 1 P M 4 3 2 1 0 D B U C K O C L E D 2 L E D 1 T S D T W Data from address A [4:0] shall be returned P = not(CMD xor A4 xor A3 xor A2 xor A1 xor A0) Two types of SPI commands (to SDI pin of NCV78723) from the micro controller can be distinguished: “Write to a control register” and “Read from register (control or status)”. The frame protocol for the write operation: SDI Low HIGH−Z SPI Transfer Format Write; CMD = ‘1’ LED1 = OPENLED1 or SHORTLED1 LED2 = OPENLED2 or SHORTLED2 BUCKOC = OCLED1 or OCLED2 −> immediate value of STATUS BITS; Dedicated SPI READ Command of the STATUS Register has to be performed to clear the value of read−by−clear STATUS bits Low Previous SPI WRITE command resp. “SPIERR + 0x000hex” after POR or SPI Command HIGH PARITY/FRAMING Error −Z Device in the same frame provides to the master (on the SDO) data from the required address (in frame response), thus achieving the lowest communication latency. Previous SPI READ command & NCV78723 status bits resp. “SPIERR + 0x000hex” after POR or SPI Command Low PARITY/FRAMING Error SPI Framing and Parity Error SPI communication framing error is detected by the NCV78723 in the following situations: • Not an integer multiple of 16 CLK pulses are received during the active-low CSB signal; • LSB bits (8..0) of a read command are not all zero; • SPI parity errors, either on write or read operation. P = not (CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor D6 xor D5 xor D4 xor D 3 xor D2 xor D1 xor D0) Figure 22. SPI Write Frame Referring to the previous picture, the write frame coming from the master (into the SDI) is composed from the following fields: • Bit[15] (MSB): CMD bit = 1 for write operation, • Bits[14:11]: 4 bits WRITE ADDRESS field, • Bit[10]: frame parity bit. It is ODD parity formed by the negated XOR of all other bits in the frame, • Bits[9:0]: 10 bit DATA to write Once an SPI error occurs, the flag can be reset only by reading the status register in which it is contained (using in the read frame the right communication parity bit). www.onsemi.com 25 NCV78723 SPI ADDRESS MAP Table 9. NCV78723 SPI ADDRESS MAP ADDR R/W 0x00 NA Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x01 R/W BUCK1_ISENS_THR[1:0] 0x02 R/W BUCK2_ISENS_THR[1:0] 0x03 R/W 0x04 R/W 0x05 R/W BUCK1_ TSD_AUT_ RCVR_EN 0x06 R/W VTEMP_ OFF_COMP ODD PAR (Note 30) 0x07 R/W 0x08 R/W VTEMP_OFF_COMP[5:3] (Note 30) 0x09 R/W ADC_VLED1_RNG_ SEL[1:0] 0x0A R 0x0 ODD PARITY VLED1ON[7:0] Bit 2 Bit 1 Bit 0 BUCK1_EN BUCK2_EN NOP Register (Read/Write Operation Ignored) BUCK1_VTHR[7:0] BUCK2_VTHR[7:0] BUCK1_TOFF[4:0] BUCK1_OFF_ BUCK2_OFF_ CMP_DIS CMP_DIS (Note 31) (Note 31) DRV_ SLOW_EN (Note 31) BUCK2_TOFF[4:0] BUCKx_OC_OCCMP_ THR[1:0] FSO_MD[2:0] BUCK2_ TSD_AUT_ RCVR_EN THERMAL_WARNING_THR[7:0] LED_SEL_DUR[8:0] VTEMP_OFF_COMP[2:0] (Note 30) BUCK1_ISENS_TRIM[6:0] BUCK2_ISENS_TRIM[6:0] ADC_VLED2_RNG_ SEL[1:0] OTP_BIAS_H OTP_BIAS_L OTP_ADDR[1:0] 0x0B R 0x0 ODD PARITY VLED2ON[7:0] 0x0C R 0x0 ODD PARITY VLED1[7:0] 0x0D R 0x0 ODD PARITY VLED2[7:0] 0x0E R 0x0 ODD PARITY VTEMP[7:0] 0x0F R 0x0 ODD PARITY VBOOST[7:0] 0x10 R 0x0 ODD PARITY VDD[7:0] BUCK1_TON_DUR[7:0] OTP_OPERATION[1:0] 0x11 R 0x0 ODD PARITY 0x12 R 0x0 ODD PARITY 0x13 R 0x0 ODD PARITY 0x14 R 0x0 ODD PARITY 0x15 R 0x0 ODD PARITY 0x16 R 0x0 ODD PARITY 0x0 0x17 R 0x0 ODD PARITY 0x0 0x18 R 0x0 ODD PARITY BUCK2_ISENS_D1[3:0] BUCK1_ISENS_D1[3:0] 0x19 R 0x0 ODD PARITY BUCK2_ISENS_D2[3:0] BUCK1_ISENS_D2[3:0] 0x1A R 0x0 ODD PARITY BUCK2_ISENS_D3[3:0] BUCK1_ISENS_D3[3:0] 0x1B R 0x0 ODD PARITY BUCK_ISENS_TC1[3:0] BUCK_ISENS_TC0[3:0] 0x1C R 0x0 ODD PARITY BUCK_ISENS_TC3[3:0] BUCK_ISENS_TC2[3:0] 0x1D R 0x0 ODD PARITY 0x1E R 0x1F R OTHER R BUCK2_TON_DUR[7:0] 0x0 OTP_FAIL FSO OPENLED1 SHORTLED1 OCLED1 HWR LED1VAL LED2VAL SPIERR TSD TW OTP_ ACTIVE BUCK1_ MIN_TON BUCK2_ MIN_TON BUCK1_ STATUS BUCK2_ STATUS 0x0 OPENLED2 SHORTLED2 OCLED2 BUCK1_ISENS_RNG[6:0] BUCK2_ISENS_RNG[6:0] 0x0 TC_VERSION OTP_DATA[9:0] 0x0 REVID[7:0] 0x0 30. Read Only. 31. Available only on N78723−2 device. www.onsemi.com 26 NCV78723 Table 10. BIT DEFINITION Symbol MAP Position Description REGISTER 0X00 (CR): NOP REGISTER, RESET VALUE (POR) = 00000000002 NOP Bits [9:0] – ADDR_0x00 NOP Register (Read/Write Operation Ignored) REGISTER 0X01 (CR): BUCK 1 PEAK CURRENT SETTINGS, RESET VALUE (POR) = 00000000002 BUCK1_ISENS_THR[1:0] Bits [9:8] – ADDR_0x01 Peak Current: Selection of the Range 1, 2, 3 or 4 BUCK1_VTHR[7:0] Bits [7:0] – ADDR_0x01 Peak Current Comparator Threshold Value REGISTER 0X02 (CR): BUCK 2 PEAK CURRENT SETTINGS, RESET VALUE (POR) = 00000000002 BUCK2_ISENS_THR[1:0] Bits [9:8] – ADDR_0x02 Peak Current: Selection of the Range 1, 2, 3 or 4 BUCK2_VTHR[7:0] Bits [7:0] – ADDR_0x02 Peak Current Comparator Threshold Value REGISTER 0X03 (CR): BUCK 1 AND 2 TOFF SETTINGS, RESET VALUE (POR) = 00000000002 BUCK1_TOFF[4:0] Bits [9:5] – ADDR_0x03 Buck 1 TOFF·VLED Constant Settings BUCK2_TOFF[4:0] Bits [4:0] – ADDR_0x03 Buck 2 TOFF·VLED Constant Settings REGISTER 0X04 (CR): BUCK SETTINGS, RESET VALUE (POR) = 00000000002 BUCK1_OFF_CMP_DIS Bit 9 – ADDR_0x04 Buck 1 Offset Cancellation Disable BUCK2_OFF_CMP_DIS Bit 8 – ADDR_0x04 Buck 2 Offset Cancellation Disable DRV_SLOW_EN Bit 7 – ADDR_0x04 Slow Driver Slope Enable BUCKx_OC_OCCMP_THR[1:0] Bits [6:5] – ADDR_0x04 Overcurrent Detection Settings FSO_MD[2:0] Bits [4:2] – ADDR_0x04 FSO Mode Selection BUCK1_EN Bit 1 – ADDR_0x04 Buck Regulator Channel 1 Enable Bit BUCK2_EN Bit 0 – ADDR_0x04 Buck Regulator Channel 2 Enable Bit REGISTER 0X05 (CR): BUCK SETTINGS, RESET VALUE (POR) = 00101100112 BUCK1_TSD_AUT_RCVR_EN Bit 9 – ADDR_0x05 Buck 1 Automatic Recovery after TSD BUCK2_TSD_AUT_RCVR_EN Bit 8 – ADDR_0x05 Buck 2 Automatic Recovery after TSD THERMAL_WARNING_THR[7:0] Bits [7:0] – ADDR_0x05 Thermal Warning Threshold Settings REGISTER 0X06 (CR): BUCK SETTINGS, RESET VALUE (POR) = X0000000002 VTEMP_OFF_COMP ODD PAR. Bit 9 – ADDR_0x06 ADC VTEMP Trimming Parity Bit LED_SEL_DUR[8:0] Bits [8:0] – ADDR_0x06 VLED Measurement Settings REGISTER 0X07 (CR): BUCK SETTINGS, RESET VALUE (POR) = XXX00000002 VTEMP_OFF_COMP[2:0] Bits [9:7] – ADDR_0x07 ADC VTEMP Trimming BUCK1_ISENS_TRIM[6:0] Bits [6:0] – ADDR_0x07 Compensation of the Buck 1 Peak Current REGISTER 0X08 (CR): BUCK SETTINGS, RESET VALUE (POR) = XXX00000002 VTEMP_OFF_COMP[5:3] Bits [9:7] – ADDR_0x08 ADC VTEMP Trimming BUCK2_ISENS_TRIM[6:0] Bits [6:0] – ADDR_0x08 Compensation of the Buck 2 Peak Current REGISTER 0X09 (CR): BUCK SETTINGS, RESET VALUE (POR) = 00000000002 ADC_VLED1_RNG_SEL[1:0] Bits [9:8] – ADDR_0x09 Range Select for VLED ADC, Channel 1 ADC_VLED2_RNG_SEL[1:0] Bits [7:6] – ADDR_0x09 Range Select for VLED ADC, Channel 2 OTP_BIAS_H Bit 5 – ADDR_0x09 OTP Bias High OTP_BIAS_L Bit 4 – ADDR_0x09 OTP Bias Low OTP_ADDR[1:0] Bits [3:2] – ADDR_0x09 OTP Address OTP_OPERATION[1:0] Bits [1:0] – ADDR_0x09 OTP Operation REGISTER 0X0A (SR): VLED1ON, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x0A Odd Parity over Data VLED1ON[7:0] Bits [7:0] – ADDR_0x0A Output of VLED 1 ADC REGISTER 0X0B (SR): VLED2ON, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x0B Odd Parity over Data VLED2ON[7:0] Bits [7:0] – ADDR_0x0B Output of VLED 2 ADC www.onsemi.com 27 NCV78723 Table 10. BIT DEFINITION (continued) Symbol MAP Position Description REGISTER 0X0C (SR): VLED1, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x0C Odd Parity over Data VLED1[7:0] Bits [7:0] – ADDR_0x0C Output of VLED 1 ADC REGISTER 0X0D (SR): VLED2, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x0D Odd Parity over Data VLED2[7:0] Bits [7:0] – ADDR_0x0D Output of VLED 2 ADC REGISTER 0X0E (SR): VTEMP, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x0E Odd Parity over Data VTEMP[7:0] Bits [7:0] – ADDR_0x0E Output of VTEMP ADC REGISTER 0X0F (SR): VBOOST, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x0F Odd Parity over Data VBOOST[7:0] Bits [7:0] – ADDR_0x0F Output of VBOOST ADC REGISTER 0X10 (SR): VDD, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x10 Odd Parity over Data VDD[7:0] Bits [7:0] – ADDR_0x10 Output of VDD ADC REGISTER 0X11 (SR): BUCK1_TON_DUR, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x11 Odd Parity over Data BUCK1_TON_DUR[7:0] Bits [7:0] – ADDR_0x11 Buck 1 Ton Duration REGISTER 0X12 (SR): BUCK2_TON_DUR, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x12 Odd Parity over Data BUCK2_TON_DUR[7:0] Bits [7:0] – ADDR_0x12 Buck 2 Ton Duration REGISTER 0X13 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 0X000X00X02 ODD PARITY Bit 8 – ADDR_0x13 Odd Parity over Data OPENLED1 Bit 5 – ADDR_0x13 Buck 1 Open LED Flag, Latched SHORTLED1 Bit 4 – ADDR_0x13 Buck 1 Short LED Flag, Latched OCLED1 Bit 3 – ADDR_0x13 Buck 1 Overcurrent Flag, Latched OPENLED2 Bit 2 – ADDR_0x13 Buck 2 Open LED Flag, Latched SHORTLED2 Bit 1 – ADDR_0x13 Buck 2 Short LED Flag, Latched OCLED2 Bit 0 – ADDR_0x13 Buck 2 Overcurrent Flag, Latched REGISTER 0X14 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 0X001XXXXX2 ODD PARITY Bit 8 – ADDR_0x14 Odd Parity over Data OTP_FAIL Bit 7 – ADDR_0x14 OTP Failure Flag, Latched FSO Bit 6 – ADDR_0x14 Chip being in FSO Mode Flag, Non-Latched HWR Bit 5 – ADDR_0x14 Hardware Reset Flag, Latched LED1VAL Bit 4 – ADDR_0x14 Actual Status of LEDCTRL1 Pin, Non-Latched LED2VAL Bit 3 – ADDR_0x14 Actual Status of LEDCTRL2 Pin, Non-Latched SPIERR Bit 2 – ADDR_0x14 SPI Error Flag, Latched TSD Bit 1 – ADDR_0x14 Thermal Shutdown Flag, Latched TW Bit 0 – ADDR_0x14 Thermal Warning Flag, Latched REGISTER 0X15 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 01000000002 ODD PARITY Bit 8 – ADDR_0x15 Odd Parity over Data OTP_ACTIVE Bit 4 – ADDR_0x15 OTP Active Flag, Non-Latched BUCK1_MIN_TON Bit 3 – ADDR_0x15 Minimal Ton Detected on Buck 1, Latched BUCK2_MIN_TON Bit 2 – ADDR_0x15 Minimal Ton Detected on Buck 2, Latched BUCK1_STATUS Bit 1 – ADDR_0x15 Actual Status of Buck 1 Regulator, Non-Latched BUCK2_STATUS Bit 0 – ADDR_0x15 Actual Status of Buck 2 Regulator, Non-Latched www.onsemi.com 28 NCV78723 Table 10. BIT DEFINITION (continued) Symbol MAP Position Description REGISTER 0X16: BUCK TRIMMING, RESET VALUE (POR) = 0X0XXXXXXX2 ODD PARITY Bit 8 – ADDR_0x16 Odd Parity over Data BUCK1_ISENS_RNG[6:0] Bits [6:0] – ADDR_0x16 Trimming Constant for Highest Range on Hot for Buck 1 Peak Current REGISTER 0X17: BUCK TRIMMING, RESET VALUE (POR) = 0X0XXXXXXX2 ODD PARITY Bit 8 – ADDR_0x17 Odd Parity over Data BUCK2_ISENS_RNG[6:0] Bits [6:0] – ADDR_0x17 Trimming Constant for Highest Range on Hot for Buck 2 Peak Current REGISTER 0X18: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x18 Odd Parity over Data BUCK2_ISENS_D1[3:0] Bits [7:4] – ADDR_0x18 Delta Trimming Constant for Buck 2 Peak Current BUCK1_ISENS_D1[3:0] Bits [3:0] – ADDR_0x18 Delta Trimming Constant for Buck 1 Peak Current REGISTER 0X19: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x19 Odd Parity over Data BUCK2_ISENS_D2[3:0] Bits [7:4] – ADDR_0x19 Delta Trimming Constant for Buck 2 Peak Current BUCK1_ISENS_D2[3:0] Bits [3:0] – ADDR_0x19 Delta Trimming Constant for Buck 1 Peak Current REGISTER 0X1A: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x1A Odd Parity over Data BUCK2_ISENS_D3[3:0] Bits [7:4] – ADDR_0x1A Delta Trimming Constant for Buck 2 Peak Current BUCK1_ISENS_D3[3:0] Bits [3:0] – ADDR_0x1A Delta Trimming Constant for Buck 1 Peak Current REGISTER 0X1B: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x1B Odd Parity over Data BUCK_ISENS_TC1[3:0] Bits [7:4] – ADDR_0x1B Temperature Coefficient Trimming Constant for Buck Peak Current BUCK_ISENS_TC0[3:0] Bits [3:0] – ADDR_0x1B Temperature Coefficient Trimming Constant for Buck Peak Current REGISTER 0X1C: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX2 ODD PARITY Bit 8 – ADDR_0x1C Odd Parity over Data BUCK_ISENS_TC3[3:0] Bits [7:4] – ADDR_0x1C Temperature Coefficient Trimming Constant for Buck Peak Current BUCK_ISENS_TC2[3:0] Bits [3:0] – ADDR_0x1C Temperature Coefficient Trimming Constant for Buck Peak Current REGISTER 0X1D: BUCK TRIMMING, RESET VALUE (POR) = 0X0000000X2 ODD PARITY Bit 8 – ADDR_0x1D Odd Parity over Data TC_VERSION Bit 0 – ADDR_0x1D Usage of BUCK_ISENS_TCx[3:0] Constants REGISTER 0X1E: OTP DATA, RESET VALUE (POR) = 00000000002 OTP_DATA[9:0] Bits [9:0] – ADDR_0x1E OTP Data REGISTER 0X1F: REVID, RESET VALUE (POR) = 00000XXXXXXX2 REVID[7:0] Bits [7:0] – ADDR_0x1F Revision ID • SPI_REVID[4:3]: Full Mask Version • SPI_REVID[2]: N78723−0/N78723−2 Distinguishing POR values of status registers are shown in situation that FSO mode is not entered after POR. All latched flags are “cleared by read”. ‘x’ means that value after reset is defined during reset phase (diagnostics) or is trimmed during manufacturing process. SPI register SPI_REVID[7:0] is used to track the silicon version, following encoding mechanism is used: • SPI_REVID[7:6]: Constant 00 [binary] • SPI_REVID[5]: 713/723 Distinguishing Bit (REVID[5] = 0 means 723) • Bit (REVID[2] = 0 means N78723−0) SPI_REVID[1:0]: Metal Tune REVID[7:0] for N78723−0 device is 11hex (723 = 0, Full Mask Version = 2, N78723−0 = 0, Metal Tune = 1) REVID[7:0] for N78723−2 device is 14hex (723 = 0, Full Mask Version = 2, N78723−2 = 1, Metal Tune = 0) www.onsemi.com 29 NCV78723 OTP MEMORY Description The OTP (Once Time Programmable) memory contains 40 bits which bear the most important application dependant parameters and is user programmable via SPI interface. The programming of these bits is typically done at the end of the module manufacturing line. OTP memory serves to store configuration data for Fail-Safe or Stand-Alone functionality or default configuration of the chip after power-up. The OTP bits can be programmed only once, this is ensured by dedicated OTP Lock Bit which is set during programming. Table 11) and OTP Lock Bit are programmed into OTP memory. OTP Zap operation is allowed to be performed only once − when OTP Lock Bit is unprogrammed SPI status bit OTP_ACTIVE is set to “log. 1” when an OTP operation is in progress. OTP Programming Procedure Following procedure should be applied to program OTP memory: • VBOOST voltage has to be in range between 15 V and 20 V with current capability at least 50 mA • VDD voltage has to be kept in range for normal mode operation • The junction temperature has to stay in range from 0°C to 125°C during OTP programming • SPI registers listed in Table 11 have to be written with required content • Content of the SPI registers (those listed in Table 11) is programmed into the OTP memory by OTP_OPERATION[1:0] = 0x2 SPI write command. OTP Lock Bit is programmed automatically at the same time to prevent any further OTP programming Table 11. OTP MAP OTP Bits Connection to SPI Register OTP[7:0] BUCK1_VTHR[7:0] OTP[9:8] BUCK1_ISENS_THR[1:0] OTP[17:10] BUCK2_VTHR[7:0] OTP[19:18] BUCK2_ISENS_THR[1:0] OTP[24:20] BUCK1_TOFF[4:0] OTP[29:25] BUCK2_TOFF[4:0] OTP[30] BUCK1_EN OTP[31] BUCK2_EN OTP[34:32] FSO_MD[2:0] OTP[35] BUCK1_TSD_AUT_RCR_EN OTP[36] BUCK2_TSD_AUT_RCR_EN OTP[38:37] BUCKx_OC_OCCMP_THR[1:0] OTP[39] OTP Lock Bit OTP Programming Verification OTP_FAIL bit in the SPI status register is set when VBOOST under-voltage (see OTP_UV parameter) is detected during OTP Zap operation. It is clear by read flag. The OTP_BIAS_H and OTP_BIAS_L registers are used to check proper OTP programming. After OTP programming, the OTP content has to be the same as programmed when OTP is read with OTP_BIAS_H = 1 and OTP_BIAS_L = 1. Following procedure should be applied to verify OTP content: • VDD voltage has to be kept in range for normal mode operation • Write SPI registers OTP_BIAS_L = 1 and OTP_BIAS_H = 0 • Write SPI register OTP_OPERATION[1:0] = 0x1 (OTP Refresh) for all OTP_ADDR[1:0] values and check corresponding OTP_DATA[9:0] content which has to match with previously programmed data • Write SPI registers OTP_BIAS_L = 0 and OTP_BIAS_H = 1 • Write SPI register OTP_OPERATION[1:0] = 0x1 (OTP Refresh) for all OTP_ADDR[1:0] values and check corresponding OTP_DATA[9:0] content which has to match with previously programmed data • Programming is considered as successful when no mismatch is observed The OTP bits addressed by SPI register OTP_ADDR[1:0] are accessible (read only) in the SPI register OTP_DATA[9:0] after OTP Refresh operation (OTP_OPERATION[1:0] = 0x1) in the following way: OTP_ADDR[1:0] = 0x0: OTP_DATA[9:0] = OTP[9:0] OTP_ADDR[1:0] = 0x1: OTP_DATA[9:0] = OTP[19:10] OTP_ADDR[1:0] = 0x2: OTP_DATA[9:0] = OTP[29:20] OTP_ADDR[1:0] = 0x3: OTP_DATA[9:0] = OTP[39:30] OTP Operations The NCV78723 supports following operations with OTP memory: • OTP_OPERATION[1:0] = 0x0 or 0x3: NOP (no operation) • OTP_OPERATION[1:0] = 0x1: OTP Refresh – refresh of the whole OTP memory (40 bits). Data addressed by SPI register OTP_ADDR[1:0] are available in SPI register OTP_DATA[9:0] after the end of OTP Refresh operation • OTP_OPERATION[1:0] = 0x2: OTP Zap – data from SPI register (those listed in www.onsemi.com 30 NCV78723 Table 12. ORDERING INFORMATION Marking Package* Shipping† NCV78723MW0CR2G N78723−0 QFN24 5 × 5 with Wettable Flank (Pb-Free) 5,000 / Tape & Reel NCV78723MW0R2G N78723−0 QFN24 5 × 5 with Wettable Flank (Pb-Free) 5,000 / Tape & Reel NCV78723MW2R2G N78723−2 QFNW24 5 × 5 with Step-cut Wettable Flank (Pb-Free) 5,000 / Tape & Reel Device** **NCV78723MW2 & NCV78723MW0 have different package mold compound. Please contact ON Semiconductor for technical details. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 31 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFNW24 5x5, 0.65P CASE 484AF ISSUE A DATE 07 AUG 2018 1 24 SCALE 2:1 PIN ONE LOCATION D A B ÉÉÉ ÉÉÉ ÉÉÉ L3 L L3 L ALTERNATE CONSTRUCTION E DETAIL A EXPOSED COPPER TOP VIEW A4 A1 DETAIL B 0.10 C C C 0.08 C 0.10 D2 DETAIL A A1 A4 A A3 A1 SIDE VIEW NOTE 4 C SEATING PLANE PLATING ALTERNATE CONSTRUCTION DETAIL B C A B M A4 L 24X 7 0.10 M C A B 13 K 1 19 e e/2 BOTTOM VIEW PLATED SURFACES L3 SECTION C−C E2 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 24X b 0.10 M C A B 0.05 M C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT 5.30 3.66 24X 0.62 1 5.30 3.66 DIM A A1 A3 A4 b D D2 E E2 e K L L3 MILLIMETERS MIN NOM MAX 0.80 0.85 0.90 −−− −−− 0.05 0.20 REF 0.10 −−− −−− 0.25 0.30 0.35 4.90 5.00 5.10 3.40 3.50 3.60 4.90 5.00 5.10 3.40 3.50 3.60 0.65 BSC 0.35 REF 0.30 0.40 0.50 0.05 REF GENERIC MARKING DIAGRAM* XXXXXXXX XXXXXXXX AWLYYWWG G XXXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 24X 0.65 PITCH 0.40 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON30093G QFNW24 5x5, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN24 5x5, 0.65P CASE 485CS ISSUE O DATE 24 OCT 2012 1 24 SCALE 2:1 PIN ONE REFERENCE 2X ÉÉ ÉÉ L L A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C EXPOSED Cu 2X 0.15 C TOP VIEW A DETAIL B 0.10 C (A3) A1 A3 0.08 C NOTE 4 C SIDE VIEW 0.10 D2 DETAIL A M M A1 GENERIC MARKING DIAGRAM* C A B 0.10 13 DETAIL B ALTERNATE CONSTRUCTION SEATING PLANE K 7 ÉÉÉ ÉÉÉ MOLD CMPD 1 C A B XXXXXXXX XXXXXXXX AWLYYWWG G E2 1 24 24X L 24X e e/2 b 0.10 M C A B 0.05 M C XXXXX A WL YY WW G NOTE 3 BOTTOM VIEW SOLDERING FOOTPRINT* 5.30 0.62 3.66 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 24X 3.66 MILLIMETERS MIN MAX 0.80 0.90 −−− 0.05 0.20 REF 0.25 0.35 5.00 BSC 3.40 3.60 5.00 BSC 3.40 3.60 0.65 BSC 0.20 MIN 0.30 0.50 −−− 0.15 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 5.30 0.65 PITCH 24X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON84592E QFN24, 5x5, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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