NCV84160DR2G

Self Protected Very Low Iq High Side Driver with Analog Current Sense NCV84160 The NCV84160 is a fully protected single channel high side driver that can be used to switch a wide variety of loads, such as bulbs, solenoids, and other actuators. The device incorporates advanced protection features such as active inrush current management, over−temperature shutdown with automatic restart and an overvoltage active clamp. A dedicated Current Sense pin provides precision analog current monitoring of the output as well as fault indication of short to VD, short circuit to ground and ON and OFF state open load detection. An active high Current Sense Disable pin allows all diagnostic and current sense features to be disabled. www.onsemi.com 8 1 SOIC−8 CASE 751 STYLE 11 Features • • • • • • • • • • • • • • • • • MARKING DIAGRAM Short Circuit Protection with Inrush Current Management CMOS (3 V / 5 V) Compatible Control Input Very Low Standby Current Very Low Current Sense Leakage Proportional Load Current Sense Current Sense Disable Off State Open Load Detection Output Short to VD Detection Overload and Short to Ground Indication Thermal Shutdown with Automatic Restart Undervoltage Shutdown Integrated Clamp for Inductive Switching Loss of Ground and Loss of VD Protection ESD Protection Reverse Battery Protection AEC−Q100 Qualified This is a Pb−Free Device 8 84160 ALYWG G 1 84160 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS GND Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial 1 VD IN OUT CS OUT CS_DIS VD (Top View) ORDERING INFORMATION FEATURE SUMMARY Max Supply Voltage VD 41 V Operating Voltage Range VD 4.5 to 28 V RDSon (max) TJ = 25°C RON 160 mW Output Current Limit (typical) ILIM 12 A ID(off) 0.01 mA OFF−state Supply Current (typical) © Semiconductor Components Industries, LLC, 2017 November, 2019 − Rev. 5 1 Device Package Shipping† NCV84160DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NCV84160/D NCV84160 Block Diagram & Pin Configuration VD Overvoltage Protection Undervoltage Protection IN Output Clamping Regulated Charge Pump Current Limit CS_DIS Overtemperature and Power Protection OFF State Open Load Detection Analog Fault OUT Control CS Logic Current Sense GND Figure 1. Block Diagram Table 1. SO8 PACKAGE PIN DESCRIPTION Pin # Symbol Description 1 GND 2 IN Logic Level Input 3 CS Analog Current Sense Output 4 CS_DIS Ground Active High Current Sense Disable 5 VD 6 OUT Supply Voltage Output 7 OUT Output 8 VD Supply Voltage www.onsemi.com 2 NCV84160 ID V DS IIN VD IN IOUT OUT ICS_DIS CS ICSD VD CS_DIS VIN VOUT GND VCS VCS_DIS IGND Figure 2. Voltage and Current Conventions Table 2. Connection suggestions for unused and or unconnected pins Connection Input Output Current Sense Current Sense Enable Floating X X Not Allowed X To Ground Through 10 kΩ resistor Not Allowed Through 1 kΩ Resistor Through 10 kΩ resistor 1 IN 2 CS 3 CS_DIS 4 NCV84160 GND Figure 3. Pin Configuration (top view) www.onsemi.com 3 8 VD 7 OUT 6 OUT 5 VD NCV84160 ELECTRICAL SPECIFICATIONS Table 3. MAXIMUM RATINGS Value Rating DC Supply Voltage Peak Transient Input Voltage (Load Dump 46 V, VD = 14 V, ISO16750−2: 2012 Test B) Input Voltage Symbol Min Max Unit VD −0.3 41 V 48 V 10 V Vpeak VIN −10 IIN −5 Input Current 5 mA −200 mA Internally Limited A 200 mA VD−41 VD V VCS_DIS −10 10 V ICS_DIS −5 5 mA Reverse Ground Pin Current IGND Output Current (Note 2) IOUT CS Current ICS CS Voltage VCS CS_DIS Voltage CS_DIS Current Power Dissipation Tc = 25°C (Note 4) Ptot Electrostatic Discharge (HBM Model 100 pF / 1500 W) Input Current Sense Current Sense Enable Output VD Charge Device Model CDM−AEC−Q100−011 VESD Single Pulse Inductive Load Switching Energy (Note 1) (L = 8 mH, Vbat = 13.5 V; IL = 3.08 A, TJ_Start = 150°C) EAS Operating Junction Temperature Storage Temperature −6 1.49 W DC 4 3 4 3 3 kV kV kV kV kV 750 V 53.71 mJ TJ −40 +150 °C Tstorage −55 +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Not subjected to production testing 2. Reverse Output current has to be limited by the load to stay within absolute maximum ratings and thermal performance. Table 4. THERMAL RESISTANCE RATINGS Parameter Thermal Resistance Junction−to−Lead Junction−to−Ambient (Note 3) Junction−to−Ambient (Note 4) Symbol Max. Value RqJL RqJA RqJA 32 98 84 3. Min. pad size, 1 oz. Cu with backside plane covered with 1 oz. Cu (backside plane not electrically connected). 4. 2 cm2 pad size, 1 oz. Cu with backside plane covered with 1 oz. Cu (backside plane not electrically connected). www.onsemi.com 4 Units °C/W NCV84160 ELECTRICAL CHARACTERISTICS (8 ≤ VD ≤ 28 V; −40°C < TJ < 150°C unless otherwise specified) Table 5. POWER Value Rating Symbol Conditions Min Typ Max Unit 4.5 − 28 V 4.5 V Operating Supply Voltage VD Undervoltage Shutdown VUV 3.5 Undervoltage Shutdown Hysteresis VUV_HYST 0.5 On Resistance Supply Current (Note 5) Output Leakage Current RON ID IL(OFF) V IOUT = 1 A, TJ = 25°C 160 IOUT = 1 A, TJ = 150°C 320 IOUT = 1 A, VD = 5 V, TJ = 25°C 210 mW OFF−state: VD = 13 V, VIN = VOUT = 0 V, TJ = 25°C 0.01 0.5 mA ON−state: VD = 13 V, VIN = 5 V, IOUT = 0 A 1.9 3.5 mA VIN = VOUT = 0 V, VD = 13 V, TJ = 25°C 0.5 mA VIN = VOUT = 0 V, VD = 13 V, TJ = 125°C 0.5 5. Includes PowerMOS leakage current. Table 6. LOGIC INPUTS (VD = 13.5 V; −40°C < TJ < 150°C) Value Rating Symbol Input Voltage − Low VIN_LOW Input Current − Low IIN_LOW Input Voltage − High VIN_HIGH Input Current − High IIN_HIGH Input Hysteresis Voltage VIN_HYST Input Clamp Voltage VIN_CL CS_DIS Voltage − Low VCS_DIS_LOW CS_DIS Current − Low ICS_DIS_LOW CS_DIS Voltage − High VCS_DIS_HIGH CS_DIS Current − High ICS_DIS_HIGH CS_DIS Hysteresis Voltage VCS_DIS_HYST CS_DIS Clamp Voltage VCS_DIS_CL Conditions VIN = 0.9 V Min Typ Max Unit 0.9 V 1 mA 2.1 V VIN = 2.2 V 10 0.2 V IIN = 1 mA 12 13 14 IIN = −1 mA −14 −13 −12 0.9 VCS_DIS = 0.9 V mA V V 1 mA 2.1 V VCS_DIS = 2.2 V 10 0.2 mA V ICS_DIS = 1 mA 12 13 14 ICS_DIS = −1 mA −14 −13 −12 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 NCV84160 Table 7. SWITCHING CHARACTERISTICS (TJ = 25°C) Value Min Typ Max Symbol Conditions Turn−On Delay Time td_on to 10% VOUT, VD = 13 V, RL = 13 W 10 ms Turn−Off Delay Time td_off to 90% VOUT, VD = 13 V, RL = 13 W 10 ms Slew Rate On dVOUT/dton 10% to 80% VOUT, VD = 13 V, RL = 13 W 0.7 V / ms Slew Rate Off dVOUT/dtoff 90% to 10% VOUT, VD = 13 V, RL = 13 W 0.7 V / ms Turn−On Switching Loss (Note 6) Eon VD = 13 V, RL = 13 W 0.04 mJ Turn−Off Switching Loss (Note 6) Eoff VD = 13 V, RL = 13 W 0.04 mJ Rating Unit 6. Not subjected to production testing Table 8. OUTPUT DIODE CHARACTERISTICS Value Rating Forward Voltage Symbol Conditions VF IOUT = −1 A, TJ = 150°C, VF = VOUT − VD Min Typ Max Unit 0.7 V Table 9. PROTECTION FUNCTIONS (Note 8) Value Rating Temperature Shutdown (Note 7) Temperature Shutdown Hysteresis (TSD − TR) (Note 7) Symbol Conditions TSD Min Typ Max Unit 150 175 200 °C TSD_HYST Reset Temperature (Note 7) TR TR_CS+1 Thermal Reset of CS_FAULT (Note 7) TR_CS 135 DC Output Current Limit ILIM_H VD = 13 V 6 7 °C TR_CS+5 °C °C 12 5 V < VD < 28 V 18 A 18 A Short Circuit Current Limit during Thermal Cycling (Note 7) ILIM_L VD = 13 V TR < TJ < TSD Switch Off Output Clamp Voltage VOUT_CLAMP IOUT = 1 A, VIN = 0 V, L = 20 mH VD − 41 VD − 45 VD − 52 V VOV VIN = 0 V, ID = 20 mA 41 45 52 V VDS_ON IOUT = 0.025 A, −40°C ≤ TJ ≤ 150°C Overvoltage Protection Output Voltage Drop Limitation 6.5 A 25 mV 7. Not subjected to production testing. 8. To ensure long term reliability during overload or short circuit conditions, protection and related diagnostic signals must be used together with a fitting hardware & software strategy. If the device operates under abnormal conditions, this hardware & software solution must limit the duration and number of activation cycles. Table 10. OPEN−LOAD DETECTION (8 ≤ VD ≤ 18 V) Value Symbol Conditions Min Typ Max Unit Open−load Off−State Detection Threshold VOL VIN = 0 V 2 − 4 V Open−load On−State Detection Threshold IOL VIN = 5 V, ICS = 5 mA 0.5 5 mA Open−load Detection Delay at Turn−Off td_OL_off 100 800 ms Off−State Output Current IOLOFF1 VIN = 0 V, VOUT = VOL −3 3 mA tD_OL VOUT = 4 V, VIN = 0 V, VCS = 90% of VCS_HIGH 20 ms Rating Output rising edge to CS rising edge during open−load www.onsemi.com 6 NCV84160 Table 11. CURRENT SENSE CHARACTERISTICS (8 ≤ VD ≤ 18 V) Value Symbol Conditions min typ max Unit Current Sense Ratio K0 IOUT = 0.025 A, VCS = 0.5 V, TJ = −40°C to 150°C 260 490 760 IOUT / ICS Current Sense Ratio K1 IOUT = 0.35 A, VCS = 0.5 V, TJ = −40°C to 150°C 310 465 620 IOUT = 0.35 A, VCS = 0.5 V, TJ = 25°C to 150°C 360 465 545 DK1 / K1 IOUT = 0.35 A, VCS = 0.5 V, TJ = −40°C to 150°C −11 K2 IOUT = 0.5 A, VCS = 4 V, TJ = −40°C to 150°C 350 455 570 IOUT = 0.5 A, VCS = 4 V, TJ = 25°C to 150°C 380 455 530 DK2 / K2 IOUT = 0.5 A, TJ = −40°C to 150°C −8 K3 IOUT = 1.5 A, VCS = 4 V, TJ = −40°C to 150°C 405 455 505 IOUT = 1.5 A, VCS = 4 V, TJ = 25°C to 150°C 415 455 495 DK3 / K3 IOUT = 1.5 A, TJ = −40°C to 150°C −4 4 % CSIlkg IOUT = 0 A, VCS = 0 V VCS_DIS = 5 V, VIN = 0 V TJ = −40°C to 150°C 1 mA IOUT = 0 A, VCS = 0 V VCS_DIS = 0 V, VIN = 5 V TJ = −40°C to 150°C 2 IOUT = 1 A, VCS = 0 V VCS_DIS = 5 V, VIN = 5 V TJ = −40°C to 150°C 1 Rating Current Sense Ratio Drift (Note 9) Current Sense Ratio Current Sense Ratio Drift (Note 9) Current Sense Ratio Current Sense Ratio Drift (Note 9) Current Sense Leakage Current CS Max Voltage 11 8 % CSMax RCS = 10 KW, IOUT = 1 A Current Sense Voltage in Fault Condition (Note 10) VCS_FAULT VD = 13 V, RCS = 3.9 kW 8 V Current Sense Current in Fault Condition (Note 10) ICS_FAULT VD = 13 V, VCS = 5 V 10 mA CS_DIS Low to CS High Delay Time tCS_HIGH1 VCS < 4 V, 0.025 A < IOUT < 1.5 A ICS = 90% of ICS Max 40 100 ms CS_DIS High to CS Low Delay Time tCS_LOW1 VCS < 4 V, 0.025 A < IOUT < 1.5 A ICS = 10% of ICS Max 5 20 ms VIN High to CS High Delay Time tCS_HIGH2 VCS < 4 V, 0.025 A < IOUT < 1.5 A ICS = 90% of ICS Max 30 160 ms VIN Low to CS Low Delay Time tCS_LOW2 VCS < 4 V, 0.025 A < IOUT < 1.5 A ICS = 10% of ICS Max 80 250 ms DtCS_HIGH2 VCS < 4 V, ICS = 90% of ICS Max, IOUT = 90% of IOUTmax, IOUTmax = 1.5 A 110 ms Delay Time ID Rising Edge to Rising Edge of CS 5 % 9. Not subjected to production testing. 10. The following fault conditions are: Overtemperature, Power Limitation, and OFF State Open−Load Detection. www.onsemi.com 7 V NCV84160 Table 12. TRUTH TABLE Conditions Input Output CS (VCS_DIS = 0 V) (Note 11) Normal Operation L H L H 0 ICS = IOUT/KNOMINAL Over−temperature L H L L 0 VCS_FAULT Under−voltage L H L L 0 0 Overload H H H (no active current mgmt) Cycling (active current mgmt) ICS = IOUT/KNOMINAL VCS_FAULT Short circuit to Ground L H L L 0 VCS_FAULT OFF State Open−Load L H VCS_FAULT 11. If the VCS_DIS is high, the Current Sense output is at a high impedance, its potential depends on leakage currents and external circuitry. www.onsemi.com 8 NCV84160 ELECTRICAL CHARACTERISTICS WAVEFORMS AND GRAPHS Resistive Switching Characteristics VOUT 90% 90% 80% 80% dVOUT/dt(off) dVOUT/dt(on) 10% 10% td(on) td(off) VIN t(on) t(off) Figure 4. Switching Characteristics Normal Operation VIN t IOUT tON tOFF tON t VCS_DIS ICS tCS_High2 tCS_Low1 tCS_High1 ntCS_High2 t t Figure 5. Normal Operation with Current Sense Timing Characteristics www.onsemi.com 9 NCV84160 VIN DtCS_High2 t IOUT IOUTMAX 90% IOUTMAX t ICS ICSMAX 90% ICSMAX t Figure 6. Delay Response from Rising Edge of IOUT and Rising Edge of CS (for CS_EN = 5V) VIN t VOUT VOL VCS VCS_FAULT td_OL_off Figure 7. OFF−State Open−Load Flag Delay Timing www.onsemi.com 10 t t NCV84160 VIN VOUT VOL IOUT VCS VCS_Fault tCS_Low1 td_OL_off VCS_DIS Figure 8. Off−State Open−Load with added external components VD − V OUT TJ = 150°C TJ = 25°C TJ = -40°C VDS_ON VDS_ON/RON(T) IOUT Figure 9. Voltage Drop Limitation for VDS_ON www.onsemi.com 11 650 620 590 560 530 500 470 440 410 380 350 320 290 A. Max, −40°C ≤ TJ ≤ 150°C B. Max, 25°C ≤ TJ ≤ 150°C DK/K (%) IOUT/ICS NCV84160 C. Typ, −40°C ≤ TJ ≤ 150°C D. Min, 25°C ≤ TJ ≤ 150°C E. Min, −40°C ≤ TJ ≤ 150°C 0 0.2 0.4 0.6 0.8 IOUT (A) 1.0 1.2 1.4 18 15 12 9 6 3 0 −3 −6 −9 −12 −15 −18 A. Max, −40°C ≤ TJ ≤ 150°C B. Min, −40°C ≤ TJ ≤ 150°C 0 1.6 Figure 10. IOUT/ISense vs IOUT 0.2 0.4 0.6 0.8 1.0 IOUT (A) 1.2 1.4 1.6 Figure 11. Maximum Current Sense Ratio Drift vs Load Current www.onsemi.com 12 NCV84160 VIN IOUT IlimH IlimTCycling ICS ICS_Fault VCS_DIS Figure 12. Short to GND or Overload VIN t Overload IOUT DC Output Current Limit Current Limit during thermal cycling ILIM_H ILIM_L t TJ TSD TR TRS DTJ DTJ_RST TJ_Start t Figure 13. How TJ Progresses During Short to GND or Overload www.onsemi.com 13 NCV84160 V IN I OUT Overload I LIM_H I NOMINAL I LIM_L I CS I CS_FAULT I NOM /K V CS_DIS Figure 14. Discontinuous Overload or Short to GND www.onsemi.com 14 NCV84160 VIN Resistive short from OUT to VD Short from OUT to VD VOUT VOL IOUT VCS VCS_Fault td_OL_off td_OL_off VCS_DIS Figure 15. Short Circuit from OUT to VD www.onsemi.com 15 NCV84160 9 4.5 150°C 4 7 6 25°C 3 IIN (mA) ILOFF (mA) 3.5 2.5 2 −40°C 1.5 5 0.5 1 10 20 VD (V) 30 Iin @ 2.1 V 3 2 0 Iin @ 0.9 V 4 1 0 Iin @ 5 V 8 0 −50 40 Figure 16. Output Leakage Current vs. VD Voltage & Temperature, VOUT = 0 V 50 100 TEMPERATURE (°C) 150 Figure 17. Input Current vs. Temperature 14 −10 12 −10.5 Iin @ 1 mA Iin @ −1 mA −11 10 −11.5 VIN_CL (V) VIN_CL (V) 0 8 6 −12 −12.5 4 −13 2 −13.5 0 −50 0 50 100 TEMPERATURE (°C) −14 −50 150 Figure 18. Input Clamp Voltage (Positive) vs. Temperature 0 50 100 TEMPERATURE (°C) 150 Figure 19. Input Clamp Voltage (Negative) vs. Temperature 1.8 2.5 1.6 1.4 VIN_LOW (V) VIN_HIGH (V) 2 1.5 1 1.2 1 0.8 0.6 0.4 0.5 0.2 0 −50 0 50 100 TEMPERATURE (°C) 0 −50 150 Figure 20. VIN Threshold High vs. Temperature 0 50 100 TEMPERATURE (°C) 150 Figure 21. VIN Threshold Low vs. Temperature www.onsemi.com 16 0.4 400 0.35 350 0.3 300 0.25 250 RON (mW) VIN_HYST (V) NCV84160 0.2 0.15 200 150 0.1 100 0.05 50 0 −50 0 50 100 TEMPERATURE (°C) 0 150 −50 Figure 22. Hyseresis Input Voltage vs. Temperature 5 350 4.8 4.2 VUV (V) RON (mW) 4.4 125°C 200 25°C 150 4 3.8 3.6 −40°C 100 3.4 50 0 3.2 0 5 10 15 20 VD (V) 25 30 3 −50 35 Figure 24. RON vs. Temperature & VD Voltage 900 800 1000 VD = 13 V RL = 13 W 800 600 500 400 300 600 500 400 300 200 100 100 0 50 100 TEMPERATURE (°C) 150 700 200 0 −50 50 100 TEMPERATURE (°C) VD = 13 V RL = 13 W 900 700 0 Figure 25. Undervoltage Shutdown vs. Temperature dVOUT/dtoff (V/ms) 1000 dVOUT/dton (V/ms) 150 4.6 150°C 250 50 100 TEMPERATURE (°C) Figure 23. RON vs. Temperature 400 300 0 0 150 −50 Figure 26. Slew Rate On vs. Temperature 0 50 100 TEMPERATURE (°C) Figure 27. Slew Rate Off vs. Temperature www.onsemi.com 17 150 NCV84160 19 4 17 3.5 VCS_DIS_HIGH (V) ILIM (A) 15 13 11 9 2.5 2 1.5 1 7 5 3 0.5 −50 0 50 100 TEMPERATURE (°C) 0 150 −50 0 14 3.5 12 VCS_DIS CLAMP (V) 3 2.5 2 1.5 1 10 8 6 4 0.5 2 0 0 −50 0 50 100 TEMPERATURE (°C) 150 Figure 30. CS_DIS Threshold Low vs. Temperature ICS_DIS = 1 mA −50 0 50 100 TEMPERATURE (°C) ICS_DIS = −1 mA −10.5 −11 −11.5 −12 −12.5 −13 −13.5 0 150 Figure 31. CS_DIS Clamp Voltage (Positive) vs. Temperature −10 −14 −50 150 Figure 29. CS_DIS Threshold High vs. Temperature 4 VCS_DIS CLAMP (V) VCS_DIS_LOW (V) Figure 28. Current Limit vs. Temperature, VD = 13.5 V 50 100 TEMPERATURE (°C) 50 100 TEMPERATURE (°C) 150 Figure 32. CS_DIS Clamp Voltage (Negative) vs. Temperature www.onsemi.com 18 NCV84160 ISO 7637−2: 2011(E) PULSE TEST RESULTS ISO 7637−2:2011 Test Pulse Test Severity Levels III IV Delays and Impedance # of Pulses or Test Time Pulse / Burst rep. time 1 −112 −150 2 ms, 10 W 500 pulses 0.5 s 2a 55 112 0.05 ms, 2 W 500 pulses 0.5 s 3a −165 −220 0.1 us, 50 W 1h 100 ms 3b 112 150 0.1 us, 50 W 1h 100 ms ISO 7637−2:2011 Test Pulse Test Results III 1 2a IV A A E 3a A 3b A Class Functional Status A All functions of a device perform as designed during and after exposure to disturbance. B All functions of a device perform as designed during exposure. However, one or more of them can go beyond specified tolerance. All functions return automatically to within normal limits after exposure is removed. Memory functions shall remain class A. C One or more functions of a device do not perform as designed during exposure but return automatically to normal operation after exposure is removed. D One or more functions of a device do not perform as designed during exposure and do not return to normal operation until exposure is removed and the device is reset by simple ”operator/use” action. E One or more functions of a device do not perform as designed during and after exposure and cannot be returned to proper operation without replacing the device. www.onsemi.com 19 NCV84160 Application Information +5V VD RμC CS RμC ZCS Output Clamping IN ZVD Micro Controller RμC Dld VBAT Control Logic CS_DIS ZBody OUT Cexternal RCS ZESD ZL GND RGND Figure 33. Application Schematic Loss of Ground Protection −I GND + When device or ECU ground connection is lost and load is still connected to ground, the device will turn the output OFF. In loss of ground state, the output stage is held OFF independent of the state of the input. Input resistors are recommended between the device and microcontroller. −V D R GND (eq. 1) Since this resistor can be used amongst multiple High−Side devices, please take note the sum of the maximum active GND currents (IGND(On)max) for each device when sizing the resistor. Please note that if the microprocessor GND is not shared by the device GND, then RGND produces a shift of (IGND(On)max * RGND) in the input thresholds and CS output values. If the calculated power dissipation leads to too large of a resistor size or several devices have to share the same resistor, please look at the second solution for Reverse Battery Protection. Refer to the figure below for selecting the proper RGND. Reverse Battery Protection Solution 1: Resistor in the GND line only (no parallel Diode) The following calculations are true for any type of load. In the case for no diode in parallel with RGND, the calculations below explain how to size the resistor. Consider the following parameters: –IGND Maximum = 200 mA for up to −VD = 32 V. Where –IGND is the DC reverse current through the GND pin and –VD is the DC reverse battery voltage. www.onsemi.com 20 NCV84160 Figure 34. Reverse Battery RGND Considerations Undervoltage Protection Solution 2: Diode (DGND) in parallel with RGND in the ground line. A resistor value of RGND = 1 kOhm should be selected and placed in parallel to DGND if the device drives an inductive load. The diode (DGND) provides a ~600−700 mV shift in the input threshold and current sense values if the micro controller ground is not common to the device ground. This shift will not vary even in the case of multiple high−side devices using the same resistor/diode network. The device has two under−voltage threshold levels, VD_MIN and VUV. Switching function (ON/OFF) requires supply voltage to be at least VD_MIN. The device features a lower supply threshold VUV, above which the output can remain in ON state. While all protection functions are guaranteed when the switch is ON, diagnostic functions are operational only within nominal supply voltage range VD. VOUT V UV V D _ MIN VD Figure 35. Undervoltage Behavior www.onsemi.com 21 NCV84160 Overvoltage Protection Overload Protection The NCV84160 has two Zener diodes ZVD and ZCS, which provide integrated overvoltage protection. ZVD protects the logic block by clamping the voltage between supply pin VD and ground pin GND to VZVD. ZCS limits voltage at current sense pin CS to VD – VZCS. The output power MOSFET’s output clamping diodes provide protection by clamping the voltage across the MOSFET (between VD pin and OUT pin) to VCLAMP. During overvoltage protection, current flowing through ZVD, ZCS and the output clamp must be limited. Load impedance ZL limits the current in the body diode ZBody. In order to limit the current in ZVD a resistor, RGND (150 Ω), is required in the GND path. External resistors RCS and RSENSE limit the current flowing through ZCS and out of the CS pin into the micro−controller I/O pin. With RGND, the GND pin voltage is elevated to VD – VZVD when the supply voltage VD rises above VZVD. ESD diodes ZESD pull up the voltage at logic pins IN, CS_Dis close to the GND pin voltage VD – VZVD. External resistors RIN, and RCS_DIS are required to limit the current flowing out of the logic pins into the micro−controller I/O pins. During overvoltage exposure, the device transitions into a self−protection state, with automatic recovery after the supply voltage comes back to the normal operating range. The specified parameters as well as short circuit robustness and energy capability cannot be guaranteed during overvoltage exposure. Current limitation as well as over−temperature shutdown mechanisms are integrated into the NCV84160 to provide protection from overload conditions such as bulb inrush or short to ground. Current Limitation In case of overload, the NCV84160 limits the current in the output power MOSFET to a safe value. Due to high power dissipation during current limitation, the device’s junction temperature increases rapidly. In order to protect the device, the output driver is shut down by one of the two over−temperature protection mechanisms. The output current limitation level is dependent on the drain−to−source voltage of the power MOSFET. If the input remains active during the shutdown, the output power MOSFET will automatically be re−activated after a minimum OFF time or when the junction temperature returns to a safe level. Output Clamping with Inductive Load Switch Off: The output voltage VOUT drops below GND potential when switching off inductive loads. This is because the inductance develops a negative voltage across the load in response to a decaying current. The integrated clamp of the device clamps the negative output voltage to a certain level relative to the supply voltage VBAT. During output clamping with inductive load switch off, the energy stored in the inductance is rapidly dissipated in the device resulting in high power dissipation. This is a stressful condition for the device and the maximum energy allowed for a given load inductance should not be exceeded in any application. VIN t IOUT t VOUT VBAT t VCLAMP VBAT −VCLAMP Figure 36. Inductive Load Switching www.onsemi.com 22 NCV84160 10 VD = 13.5 V RL = 0 Ω TJstart = 150°C, Single Pulse I L (A) TJstart = 100°C, Repetitive Pulse TJstart = 125°C, Repetitive Pulse 1 1 10 L (mH) Figure 37. Maximum Switch−Off Current vs. Load Inductance, VD = 13.5 V; RL = 0 W www.onsemi.com 23 100 NCV84160 Open Load Detection in OFF State Open load diagnosis in the OFF−state can be performed by activating an external resistive pull−up path (RPU) to VBAT. To calculate the pull−up resistance, external leakage currents (designed pull−down resistance, humidity−induced leakage etc) as well as the open load threshold voltage VOL have to be taken into account. VBAT VD VOL_OFF IN ZBody ICS_FAULT RPU OUT CS GND RCS RPD RLEAK ZL RGND Figure 38. Off State Open Load Detection Circuit Current Sense in PWM Mode While operating in PWM mode, the current sense functionality can be used, but the timing of the input signal and the response time of the current sense need to be considered. When operating in PWM mode, the following performance is to be expected. The CS_DIS pin should be left low to eliminate any unnecessary delay time to the circuit. When VIN switches from low to high, there will be a typical delay (tCS_High2) before the current sense responds. Once this timing delay has passed, the rise time of the current sense output (DtCS_High2) also needs to be considered. When VIN switches from high to low a delay time (tCS_Low1) needs to be considered. As long as these timing delays are allowed, the current sense pin can be operated in PWM mode. www.onsemi.com 24 NCV84160 PACKAGE AND PCB THERMAL DATA (Note 1) Figure 39. Junction to Ambient Transient Thermal Impedance (Min. Pad Cu Area) Figure 40. Junction to Ambient Transient Thermal Impedance (2 cm2 Cu Area) 1. PCB FR4 Area = 4.8 cm x 4.8 cm, PCB Thickness = 1.6 mm, backside plane covered with 1 oz. Cu (backside plane not electrically connected) www.onsemi.com 25 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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