NCV8855

NCV8855 Quad-Output Automotive System Power Supply IC with Integrated High-Side 2A Switch The NCV8855 is a multiple output controller / regulator IC with an integrated high−side load switch. The NCV8855 addresses automotive radio system and instrument cluster power supply requirements. In addition to the high−side load switch, the NCV8855 includes a switch−mode power supply (SMPS) buck controller, a 2.5 A SMPS buck regulator and two low dropout (LDO) linear regulator controllers. The NCV8855 in combination with the ultra−low quiescent current NCV861x IC forms an eight−output automotive radio or instrument cluster power solution. The NCV8855 has an internally set switching frequency of 170 kHz, with a SYNC pin for external frequency synchronization. The NCV8855 is intended to supply power to various loads, such as a tuner, CD logic, audio processor and CD / tape control within a car radio. The high−side switch can be used for a CD / tape mechanism or switching an electrically−powered antenna or display unit. In an instrument cluster application, the NCV8855 can be used to power graphics display, flash memory and CAN transceivers. In addition, the high−side switch can be used to limit power to a TFT display during a battery over−voltage condition. Features http://onsemi.com MARKING DIAGRAM 1 1 40 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR A WL YY WW G NCV8855 AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† 2500 / Tape & Reel • • • • • • • • • • • • • • < 1 mA Shutdown Current Meets ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions VIN Operating Range 9.0 to 18.0 V 1 SMPS Controller with Adjustable Current Limit 1 SMPS Regulator with Internal 300 mW NMOS Switch 2 LDO Controllers with Current Limit and Short Circuit Protection 1 High−side Load Switch with Internal 300 mW NMOS FET Adjustable Output Voltage for All Controllers / Regulators 800 mV, $1% Reference Voltage System Enable Pin Single Enable Pin for Both LDO Controllers Independent Enable for High−side Load Switch Thermal Shutdown with Thermal Warning Indicator This is a Pb−Free Device NCV8855BMNR2G QFN−40 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • Automotive Radio • Instrument Cluster, Driver Information System (DIS) © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. 1 1 Publication Order Number: NCV8855/D NCV8855 TYPICAL APPLICATION SCHEMATIC SHOWING DETAILED BLOCK DIAGRAM DRV_VPP SYS _EN 22 5 VIN Bandgap V1 VR DRV_VPP ILIMIT VIN 5V_IC I LIMIT 35 5V_IC V1 VR VIN LDO 36 11 DRAIL BST2 VIN_SW VBATT VBATT BST1 Q1 GH1 SN1 Q2 GL1 25 Gate Control 24 23 21 QS QR CLK1 CLK2 SQ R ILIMIT V REF 10 VOUT1 9 SS2 SN2 D1 VOUT2 OCSET ILIMIT 27 SS1 V REF EA RAMP1 70% VREF SCP SCP RAMP2 EA 3 2 SW_FB2 COMP2 SYNC SW_FB1 COMP1 29 30 DRV_VPP 5V_IC UVLO CLK1 RAMP1 CLK2 RAMP2 OSC 180° out−of−phase 4 HOT_FLG 8 TWARN1 TWARN2 Main Logic / Fault Control TSD1 TSD2 Int. rails and references V REF 5V_IC ILIMIT 7 6 HS_EN LDO_EN VOUT1 ISNS1+ ISNS1 − 40 39 1 38 ILIMIT 31 32 ISNS2+ ISNS2− LR _G2 LR_FB2 Q4 VBATT VOUT3 Q3 LR_G1 LR_FB1 VREF EA EA 33 34 VOUT4 SCP 70% VREF VBATT VIN 26 VIN SCP 70% VREF Control CLK1 HS_OUT HS_S 28 Current Limit Vneg clamp Vhigh clamp Charge Pump 37 AGND 20 PGND Figure 1. Application Schematic / Block Diagram Components D1 Q1, Q2 Q3, Q4 Part Number MBRS4201T3 NTD24N06 NTD20P06LT4G Value 200 V, 4 A, Schottky, 0.61 V Vf, SMC 60 V, N type MOSFET, 32 mW , DPAK −60V, P type MOSFET, 130 mW, DPAK Manufacturer ON Semiconductor ON Semiconductor ON Semiconductor http://onsemi.com 2 NCV8855 PIN FUNCTION DESCRIPTIONS Pin No. 5 6 7 8 22 35 36 4 37 Symbol SYS_EN LDO_EN HS_EN HOT_FLG DRV_VPP 5V_IC DRAIL SYNC AGND Description Main enable pin for the IC. A logic high on this pin will enable the part. Leaving this pin floating or driving it to ground will place the IC in shutdown mode. Enable pin for both LDO controllers. A logic high on this pin will enable both LDO controllers. If this pin is left floating, an internal pull down keeps the LDOs disabled. Enable pin for the high−side load switch. A logic high on this pin will enable the HSS. If this pin is left floating, an internal pull down keeps the HSS disabled. Thermal warning indicator. This pin provides an early warning signal of an impending thermal shutdown. Output of the internal 7.2 V linear regulator. Bypass this pin with 1 mF to ground. Output of the internal 5 V linear regulator. Bypass this pin with 0.1 mF to ground. Output of the internal 4.2 V linear regulator. Bypass this pin with 0.1 mF to ground. Synchronization pin. Use this pin to synchronize the internal oscillator to an external clock. If synchronization is not used, connect this pin to AGND. Analog ground. Reference point for internal signals. SWITCH−MODE POWER SUPPLY 1 (SMPS1) PIN CONNECTIONS 27 29 30 OCSET SW_FB1 COMP1 Overcurrent set pin, used to set the current limit threshold. A resistor connected from this pin and the upper MOSFET Drain sets the current limit protection level. Output voltage feedback pin. Connect a resistor divider network to VOUT1 to set the desired output voltage. This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB1 pin to compensate the voltage-mode control feedback loop. This pin is the supply rail for the upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST1) between this pin and the SN1 pin. A typical value for CBST1 is 0.1 mF. GH1 is the output pin of the internal upper N−Channel MOSFET gate driver. Keep the trace from this pin to the gate of the upper MOSFET as short as possible to achieve the best turn−on and turn−off performance and to reduce electro−magnetic emissions. This pin is the return path of the upper floating gate driver. Connect this pin to the source of the upper MOSFET. This pin is also used to sense the current flowing through the upper MOSFETs. GL1 is the output pin of the synchronous rectifier gate driver. Connect this pin to the lower N−channel MOSFET. This pin is the return path for SMPS1 lower MOSFET driver current. Connect this pin to the source of the lower MOSFET. 25 BST1 24 GH1 23 21 20 SN1 GL1 PGND PINS NOT INTERNALLY CONNECTED TO SILICON EP 12 thru 19 − Exposed pad of QFN package. Connect to printed circuit board ground to improve thermal performance. These pins can be left floating or tied to ground to improve thermal performance. SWITCH−MODE POWER SUPPLY 2 (SMPS2) PIN CONNECTIONS 10 VIN_SW This pin is the supply rail for the internal upper N−Channel MOSFET. Bypass this pin with a local ceramic capacitor. Additional bulk capacitance may be required based off output requirements. Refer to application section for more information. Output voltage feedback pin. Connect a resistor divider network to VOUT2 to set the desired output voltage. This pin is the output of the error amplifier and the non−inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB2 pin to compensate the voltage−controlled feedback loop. This pin is the supply rail for the internal upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST2) between this pin and the SN2 pin. A typical value for CBST2 is 0.1 mF. Source output of the internal upper N−channel MOSFET. 3 2 11 SW_FB2 COMP2 BST2 9 SN2 http://onsemi.com 3 NCV8855 PIN FUNCTION DESCRIPTIONS Pin No. Symbol Description LOW DROPOUT LINEAR REGULATOR CONTROLLER 1 (LDO1) PIN CONNECTIONS 38 1 40 LR_FB1 LR_G1 ISNS1+ LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element. Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element. 39 ISNS1− LOW DROPOUT LINEAR REGULATOR CONTROLLER 2 (LDO2) PIN CONNECTIONS 34 33 31 LR_FB2 LR_G2 ISNS2+ LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element. Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element. 32 ISNS2− HIGH−SIDE LOAD SWITCH (HSS) PIN CONNECTIONS 26 28 VIN HS_S This pin is the supply rail for the internal high−side load switch, DRV_VPP and 5V_IC. Bypass this pin with a 1 mF ceramic capacitor. Source node output of the internal high−side N−Channel MOSFET load switch. MAXIMUM RATINGS (Voltages are with respect to AGND unless noted otherwise) Pin Name Max dc voltage (GH1, BST1, SN1, SN2, BST2, HS_S) Negative Transient (t < 50 ns) (SN1, SN2) Max dc voltage: 5V_IC Max dc voltage: DRV_VPP Max dc voltage (BST1 & GH1w/respect to SN1, GL1, BST2 w/respect to SN2) Max dc voltage (OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2) Peak Transient (ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions) (OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2) Max dc voltage (SW_FB1, COMP1, LR_FB1, LDO_EN, HOT_FLG, SW_FB2, COMP2, LR_FB2, HS_EN, SYS_EN, SYNC) Max dc voltage: PGND Maximum Operating Junction Temperature Range, TJ Maximum Storage Temperature Range, TSTG Peak Reflow Soldering Temperature: Pb−Free 60 to 150 seconds at 217°C Value −0.3 to 30 −2 6 9 −0.3 to 15 −0.3 to 40 −0.3 to 45 −0.3 to 7 −0.3 to 0.3 −40 to 150 −55 to +150 260 peak Unit V V V V V V V V V °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 NCV8855 ATTRIBUTES Description Thermal Characteristic RqJA generated from 1 sq in / 1 oz copper 1 sided PCB ESD Capability Human Body Model (SN1, SN2) Human Body Model (All Others) Machine Model Moisture Sensitivity Level MSL Symbol RqJA RqJC Value 36 3 1 2 150 1 Unit °C/W °C/W kV kV V RECOMMENDED OPERATING CONDITIONS Description VBATT range (refer to Figure 1) Ambient Temperature range ISNS1+ 1 ISNS2+ LR_FB1 LR_FB2 Value 9 V to 18 V −40°C to 105°C ISNS2− ISNS1− LR_G2 DRAIL AGND 5V_IC LR_G1 COMP2 SW_FB2 SYNC/ROSC SYS_EN COMP1 SW_FB1 HS_S OCSET VIN Top View BST1 GH1 SN1 DRV_VPP GL1 LDO_EN HS_EN HOT_FLG SN2 VIN_SW ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Supply Current and Operating Voltage Range VIN_SW quiescent current VIN_SW shutdown current High VIN detect voltage High VIN detect hysteresis VIN quiescent current VIN shutdown current VOVP No Switching, VSW_FB2 = 1V, SN2 = PGND1, TJ = 25°C SYS_EN = 0 V, TJ = 25°C VIN rising VIN falling TJ = 25°C SYS_EN = 0 V, TJ = 25°C 18 0.2 175 100 18.5 0.6 4 100 500 500 19 1 mA nA mA nA V 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. BST2 PGND Figure 2. http://onsemi.com 5 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Internal Voltage Reference Internal voltage reference range Internal Linear Regulator 5 V Supply Rail 5V_IC UVLO threshold voltage 5V_IC UVLO hysteresis Voltage range Current limit Load regulation Line regulation Internal DRV_VPP Supply Rail DRV_VPP UVLO threshold voltage DRV_VPP UVLO hysteresis Voltage range Current limit Load regulation Line regulation Dropout voltage Oscillator Oscillator frequency SYNC Logic high Logic low Pull down current Leakage current Clock synchronization range Synchronization delay to SMPS1 Synchronization delay to SMPS2 Minimum SYNC pulse width (HIGH) Minimum SYNC pulse width (LOW) From falling SYNC edge From rising SYNC edge SMPS1 synchronizing SMPS2 synchronizing VSYNC = 5 V VSYNC = 0.8 V SYS_EN = 0 V, VSYNC = 5 V 190 200 200 0.8 2 5 5 100 10 500 255 400 400 50 50 2.0 V V mA nA kHz ns ns ns ns fSW 154.7 170 185.3 kHz 1 mA v IDRV_VPP v 25 mA IDRV_VPP = 1 mA, 9 V v VIN v 18 V IDRV_VPP = 25 mA, DVDRV_VPP = 2 % VDRV_VPP VDRV_VPP rising VDRV_VPP falling No load 4.00 100 6.9 30 4.35 150 7.1 67 4.70 300 7.3 110 50 200 400 V mV V mA mV mV mV 1mA v I5V_IC v 10 mA I5V_IC = 5 mA, 9 V v VIN v 18 V V5V_IC rising V5V_IC falling No load 4.00 100 4.8 10 4.35 150 5 21 4.70 300 5.2 50 50 100 V mV V mA mV mV VREF TJ = 25°C −40°C v TJ v 150°C 0.792 0.784 0.8 0.808 0.816 V Thermal Monitoring (TMON_HSS, High−side junction temperature monitor) Thermal warning temperature TWARN1 hysteresis Thermal shutdown temperature Delta junction temperature (TSD1−TWARN1) Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) Thermal warning temperature TWARN2 140 150 160 °C 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. TSD1 TWARN1 140 10 160 10 170 20 150 160 20 180 30 °C °C °C °C http://onsemi.com 6 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) TWARN2 hysteresis Thermal shutdown temperature Delta junction temperature (TSD2−TWARN2) HOT_FLG Voltage low threshold Leakage current Sink capability System Enable Logic high Logic low Pull down resistance High−Side Enable HS_EN logic high HS_EN logic low Pull down current Leakage current LDO Enable Logic high Logic low Pull down current Leakage current ILDO_EN VLDO_EN = 5 V VLDO_EN = 0.8 V SYS_EN = 0 V, VLDO_EN = 5 V 0.8 2 5 5 100 10 500 2.0 V V mA nA IHS_EN VHS_EN = 5 V VHS_EN = 0.8 V SYS_EN = 0 V, VHS_EN = 5 V 0.8 2 5 5 100 10 500 2.0 V V mA nA TJ = 25°C 500 2.0 0.8 V V kW TJ > TWARN[x], 1 kW pullup to 5 V 1 kW pull−up to 5 V, TJ = 25°C VHOT_FLG = 0.8 V 4.6 100 0.4 500 V nA mA TSD2 10 160 10 170 20 20 180 30 °C °C °C SWITCH−MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS Over Current Protection OCSET current sink OCSET leakage current OCSET comparator differential range OCSET comparator common−mode range Current limit response time Short circuit threshold voltage Short circuit protection startup delay Internal Soft−Start Soft−start time tSS1 3 5 7 ms SCTH1 ROCSET = 10 kW connected to 13.2 V SYS_EN = 0 V, VOCSET = 13.2 V, TJ = 25°C (Note 1) (Note 1) From rising edge of SN1 VSW_FB1 % of VREF From SYS_EN rising edge, % of tSS1, SW_FB1 = 0.5 V, (Note 2) 50 4.0 100 75 100 200 80 125 45 55 100 65 500 750 19 275 85 150 mA nA mV V ns % % 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 7 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SWITCH−MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS Error Amplifier Dc gain Gain−bandwidth product SW_FB1 input bias current Input offset voltage Slew rate COMP1 source current (Note 1) (Note 1) SW_FB1 = 0.8 V (Note 1) CCOMP1 = 50 pF, $1 mA dc load Slew rate within ramp voltage levels (Note 1) VCOMP1 = 2.2 V VCOMP1 = 3.2 V COMP1 sink current VCOMP1 = 2.2 V VCOMP1 = 1.1 V Minimum COMP1 voltage Maximum COMP1 voltage Ramp maximum voltage Ramp minimum voltage Ramp voltage amplitude Duty Cycle Limitations Minimum off time Minimum pulse width Gate Driver GH1 source current GH1 sink current GL1 source current GL1 sink current SN1 falling to GL1 rising, non−overlap time GL1 falling to GH1 rising, non−overlap time SN1 falling non−overlap threshold voltage GL1 falling non−overlap threshold voltage SN1 falling override timer 50 1.0 tNOLT VGH1 – VSN1 = 4 V, TJ = 25°C VGH1 – VSN1 = 2 V, TJ = 25°C VGL1 – PGND = 4 V, TJ = 25°C VGL1 – PGND = 1 V, TJ = 25°C 1.5 1.5 1.5 1.5 30 30 1.8 2 100 150 70 70 3.0 A A A A ns ns V V ns tMINOFF1 tMINON1 GH1 falling to GL1 rising GH1 rising to GH1 falling 80 120 140 250 200 300 ns ns VRAMP1 ICOMP1 = 500 mA ICOMP1 = 2 mA 3.3 2.8 1.1 1.6 3.0 1.2 1.8 3.2 1.3 2.0 6 1.5 1.6 1.1 0.7 8 8 8 8 8 1.05 70 8 85 10 100 800 dB MHz nA mV V/ms mA mA mA mA V V V V V SWITCH−MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS Over Current Protection Internal current limit Current limit blanking time Short circuit threshold voltage Short circuit protection startup delay SCTH2 VSW_FB2 % of VREF From SYS_EN rising edge, % of tSS2, SW_FB2 = 0.5 V 2.5 100 75 100 85 125 3.05 4.2 200 95 150 A ns % % 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 8 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SWITCH−MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS Internal Soft−start Soft−start time Error Amplifier Dc gain Gain−bandwidth product SW_FB2 input bias current Input offset voltage Slew rate COMP2 source current CCOMP2 = 50 pF, ±1 mA dc load Slew rate within ramp voltage levels (Note 1) VCOMP2 = 2.2 V VCOMP2 = 3.2 V COMP2 sink current VCOMP2 = 2.2 V VCOMP2 = 1.1 V Minimum COMP2 voltage Maximum COMP2 voltage Ramp maximum voltage Ramp minimum voltage Ramp voltage amplitude Duty Cycle Limitations Minimum off time Minimum pulse width Switching MOSFET N−channel MOSFET RDS(on) Turn−on time Turn−off time TJ = 25°C, Guaranteed at Probe SN2 → 0 V to 13.2 V, IOUT = 1 A (inductive load), TJ = 25°C SN2 → 13.2 V to 0 V, IOUT = 1 A (inductive load), TJ = 25°C 300 30 30 360 mW ns ns tMINOFF2 tMINON2 SN2 falling to SN2 rising SN2 rising to SN2 falling, 80 120 140 250 200 300 ns ns VRAMP2 ICOMP2 = 500 mA ICOMP2 = 2 mA 3.3 2.8 1.1 1.6 3.0 1.2 1.8 3.2 1.3 2.0 6 1.5 1.6 1.1 0.7 8 8 8 8 8 1.05 (Note 1) (Note 1) SW_FB2 = 0.8 V 70 8 85 10 100 500 800 dB MHz nA mV V/ms mA mA mA mA V V V V V tSS2 SYNC floating 3 5 7 ms LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS Output Voltage Regulation Output voltage accuracy Output voltage line regulation Output voltage load regulation Output load capacitance range Output load capacitance ESR range Power supply ripple rejection Current Limit Current limit threshold voltage VSNS1 VISNS1+ – VISNS1− 90 110 130 mV PSRR1 COUT3 VLR_FB1 tied to VOUT3 directly, NTD20P06L pass device IOUT3 = 10 mA, 4.5 V v VISNS1+ v 5.5 V, NTD20P06L pass device 1 mA v IOUT3 v 500 mA, VISNS1+ = 5 V, NTD20P06L pass device (Note 1) (Note 1) NTD20P06L pass device (Note 1) −2 −0.25 −0.5 10 0.01 60 0.01 0.2 2 0.25 0.5 100 5 % % % mF W dB 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 9 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS Current Limit ISNS1+ leakage current ISNS1− leakage current Short circuit threshold voltage Short circuit blanking time Error Amplifier Feedback bias current Maximum |VGS| LR_FB1 = 0.5 V 2 mA, internally clamped 10 100 11.7 500 13.5 nA V IISNS1+ IISNS1− SYS_EN = 0, TJ = 25°C, VISNS1+ = 13.2 V SYS_EN = 0, TJ = 25°C, VISNS1− = 13.2 V VLR_FB1 % of VREF From rising edge of LDO_EN 60 10 100 100 70 12 500 500 80 14 nA nA % ms LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO2, VOUT4) SPECIFICATIONS Output Voltage Regulation Output voltage accuracy Output voltage line regulation Output voltage load regulation Output load capacitance range Output load capacitance ESR range Power supply ripple rejection Current Limit Current limit threshold voltage ISNS2+ leakage current ISNS2− leakage current Short circuit threshold voltage Short circuit blanking time Error Amplifier Feedback bias current Maximum |VGS| LR_FB2 = 0.5 V 2 mA, internally clamped 10 100 11.7 500 13.5 nA V VSNS2 IISNS2+ IISNS2− VISNS2+ – VISNS2− SYS_EN = 0, TJ = 25°C, VISNS2+ = 13.2 V SYS_EN = 0, TJ = 25°C, VISNS2− = 13.2 V VLR_FB2 % of VREF From rising edge of LDO_EN 60 10 90 110 100 100 70 12 130 500 500 80 14 mV nA nA % ms PSRR2 COUT4 VLR_FB2 tied to VOUT4 directly, NTD20P06L pass device IOUT4 = 10 mA, 9 V v VISNS2+ v 18 V, NTD20P06L pass device 1 mA v IOUT4 v 500 mA, NTD20P06L pass device (Note 1) (Note 1) NTD20P06L pass device (Note 1) −2 −0.25 −0.5 10 0.01 60 0.01 0.2 2 0.25 0.5 100 5 % % % mF W dB High−side Load Switch (HSS) Current Limit Peak current limit Short circuit timeout Short circuit threshold voltage Current overload threshold voltage Current overload timeout Voltage Clamp Source output positive clamping voltage Source output negative clamping voltage VCLAMP+ VCLAMP− 1 mA v IHS_S v 2 A VCLAMP+ v VIN v VOVP ILOADSW = 50 mA 15.4 −1.6 16.0 16.6 V V IHSSLIM tSCP VSCP(HS_S) VDS VIN – VHS_S 2.00 1.300 4.0 3.3 2.600 2.80 1.506 4.5 3.95 3.012 3.64 1.800 5.0 4.6 3.600 A ms V V ms 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 10 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit High−side Load Switch (HSS) MOSFET HSS RDS(on) HSS dropout voltage Turn On/Off Turn on time (resistive load) Turn off time RHS_S = 6.6 W, 90% VIN RHS_S = 6.6 W, 10% VIN 40 50 80 125 120 200 ms ms VGS(HSS) = 8 V IHS_S = 1 A 233 233 442 442 mW mV 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. 1.506 msec 3.012 m sec VDS w 3.75 V VHS_S VDS=3.75V 4.5V ILOAD 2.8A HS_EN HS Current Overload (Latched shutdown of HS only) Figure 3. http://onsemi.com 11 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 169.4 169.2 169.0 168.8 fSW (kHz) 168.4 168.2 167.8 167.6 167.4 −50 −25 0 25 50 75 100 125 150 0.796 −50 −25 0 25 50 75 100 125 150 168.0 0.798 VREF (V) 168.6 0.802 0.800 0.804 0.808 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 4. Switching Frequency vs. Junction Temperature 3.2 3.1 HSS CURRENT LIMIT (A) 3.0 tNOL (ns) 2.9 2.8 2.7 2.6 2.5 2.4 −50 −25 0 25 50 75 100 125 150 65 60 55 50 45 40 35 30 −50 Figure 5. Reference Voltage vs. Junction Temperature −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. HSS Current Limit vs. Junction Temperature 7.18 7.16 VDRV_VPP (V) 7.14 7.12 7.10 7.08 7.06 −50 80.8 80.6 80.4 80.2 SCTH (%) 80.0 79.8 79.6 79.4 79.2 79.0 78.8 −25 0 25 50 75 100 125 150 78.6 −50 Figure 7. SMPS1 Non−Overlap Time vs. Junction Temperature SMPS2 SMPS1 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 8. Drive Voltage vs. Junction Temperature Figure 9. Short Circuit Threshold vs. Junction Temperature http://onsemi.com 12 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 1.820 1.815 1.810 tMINON (ns) VRAMP (V) 1.805 SMPS1 SMPS2 220 215 210 205 200 195 190 −25 0 25 50 75 100 125 150 185 −50 −25 0 25 50 75 100 125 150 1.800 1.795 1.790 1.785 −50 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Ramp Amplitude vs. Junction Temperature 0.14 0.12 IOCSET_L, (mA) 0.10 0.08 0.06 0.04 0.02 0.00 −50 −25 0 25 50 75 100 125 150 IOCSET, (mA) 56.6 56.4 56.2 56.0 55.8 55.6 55.4 55.2 55.0 −50 Figure 11. Minimum On Time vs. Junction Temperature −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 12. OCSET Leakage Current vs. Junction Temperature 2.5 2.0 IHS_EN, (mA) 1.5 1.0 0.5 0.0 −50 109.5 109.0 108.5 Figure 13. OCSET Current Sink vs. Junction Temperature VSNS (mV) 108.0 LDO1 107.5 107.0 106.5 −50 LDO2 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 14. HS EN Leakage Current vs. Junction Temperature Figure 15. LDO Current Limit vs. Junction Temperature http://onsemi.com 13 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 0.18 0.16 0.14 ILDO_EN (mA) 0.12 0.10 0.08 0.06 0.04 0.02 0.00 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 16. LDO EN Leakage Current vs. Junction Temperature http://onsemi.com 14 NCV8855 THEORY OF OPERATION Device Description Linear Regulator Enable (LDO_EN) The NCV8855 is a multiple output controller / regulator IC with an integrated high−side load switch. The NCV8855 will address automotive radio system and instrument cluster power supply requirements. In addition to the high−side load switch, the NCV8855 comprise a switch−mode power supply (SMPS) buck controller, a 2 A SMPS buck regulator, and two low dropout linear regulator controllers (LDO). The NCV8855 in combination with the ultra−low Iq NCV861x IC forms an eight output automotive radio or instrument cluster power solution. DRV_VPP 5V_IC 22 35 SYS_EN 5 6 LDO_EN MAIN 8 HOT_FLG 11 BST2 10 VIN_SW 9 SN2 SMPS1 VOUT1 SMPS2 VOUT2 The low−dropout linear regulators (LDOs) have a dedicated enable pin. This pin controls the startup and shutdown of the LDOs. The SYS_EN pin must be logic high for this pin to function. It is possible to drive this pin high coincidentally with SYS_EN, but the LDO outputs will not startup until DRV_VPP and 5V_IC have increased above its UVLO thresholds. High−Side Switch Enable (HS_EN) The high−side switch enable controls only the high−side switch. Similar to LDO_EN, the SYS_EN pin must be logic high for this pin to function. The voltage level on all enable pins have been designed to work with 3.3 V or 5 V logic. IC Power (VIN, VIN_SW, DRV_VPP, 5V_IC) BST1 25 GH1 24 SN1 23 GL1 21 OCSET 27 SW_FB1 29 COMP1 30 ISNS1+ 40 ISNS1− 39 LR_G1 1 LR_FB1 38 VIN 26 HS_S 28 3 SW_FB2 2 COMP2 4 SYNC/ ROSC 31 32 33 34 ISNS2+ ISNS2− LR_G2 LR_FB2 There are many input voltage rails for the NCV8855. The main power supply input for the IC is VIN. The DRV_VPP, 5V_IC and the high−side switch drain are all driven from VIN. The DRV_VPP voltage rail is the power rail for SMPS1 & SMPS2’s gate driver circuits. The 5V_IC voltage rail is the main supply for the IC. The VIN_SW rail is the supply rail for SMPS2’s internal upper MOSFET. VIN_SW is directly tied to the drain of the N−channel MOSFET. SMPS2 Internal upper MOSFET LDO2 VOUT4 LDO1 VOUT3 High−Side Switch VIN DRV_VPP internal DRV_VPP regulator VIN_SW HIGH−SIDE SWITCH 37 20 7 HS_EN 5V_IC internal regulator 5V_IC AGND PGND Figure 17. SMPS1 & 2 Gate Drivers Main IC The NCV8855 has an internally set switching frequency of 170 kHz and provides an SYNC pin for external frequency synchronization. The NCV8855 is designed to operate within the range of 9 V to 18 V. The switch−mode power supplies are voltage−mode controlled and the LDO controllers drive P−channel MOSFETs as pass devices. System Enable (SYS_EN) ISNS1+ LDO1 ISNS1− LDO2 ISNS2+ ISNS2− Figure 18. The system enable (SYS_EN) pin is used to start device operation or place it in low quiescent shutdown. Driving this pin high will allow the two main internal voltage rails (DRV_VPP and 5V_IC) to power up. These voltage rails require external bypassing and have independent UVLO trip points. Both rails must be operational in order for the IC to function. After exceeding its UVLO threshold, the IC will power up the switch−mode power supplies with a soft−start. Conversely, a logic−low on the pin will power down the DRV_VPP and 5V_IC rails and place the IC in an ultra−low current shutdown state. Two additional inputs rails are ISNS1+ and ISNS2+. These inputs not only serve as the positive reference for the current sense circuit, but also serve as the supply rail for the LDO error amplifier. Startup and Shutdown Behavior The startup sequence primary depends on the system configuration. However, in every case, enable SYS_EN first. The SYNC pin must not be held at logic high before SYS_EN is enabled. Below shows typical startup and http://onsemi.com 15 NCV8855 shutdown behavior when VOUT3 is derived from VOUT1 (as shown in Figure 1). Startup and Shutdown Behavior 18.5 V 17.9 V re−start the high−side switch in the case of a TMON_HSS TSD event. If thermal monitor 2 (TMON_SW) exceeds it TSD point, the entire chip (regardless of the state of TMON_HSS) will latch off, and a SYS_EN toggle will be required to restart. Overcurrent Protection (SMPS1) VIN SYS_EN 8V_IC 5V_IC VOUT1 VOUT2 LDO_EN VOUT3 VOUT4 Natural Startup Natural Decay Controlled Soft−Star >2.2 V 2.2 V