NCV8855BMNR2G

NCV8855 Quad-Output Automotive System Power Supply IC with Integrated High-Side 2A Switch The NCV8855 is a multiple output controller / regulator IC with an integrated high−side load switch. The NCV8855 addresses automotive radio system and instrument cluster power supply requirements. In addition to the high−side load switch, the NCV8855 includes a switch−mode power supply (SMPS) buck controller, a 2.5 A SMPS buck regulator and two low dropout (LDO) linear regulator controllers. The NCV8855 in combination with the ultra−low quiescent current NCV861x IC forms an eight−output automotive radio or instrument cluster power solution. The NCV8855 has an internally set switching frequency of 170 kHz, with a SYNC pin for external frequency synchronization. The NCV8855 is intended to supply power to various loads, such as a tuner, CD logic, audio processor and CD / tape control within a car radio. The high−side switch can be used for a CD / tape mechanism or switching an electrically−powered antenna or display unit. In an instrument cluster application, the NCV8855 can be used to power graphics display, flash memory and CAN transceivers. In addition, the high−side switch can be used to limit power to a TFT display during a battery over−voltage condition. Features • • • • • • • • • • • • • • < 1 mA Shutdown Current Meets ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions VIN Operating Range 9.0 to 18.0 V 1 SMPS Controller with Adjustable Current Limit 1 SMPS Regulator with Internal 300 mW NMOS Switch 2 LDO Controllers with Current Limit and Short Circuit Protection 1 High−side Load Switch with Internal 300 mW NMOS FET Adjustable Output Voltage for All Controllers / Regulators 800 mV, $1% Reference Voltage System Enable Pin Single Enable Pin for Both LDO Controllers Independent Enable for High−side Load Switch Thermal Shutdown with Thermal Warning Indicator This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM 1 1 40 NCV8855 AWLYYWWG 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package NCV8855BMNR2G QFN−40 (Pb−Free) Shipping† 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • Automotive Radio • Instrument Cluster, Driver Information System (DIS) © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. 1 1 Publication Order Number: NCV8855/D NCV8855 TYPICAL APPLICATION SCHEMATIC SHOWING DETAILED BLOCK DIAGRAM DRV_VPP SYS _EN 22 5 Bandgap ILIMIT V1 5V_IC VIN DRV_VPP VIN VR VIN Q1 GH1 SN1 VOUT1 Q2 GL1 OCSET LDO 11 24 23 21 QS CLK1 CLK2 QR R 9 ILIMIT RAMP2 27 EA 29 30 RAMP1 70% VREF SCP DRV_VPP 3 OSC 180° out−of−phase 5V_IC HOT_FLG 8 TWARN1 TWARN2 ISNS1+ VOUT1 ISNS1− VOUT3 Q3 LR_G1 LR_FB1 39 6 TSD1 Int. rails and references TSD2 40 ILIMIT V REF EA EA HS_OUT HS_S 26 28 SN2 VOUT2 SW_FB2 COMP2 SYNC HS_EN LDO_EN 31 33 34 ISNS2+ VBATT ISNS2− LR _G2 Q4 VOUT4 LR_FB2 SCP 70% VREF VIN ILIMIT 38 SCP VBATT VBATT 5V_IC 32 VREF 1 4 7 Main Logic / Fault Control UVLO VIN_SW V REF EA CLK1 RAMP1 CLK2 RAMP2 BST2 D1 2 SCP DRAIL SS2 ILIMIT V REF COMP1 10 S Q SS1 SW_FB1 36 25 Gate Control VBATT 5V_IC I LIMIT V1 VR BST1 35 70% VREF VIN Control Current Limit Vneg clamp 37 CLK1 Vhigh clamp Charge Pump 20 AGND PGND Figure 1. Application Schematic / Block Diagram Components D1 Part Number Value Manufacturer MBRS4201T3 200 V, 4 A, Schottky, 0.61 V Vf, SMC ON Semiconductor Q1, Q2 NTD24N06 60 V, N type MOSFET, 32 mW , DPAK ON Semiconductor Q3, Q4 NTD20P06LT4G −60V, P type MOSFET, 130 mW, DPAK ON Semiconductor http://onsemi.com 2 NCV8855 PIN FUNCTION DESCRIPTIONS Pin No. Symbol Description 5 SYS_EN Main enable pin for the IC. A logic high on this pin will enable the part. Leaving this pin floating or driving it to ground will place the IC in shutdown mode. 6 LDO_EN Enable pin for both LDO controllers. A logic high on this pin will enable both LDO controllers. If this pin is left floating, an internal pull down keeps the LDOs disabled. 7 HS_EN Enable pin for the high−side load switch. A logic high on this pin will enable the HSS. If this pin is left floating, an internal pull down keeps the HSS disabled. 8 HOT_FLG Thermal warning indicator. This pin provides an early warning signal of an impending thermal shutdown. 22 DRV_VPP Output of the internal 7.2 V linear regulator. Bypass this pin with 1 mF to ground. 35 5V_IC Output of the internal 5 V linear regulator. Bypass this pin with 0.1 mF to ground. 36 DRAIL Output of the internal 4.2 V linear regulator. Bypass this pin with 0.1 mF to ground. 4 SYNC Synchronization pin. Use this pin to synchronize the internal oscillator to an external clock. If synchronization is not used, connect this pin to AGND. 37 AGND Analog ground. Reference point for internal signals. SWITCH−MODE POWER SUPPLY 1 (SMPS1) PIN CONNECTIONS 27 OCSET Overcurrent set pin, used to set the current limit threshold. A resistor connected from this pin and the upper MOSFET Drain sets the current limit protection level. 29 SW_FB1 Output voltage feedback pin. Connect a resistor divider network to VOUT1 to set the desired output voltage. 30 COMP1 This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB1 pin to compensate the voltage-mode control feedback loop. 25 BST1 This pin is the supply rail for the upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST1) between this pin and the SN1 pin. A typical value for CBST1 is 0.1 mF. 24 GH1 GH1 is the output pin of the internal upper N−Channel MOSFET gate driver. Keep the trace from this pin to the gate of the upper MOSFET as short as possible to achieve the best turn−on and turn−off performance and to reduce electro−magnetic emissions. 23 SN1 This pin is the return path of the upper floating gate driver. Connect this pin to the source of the upper MOSFET. This pin is also used to sense the current flowing through the upper MOSFETs. 21 GL1 GL1 is the output pin of the synchronous rectifier gate driver. Connect this pin to the lower N−channel MOSFET. 20 PGND This pin is the return path for SMPS1 lower MOSFET driver current. Connect this pin to the source of the lower MOSFET. PINS NOT INTERNALLY CONNECTED TO SILICON EP − 12 thru 19 Exposed pad of QFN package. Connect to printed circuit board ground to improve thermal performance. These pins can be left floating or tied to ground to improve thermal performance. SWITCH−MODE POWER SUPPLY 2 (SMPS2) PIN CONNECTIONS 10 VIN_SW This pin is the supply rail for the internal upper N−Channel MOSFET. Bypass this pin with a local ceramic capacitor. Additional bulk capacitance may be required based off output requirements. Refer to application section for more information. 3 SW_FB2 Output voltage feedback pin. Connect a resistor divider network to VOUT2 to set the desired output voltage. 2 COMP2 This pin is the output of the error amplifier and the non−inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB2 pin to compensate the voltage−controlled feedback loop. 11 BST2 This pin is the supply rail for the internal upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST2) between this pin and the SN2 pin. A typical value for CBST2 is 0.1 mF. 9 SN2 Source output of the internal upper N−channel MOSFET. http://onsemi.com 3 NCV8855 PIN FUNCTION DESCRIPTIONS Pin No. Symbol Description LOW DROPOUT LINEAR REGULATOR CONTROLLER 1 (LDO1) PIN CONNECTIONS 38 LR_FB1 LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. 1 LR_G1 Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element. 40 ISNS1+ Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. 39 ISNS1− Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element. LOW DROPOUT LINEAR REGULATOR CONTROLLER 2 (LDO2) PIN CONNECTIONS 34 LR_FB2 LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. 33 LR_G2 Error amplifier output of the LDO controller. Connect to gate of P−Channel MOSFET pass element. 31 ISNS2+ Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. 32 ISNS2− Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element. HIGH−SIDE LOAD SWITCH (HSS) PIN CONNECTIONS 26 VIN 28 HS_S This pin is the supply rail for the internal high−side load switch, DRV_VPP and 5V_IC. Bypass this pin with a 1 mF ceramic capacitor. Source node output of the internal high−side N−Channel MOSFET load switch. MAXIMUM RATINGS (Voltages are with respect to AGND unless noted otherwise) Pin Name Value Unit −0.3 to 30 V Negative Transient (t < 50 ns) (SN1, SN2) −2 V Max dc voltage: 5V_IC 6 V Max dc voltage (GH1, BST1, SN1, SN2, BST2, HS_S) Max dc voltage: DRV_VPP 9 V Max dc voltage (BST1 & GH1w/respect to SN1, GL1, BST2 w/respect to SN2) −0.3 to 15 V Max dc voltage (OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2) −0.3 to 40 V Peak Transient (ES−XW7T−1A278−AB Test Pulse G – Loaded Conditions) (OCSET, ISNS1+, ISNS1−, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2−, LR_G2) −0.3 to 45 V Max dc voltage (SW_FB1, COMP1, LR_FB1, LDO_EN, HOT_FLG, SW_FB2, COMP2, LR_FB2, HS_EN, SYS_EN, SYNC) −0.3 to 7 V Max dc voltage: PGND −0.3 to 0.3 V Maximum Operating Junction Temperature Range, TJ −40 to 150 °C Maximum Storage Temperature Range, TSTG −55 to +150 °C Peak Reflow Soldering Temperature: Pb−Free 60 to 150 seconds at 217°C 260 peak °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 NCV8855 ATTRIBUTES Description Symbol Value Unit RqJA 36 °C/W RqJC 3 °C/W 1 2 150 kV kV V Thermal Characteristic RqJA generated from 1 sq in / 1 oz copper 1 sided PCB ESD Capability Human Body Model (SN1, SN2) Human Body Model (All Others) Machine Model Moisture Sensitivity Level MSL 1 RECOMMENDED OPERATING CONDITIONS Description Value VBATT range (refer to Figure 1) 9 V to 18 V Ambient Temperature range −40°C to 105°C ISNS2+ LR_G2 ISNS2− LR_FB2 5V_IC DRAIL AGND LR_FB1 ISNS1− ISNS1+ LR_G1 COMP1 1 COMP2 SW_FB1 SW_FB2 HS_S OCSET SYNC/ROSC SYS_EN VIN Top View BST1 LDO_EN HS_EN GH1 HOT_FLG SN1 SN2 DRV_VPP VIN_SW GL1 PGND BST2 Figure 2. ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Supply Current and Operating Voltage Range VIN_SW quiescent current No Switching, VSW_FB2 = 1V, SN2 = PGND1, TJ = 25°C VIN_SW shutdown current 175 100 500 nA VIN rising 18 18.5 19 V High VIN detect hysteresis VIN falling 0.2 0.6 1 VIN quiescent current TJ = 25°C VIN shutdown current SYS_EN = 0 V, TJ = 25°C High VIN detect voltage SYS_EN = 0 V, TJ = 25°C mA VOVP 4 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 5 100 mA 500 nA NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit TJ = 25°C −40°C v TJ v 150°C 0.792 0.784 0.8 0.808 0.816 V 5V_IC UVLO threshold voltage V5V_IC rising 4.00 4.35 4.70 V 5V_IC UVLO hysteresis V5V_IC falling 100 150 300 mV Voltage range No load 4.8 5 5.2 V 10 21 50 mA SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Internal Voltage Reference Internal voltage reference range VREF Internal Linear Regulator 5 V Supply Rail Current limit Load regulation 1mA v I5V_IC v 10 mA 50 mV Line regulation I5V_IC = 5 mA, 9 V v VIN v 18 V 100 mV Internal DRV_VPP Supply Rail DRV_VPP UVLO threshold voltage VDRV_VPP rising 4.00 4.35 4.70 V DRV_VPP UVLO hysteresis VDRV_VPP falling 100 150 300 mV No load 6.9 7.1 7.3 V 30 67 110 mA Voltage range VDRV_VPP Current limit Load regulation 1 mA v IDRV_VPP v 25 mA 50 mV Line regulation IDRV_VPP = 1 mA, 9 V v VIN v 18 V 200 mV Dropout voltage IDRV_VPP = 25 mA, DVDRV_VPP = 2 % 400 mV 185.3 kHz 2.0 V 5 5 10 mA 100 Oscillator Oscillator frequency fSW 154.7 170 SYNC Logic high Logic low 0.8 Pull down current VSYNC = 5 V VSYNC = 0.8 V Leakage current SYS_EN = 0 V, VSYNC = 5 V Clock synchronization range 2 V 500 nA 190 255 kHz Synchronization delay to SMPS1 From falling SYNC edge 200 400 ns Synchronization delay to SMPS2 From rising SYNC edge 200 400 ns Minimum SYNC pulse width (HIGH) SMPS1 synchronizing 50 ns Minimum SYNC pulse width (LOW) SMPS2 synchronizing 50 ns 160 °C 20 °C Thermal Monitoring (TMON_HSS, High−side junction temperature monitor) Thermal warning temperature TWARN1 140 TWARN1 hysteresis Thermal shutdown temperature 150 10 TSD1 Delta junction temperature (TSD1−TWARN1) 160 170 180 °C 10 20 30 °C 140 150 160 °C Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) Thermal warning temperature TWARN2 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 6 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit 20 °C SUPPLY VOLTAGES AND SYSTEM SPECIFICATION Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) TWARN2 hysteresis Thermal shutdown temperature 10 TSD2 Delta junction temperature (TSD2−TWARN2) 160 170 180 °C 10 20 30 °C 0.4 V 500 nA HOT_FLG Voltage low threshold TJ > TWARN[x], 1 kW pullup to 5 V Leakage current 1 kW pull−up to 5 V, TJ = 25°C Sink capability VHOT_FLG = 0.8 V 100 4.6 mA 2.0 V System Enable Logic high Logic low 0.8 Pull down resistance TJ = 25°C 500 V kW High−Side Enable HS_EN logic high 2.0 HS_EN logic low 0.8 Pull down current Leakage current VHS_EN = 5 V VHS_EN = 0.8 V IHS_EN 2 SYS_EN = 0 V, VHS_EN = 5 V V V 5 5 10 mA 100 500 nA 2.0 V LDO Enable Logic high Logic low 0.8 Pull down current Leakage current VLDO_EN = 5 V VLDO_EN = 0.8 V ILDO_EN 2 SYS_EN = 0 V, VLDO_EN = 5 V V 5 5 10 mA 100 500 nA SWITCH−MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS Over Current Protection OCSET current sink ROCSET = 10 kW connected to 13.2 V OCSET leakage current SYS_EN = 0 V, VOCSET = 13.2 V, TJ = 25°C OCSET comparator differential range (Note 1) OCSET comparator common−mode range (Note 1) Current limit response time From rising edge of SN1 100 Short circuit threshold voltage SCTH1 Short circuit protection startup delay 45 55 65 mA 100 500 nA 50 750 mV 4.0 19 V 275 ns 200 VSW_FB1 % of VREF 75 80 85 % From SYS_EN rising edge, % of tSS1, SW_FB1 = 0.5 V, (Note 2) 100 125 150 % 3 5 7 ms Internal Soft−Start Soft−start time tSS1 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 7 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SWITCH−MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS Error Amplifier Dc gain (Note 1) 70 85 dB Gain−bandwidth product (Note 1) 8 10 MHz SW_FB1 input bias current SW_FB1 = 0.8 V 100 nA Input offset voltage (Note 1) 800 mV Slew rate CCOMP1 = 50 pF, $1 mA dc load Slew rate within ramp voltage levels (Note 1) COMP1 source current VCOMP1 = 2.2 V 1.5 8 mA VCOMP1 = 3.2 V 1.6 8 mA VCOMP1 = 2.2 V 1.1 8 mA VCOMP1 = 1.1 V 0.7 8 mA 1.05 V COMP1 sink current Minimum COMP1 voltage ICOMP1 = 500 mA Maximum COMP1 voltage ICOMP1 = 2 mA 6 8 V/ms 3.3 V Ramp maximum voltage 2.8 3.0 3.2 V Ramp minimum voltage 1.1 1.2 1.3 V 1.6 1.8 2.0 V Ramp voltage amplitude VRAMP1 Duty Cycle Limitations Minimum off time tMINOFF1 GH1 falling to GL1 rising 80 140 200 ns Minimum pulse width tMINON1 GH1 rising to GH1 falling 120 250 300 ns Gate Driver GH1 source current VGH1 – VSN1 = 4 V, TJ = 25°C 1.5 A GH1 sink current VGH1 – VSN1 = 2 V, TJ = 25°C 1.5 A GL1 source current VGL1 – PGND = 4 V, TJ = 25°C 1.5 A GL1 sink current VGL1 – PGND = 1 V, TJ = 25°C 1.5 A SN1 falling to GL1 rising, non−overlap time tNOLT GL1 falling to GH1 rising, non−overlap time SN1 falling non−overlap threshold voltage 1.0 GL1 falling non−overlap threshold voltage 30 70 ns 30 70 ns 1.8 3.0 V 2 SN1 falling override timer V 50 100 150 ns Internal current limit 2.5 3.05 4.2 A Current limit blanking time 100 200 ns SWITCH−MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS Over Current Protection Short circuit threshold voltage Short circuit protection startup delay SCTH2 VSW_FB2 % of VREF 75 85 95 % From SYS_EN rising edge, % of tSS2, SW_FB2 = 0.5 V 100 125 150 % 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 8 NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit SYNC floating 3 5 7 ms Dc gain (Note 1) 70 85 dB Gain−bandwidth product (Note 1) 8 10 MHz SW_FB2 input bias current SW_FB2 = 0.8 V SWITCH−MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS Internal Soft−start Soft−start time tSS2 Error Amplifier 100 Input offset voltage 500 800 CCOMP2 = 50 pF, ±1 mA dc load Slew rate within ramp voltage levels (Note 1) COMP2 source current VCOMP2 = 2.2 V 1.5 8 mA VCOMP2 = 3.2 V 1.6 8 mA VCOMP2 = 2.2 V 1.1 8 mA VCOMP2 = 1.1 V 0.7 8 mA 1.05 V Minimum COMP2 voltage ICOMP2 = 500 mA Maximum COMP2 voltage ICOMP2 = 2 mA 8 mV Slew rate COMP2 sink current 6 nA V/ms 3.3 V Ramp maximum voltage 2.8 3.0 3.2 V Ramp minimum voltage 1.1 1.2 1.3 V 1.6 1.8 2.0 V Ramp voltage amplitude VRAMP2 Duty Cycle Limitations Minimum off time tMINOFF2 SN2 falling to SN2 rising 80 140 200 ns Minimum pulse width tMINON2 SN2 rising to SN2 falling, 120 250 300 ns 360 mW Switching MOSFET N−channel MOSFET RDS(on) TJ = 25°C, Guaranteed at Probe 300 Turn−on time SN2 → 0 V to 13.2 V, IOUT = 1 A (inductive load), TJ = 25°C 30 ns Turn−off time SN2 → 13.2 V to 0 V, IOUT = 1 A (inductive load), TJ = 25°C 30 ns LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS Output Voltage Regulation Output voltage accuracy VLR_FB1 tied to VOUT3 directly, NTD20P06L pass device Output voltage line regulation IOUT3 = 10 mA, 4.5 V v VISNS1+ v 5.5 V, NTD20P06L pass device −0.25 Output voltage load regulation 1 mA v IOUT3 v 500 mA, VISNS1+ = 5 V, NTD20P06L pass device −0.5 Output load capacitance range COUT3 Output load capacitance ESR range Power supply ripple rejection −2 2 % 0.01 0.25 % 0.2 0.5 % (Note 1) 10 100 mF (Note 1) 0.01 5 W PSRR1 NTD20P06L pass device (Note 1) VSNS1 VISNS1+ – VISNS1− 60 dB Current Limit Current limit threshold voltage 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 9 90 110 130 mV NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS Current Limit ISNS1+ leakage current IISNS1+ SYS_EN = 0, TJ = 25°C, VISNS1+ = 13.2 V 100 500 nA ISNS1− leakage current IISNS1− SYS_EN = 0, TJ = 25°C, VISNS1− = 13.2 V 100 500 nA Short circuit threshold voltage VLR_FB1 % of VREF 60 70 80 % Short circuit blanking time From rising edge of LDO_EN 10 12 14 ms 100 500 nA 10 11.7 13.5 V 2 % Error Amplifier Feedback bias current LR_FB1 = 0.5 V Maximum |VGS| 2 mA, internally clamped LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO2, VOUT4) SPECIFICATIONS Output Voltage Regulation Output voltage accuracy VLR_FB2 tied to VOUT4 directly, NTD20P06L pass device Output voltage line regulation IOUT4 = 10 mA, 9 V v VISNS2+ v 18 V, NTD20P06L pass device −0.25 0.01 0.25 % Output voltage load regulation 1 mA v IOUT4 v 500 mA, NTD20P06L pass device −0.5 0.2 0.5 % Output load capacitance range COUT4 Output load capacitance ESR range Power supply ripple rejection −2 (Note 1) 10 100 mF (Note 1) 0.01 5 W PSRR2 NTD20P06L pass device (Note 1) Current limit threshold voltage VSNS2 VISNS2+ – VISNS2− ISNS2+ leakage current IISNS2+ ISNS2− leakage current IISNS2− 60 dB Current Limit 90 110 130 mV SYS_EN = 0, TJ = 25°C, VISNS2+ = 13.2 V 100 500 nA SYS_EN = 0, TJ = 25°C, VISNS2− = 13.2 V 100 500 nA Short circuit threshold voltage VLR_FB2 % of VREF 60 70 80 % Short circuit blanking time From rising edge of LDO_EN 10 12 14 ms 100 500 nA 10 11.7 13.5 V IHSSLIM 2.00 2.80 3.64 A tSCP 1.300 1.506 1.800 ms 4.0 4.5 5.0 V 3.3 3.95 4.6 V 2.600 3.012 3.600 ms 16.0 16.6 V Error Amplifier Feedback bias current LR_FB2 = 0.5 V Maximum |VGS| 2 mA, internally clamped High−side Load Switch (HSS) Current Limit Peak current limit Short circuit timeout Short circuit threshold voltage Current overload threshold voltage VSCP(HS_S) VDS VIN – VHS_S Current overload timeout Voltage Clamp Source output positive clamping voltage VCLAMP+ 1 mA v IHS_S v 2 A VCLAMP+ v VIN v VOVP 15.4 Source output negative clamping voltage VCLAMP− ILOADSW = 50 mA −1.6 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. http://onsemi.com 10 V NCV8855 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Symbol Conditions Min Typ Max Unit High−side Load Switch (HSS) MOSFET HSS RDS(on) VGS(HSS) = 8 V 233 442 mW HSS dropout voltage IHS_S = 1 A 233 442 mV Turn On/Off Turn on time (resistive load) RHS_S = 6.6 W, 90% VIN 40 80 120 ms Turn off time RHS_S = 6.6 W, 10% VIN 50 125 200 ms 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. 1.506 msec VHS_S ILOAD 3.012 msec VDS w 3.75 V VDS=3.75V 4.5V 2.8A HS_EN HS Current Overload (Latched shutdown of HS only) Figure 3. http://onsemi.com 11 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 0.808 169.4 169.2 169.0 0.804 168.8 VREF (V) fSW (kHz) 168.6 168.4 168.2 0.802 0.800 168.0 167.8 0.798 167.6 −25 0 25 50 75 100 125 0.796 −50 150 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Switching Frequency vs. Junction Temperature Figure 5. Reference Voltage vs. Junction Temperature 3.2 65 3.1 60 3.0 150 55 2.9 2.8 2.7 50 45 40 2.6 35 2.5 2.4 −50 −25 TJ, JUNCTION TEMPERATURE (°C) tNOL (ns) HSS CURRENT LIMIT (A) 167.4 −50 −25 0 25 50 75 100 125 30 −50 150 −25 TJ, JUNCTION TEMPERATURE (°C) 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 6. HSS Current Limit vs. Junction Temperature Figure 7. SMPS1 Non−Overlap Time vs. Junction Temperature 7.18 80.8 80.6 80.4 80.2 7.14 SCTH (%) VDRV_VPP (V) 7.16 7.12 7.10 SMPS2 80.0 79.8 79.6 SMPS1 79.4 79.2 79.0 7.08 78.8 7.06 −50 −25 0 25 50 75 100 125 150 78.6 −50 TJ, JUNCTION TEMPERATURE (°C) −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 9. Short Circuit Threshold vs. Junction Temperature Figure 8. Drive Voltage vs. Junction Temperature http://onsemi.com 12 150 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 220 1.820 1.815 215 SMPS2 210 1.805 tMINON (ns) VRAMP (V) 1.810 SMPS1 1.800 205 200 1.795 195 1.790 190 −25 0 25 50 75 100 125 185 −50 150 25 50 75 100 125 Figure 10. Ramp Amplitude vs. Junction Temperature Figure 11. Minimum On Time vs. Junction Temperature 56.6 0.12 56.4 150 56.2 0.10 0.08 56.0 0.06 55.8 55.6 0.04 55.4 0.02 55.2 −25 0 25 50 75 100 125 55.0 −50 150 −25 TJ, JUNCTION TEMPERATURE (°C) 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. OCSET Leakage Current vs. Junction Temperature Figure 13. OCSET Current Sink vs. Junction Temperature 2.5 109.5 109.0 2.0 108.5 VSNS (mV) IHS_EN, (mA) 0 TJ, JUNCTION TEMPERATURE (°C) 0.14 0.00 −50 −25 TJ, JUNCTION TEMPERATURE (°C) IOCSET, (mA) IOCSET_L, (mA) 1.785 −50 1.5 108.0 1.0 LDO1 107.5 0.5 0.0 −50 107.0 −25 0 25 50 75 100 125 150 106.5 −50 TJ, JUNCTION TEMPERATURE (°C) LDO2 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 15. LDO Current Limit vs. Junction Temperature Figure 14. HS EN Leakage Current vs. Junction Temperature http://onsemi.com 13 150 NCV8855 TYPICAL PERFORMANCE CHARACTERISTICS 0.18 0.16 ILDO_EN (mA) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 16. LDO EN Leakage Current vs. Junction Temperature http://onsemi.com 14 150 NCV8855 THEORY OF OPERATION Device Description Linear Regulator Enable (LDO_EN) The NCV8855 is a multiple output controller / regulator IC with an integrated high−side load switch. The NCV8855 will address automotive radio system and instrument cluster power supply requirements. In addition to the high−side load switch, the NCV8855 comprise a switch−mode power supply (SMPS) buck controller, a 2 A SMPS buck regulator, and two low dropout linear regulator controllers (LDO). The NCV8855 in combination with the ultra−low Iq NCV861x IC forms an eight output automotive radio or instrument cluster power solution. The low−dropout linear regulators (LDOs) have a dedicated enable pin. This pin controls the startup and shutdown of the LDOs. The SYS_EN pin must be logic high for this pin to function. It is possible to drive this pin high coincidentally with SYS_EN, but the LDO outputs will not startup until DRV_VPP and 5V_IC have increased above its UVLO thresholds. High−Side Switch Enable (HS_EN) The high−side switch enable controls only the high−side switch. Similar to LDO_EN, the SYS_EN pin must be logic high for this pin to function. The voltage level on all enable pins have been designed to work with 3.3 V or 5 V logic. DRV_VPP 5V_IC 22 35 6 LDO_EN SYS_EN 5 MAIN BST1 25 GH1 24 SN1 23 9 SN2 SMPS2 VOUT2 OCSET 27 SW_FB1 29 COMP1 30 VIN 26 HS_S 28 3 SW_FB2 2 COMP2 LDO2 VOUT4 4 SYNC/ ROSC LDO1 VOUT3 ISNS1+ 40 ISNS1− 39 LR_G1 1 LR_FB1 38 There are many input voltage rails for the NCV8855. The main power supply input for the IC is VIN. The DRV_VPP, 5V_IC and the high−side switch drain are all driven from VIN. The DRV_VPP voltage rail is the power rail for SMPS1 & SMPS2’s gate driver circuits. The 5V_IC voltage rail is the main supply for the IC. The VIN_SW rail is the supply rail for SMPS2’s internal upper MOSFET. VIN_SW is directly tied to the drain of the N−channel MOSFET. 11 BST2 10 VIN_SW SMPS1 VOUT1 GL1 21 IC Power (VIN, VIN_SW, DRV_VPP, 5V_IC) 8 HOT_FLG HIGH−SIDE SWITCH 37 31 32 33 34 ISNS2+ ISNS2− LR_G2 SMPS2 High−Side Internal upper Switch LR_FB2 VIN_SW MOSFET VIN 7 HS_EN DRV_VPP 5V_IC internal internal 20 DRV_VPP regulator regulator 5V_IC AGND PGND Figure 17. SMPS1 & 2 Gate Drivers The NCV8855 has an internally set switching frequency of 170 kHz and provides an SYNC pin for external frequency synchronization. The NCV8855 is designed to operate within the range of 9 V to 18 V. The switch−mode power supplies are voltage−mode controlled and the LDO controllers drive P−channel MOSFETs as pass devices. Main IC ISNS1+ ISNS2+ LDO1 LDO2 ISNS1− ISNS2− Figure 18. System Enable (SYS_EN) Two additional inputs rails are ISNS1+ and ISNS2+. These inputs not only serve as the positive reference for the current sense circuit, but also serve as the supply rail for the LDO error amplifier. The system enable (SYS_EN) pin is used to start device operation or place it in low quiescent shutdown. Driving this pin high will allow the two main internal voltage rails (DRV_VPP and 5V_IC) to power up. These voltage rails require external bypassing and have independent UVLO trip points. Both rails must be operational in order for the IC to function. After exceeding its UVLO threshold, the IC will power up the switch−mode power supplies with a soft−start. Conversely, a logic−low on the pin will power down the DRV_VPP and 5V_IC rails and place the IC in an ultra−low current shutdown state. Startup and Shutdown Behavior The startup sequence primary depends on the system configuration. However, in every case, enable SYS_EN first. The SYNC pin must not be held at logic high before SYS_EN is enabled. Below shows typical startup and http://onsemi.com 15 NCV8855 shutdown behavior when VOUT3 is derived from VOUT1 (as shown in Figure 1). re−start the high−side switch in the case of a TMON_HSS TSD event. If thermal monitor 2 (TMON_SW) exceeds it TSD point, the entire chip (regardless of the state of TMON_HSS) will latch off, and a SYS_EN toggle will be required to restart. Startup and Shutdown Behavior 18.5 V 17.9 V VIN SYS_EN 8V_IC 5V_IC Overcurrent Protection (SMPS1) >2.2 V Overcurrent protection for SMPS1 is implemented via VDS(on) sensing of the upper MOSFET. At the beginning of each switching cycle, after a short blanking time, the voltage is sampled across the upper MOSFET and compared to the threshold set by ROCSET. 2.2 V