NCV891930MW00AR2G

Low Quiescent Current 2 MHz Automotive Synchronous Buck Controller NCV891930 • • • • Radio and Infotainment Instrumentations & Clusters ADAS (safety applications) Telematics © Semiconductor Components Industries, LLC, 2018 May, 2020 − Rev. 4 1 24 ZZZZZ 30XX ALYWG G ZZZZZ XX A L Y W G = V8919, 8919A = 00, 01 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS VSW GL PGND 24 23 22 21 20 VCCEXT GH (Top View) 19 18 V_CS 1 CSP 2 17 VIN CSN 3 16 DBIAS VOUT 4 15 VSEL NC 5 14 V_SO EN 6 8 9 10 11 13 12 SYNCI 7 RSTB GND GND Typical Applications MARKING DIAGRAM SSC • 30 mA Operating Current at No Load 75 mV Current Limit Sensing Capable of 45 V Load Dump Board Selectable Fixed Output Voltages With Lockout 2 MHz Operating Frequency Adaptive Non−Overlap Circuitry Integrated Spread Spectrum Logic level Enable Input Can be Tied Directly to Battery Short Circuit Protection Pulse Skip Battery monitoring for UVLO and Overvoltage Protection Thermal Shutdown (TSD) Adjustable Soft−Start SYNCI, SYNCO, Enable, RSTB, ROSC QFN Package with Wettable Flanks (pin edge plating) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 This Device is Pb−Free, Halogen Free/BFR Free and is RoHS Compliant Note: With wettable flanks – meets JEDEC MO220 ROSC • • • • • • • • • • • • • • • 1 24 QFNW24 4x4, 0.5P CASE 484AE BST Features www.onsemi.com NC The NCV891930 is a 2 MHz fixed−frequency low quiescent current buck controller with spread spectrum that operates up to 38 V (typical). It may be synchronized to a clock or to separate NCV891930. Peak current mode control is employed for fast transient response and tight regulation over wide input voltage and output load ranges. Feedback compensation is internal to the device, permitting design simplification. The NCV891930 is capable of converting from an automotive input voltage range of 3.5 V (4.5 V during startup) to 18 V at a constant base switching frequency above the sensitive AM band, eliminating the need for costly filters and EMI countermeasures. The switching frequency folds back to 1 MHz for input voltages between 20 V up to 38 V (typical). Under load dump conditions up to 45 V the regulator shuts down. A high voltage bias regulator with automatic switchover to an external 5 V bias supply is used for improved efficiency. Several protection features such as UVLO, current limit, short circuit protection, and thermal shutdown are provided. High switching frequency produces low output voltage ripple even when using small inductor values and an all−ceramic output filter capacitor, forming a space−efficient switching solution. (410 kHz version offered with NCV881930) VDRV SYNCO ORDERING INFORMATION See detailed ordering and shipping information on page 31 of this data sheet. 1 Publication Order Number: NCV891930/D NCV891930 VOUT RSTB SYNCI V_CS CSN VOUT CSP 2 1 NCV891930 − 23 9 22 10 BST 24 8 Q1 GH 11 GL 14 15 16 Q2 + NVMFS5C468NL C VOUT − VCCEXT 19 18 17 RS L PGND 20 12 13 NVMFS5C468NL CBST VSW 21 GND SYNCO RSYNCI + VIN VDRV GND 3 VIN SSC 4 DBIAS ROSC 7 5 VSEL ROSC 6 V_SO NC NC EN VIN VIN Figure 1. 5 V Application Schematic Example RSTB SYNCI RSYNCI V_CS CSP CSN VOUT + 1 NCV891930 VIN − 8 23 9 22 10 21 GND 11 12 13 BST 24 Q1 GH GL 15 16 Q2 NVMFS5C468NL − Open or + 5 V VIN Figure 2. 3.3 V Application Schematic Example www.onsemi.com 2 + C VOUT VCCEXT 19 18 17 RS L PGND 20 14 NVMFS5C468NL CBST VSW VDRV VOUT 2 VIN GND 3 DBIAS SSC 4 VSEL ROSC 5 V_SO ROSC 7 SYNCO NC 6 NC EN VIN NCV891930 13 SYNCI 12 ROSC 8 VCCEXT VDRV BST 17 19 18 24 LDO BYPASS 5 V LDO S R OSC 14 DBIAS 16 V_CS 1 EN 6 NON OVERLAP Q PWMOUT INTERNAL RAILS SYNCI FB GH VDRV 22 VSW 21 GL 20 PGND 2 CSP 3 CSN 4 VOUT 15 VSEL Current Limit VNCL PWM/ PULSE SKIP BANDGAP VPCL SLOPE COMP TSD OVSD UVLO FAULT SOFTSTART 23 MIN ON TIME CSA ∑ VREF VCOMP FB − V_SO Q + SYNC0 VIN Z 9 SSC RSTB 10 11 GND RSTB Figure 3. Simplified Block Diagram www.onsemi.com 3 NCV891930 PIN FUNCTION DESCRIPTION Pin No. QFN24 Pin Name Description 1 V_CS Supply input for the internal current sense amplifier. Not intended for external use. Application board requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND 2 CSP Differential current sense amplifier non−inverting input 3 CSN Differential current sense amplifier inverting input 4 VOUT 5 NC No connection (Note 1) 6 EN Logic level inputs for enabling the controller. May be connected to battery 7 NC No Connection (Note 1) 8 ROSC 9 SSC Soft−start current source output. A capacitor to ground sets the soft−start time 10 GND Signal ground. Ground reference for the internal logic, analog circuitry and the compensators 11 RSTB Reset with adjustable delay. Goes low when the output is out of regulation 12 SYNCI A logic low enables Low IQ capable operating mode. External synchronization is realized with an external clock. A logic high enables continuous synchronous operating mode (low IQ mode is disabled). Ground this pin if not used 13 SYNCO Synchronization output active in synchronous operation mode. Refer to table for activation delay when coming out of low IQ mode. Connecting to the SYNCI pin of a downstream NCV891930 results in synchronized operation 14 V_SO Supply voltage for the SYNCO output driver. Not intended for external use. Application board requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND 15 VSEL Output programmed to VSEL_LO when connected to ground or when pin is not connected. Output programmed to VSEL_HI when connected to DBIAS via a 10 kW resistor (optional). Voltage setting option will be latched prior to PWM soft−start. Latch will be reset whenever the EN pin is toggled or during a UVLO event 16 DBIAS IC internal power rail. Not intended for external use other than for VSEL. Application board requires a 0.1 mF decoupling capacitor located next to IC referenced to quiet GND 17 VIN 18 VDRV 19 VCCEXT External 5 V bias supply. Overrides internal high voltage LDO when used. Application board requires a 1 mF decoupling capacitor located next to IC referenced to PGND 20 PGND Power ground. Ground reference for the high−current path including the N−FETs and output capacitor 21 GL Push−pull driver output that swings between VDRV and PGND to drive the gate of an external low side N−FET of the synchronous buck power supply 22 VSW Terminal of the high side push−pull gate driver connected to the source of the high side N−FET of the synchronous buck power supply 23 GH Push−pull driver output that swings between SW and BST to drive the gate of an external high side N−FET of the synchronous buck power supply 24 BST The BST pin is the supply rail for the gate drivers. A 0.1 mF capacitor must be connected between this pin and the VSW pin. Bootstrap pin to be connected with an external capacitor for powering the high side NFET gate with SW + (VDRV – 0.5 V) and PGND. Blocking diode is internal to the IC EPAD SMPS’s voltage feedback. Inverting input to the voltage error amplifier. Connect VOUT to nearest point−of−load Use a resistor to ground to raise the frequency above default value Input voltage for controller, may be connected to battery 5 V linear regulator supply for powering NFET gate drive circuitry and supply for bootstrap capacitor Connect to pin 20 (electrical ground) and to a low thermal resistance path to the environment 1. True no connect. Printed circuit board traces are allowable. www.onsemi.com 4 NCV891930 MAXIMUM RATINGS (Voltages with respect to GND unless otherwise indicated) Rating Symbol Value Unit EN, VIN, V_CS −0.3 to 45 V Pin Voltage t ≤ 50ns VSW −0.3 to 40 −2 V Pin Voltage GH,BST −0.3 to 45 −0.3 to 7 V with respect to VSW V Pin Voltage CSN, CSP, VOUT −0.3 to 10 V Pin Voltage VDRV, GL, VCCEXT −0.3 to 7 V Pin Voltage RSTB −0.3 to 6 V Pin Voltage DBIAS, ROSC, SSC, SYNCO, V_SO, VSEL −0.3 to 3.6 V TJ(max) −40 to 150 °C TSTG −65 to 150 °C ESDHBM 2 kV DC Supply Voltage (Note 2) Operating Junction Temperature Storage Temperature Range ESD Capability, Human Body Model (Note 3) Moisture Sensitivity Level MSL 1 − Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 4) TSLD 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114). 4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. THERMAL CHARACTERISTICS Rating Thermal Characteristics (Note 5) Thermal Resistance, Junction−to−Ambient (Note 6) Thermal Characterization Parameter, Junction−to−Top (Note 6) Symbol Value RθJA yJT 50 13 Unit °C/W 5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 6. Values based on copper area of 600 mm2, 4 layer PCB, 0.062 inch FR−4 board with 2 oz. copper on top/bottom layers and 1 oz. copper on the inside layers in a still air environment with TA = 25°C. www.onsemi.com 5 NCV891930 ELECTRICAL CHARACTERISTICS (VEN = VBAT = VIN = 4.5 V to 37 V, VBST = VSW + (VDRV – 0.5V), CBST = 0.1 mF, CDRV = 1 mF. Min/Max values are valid for the temperature range −40oC < TJ < 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation. Parameter Test Conditions Symbol Min Typ Max Unit VINLF VINLR 7.0 7.3 7.31 7.65 7.65 8.0 V VINLH 0.3 0.37 0.45 V − 5.8 − ms VFLR VFLF 18.4 18.0 − − 20 19.8 V VFLHY 0.15 0.32 0.45 V − 16 − ms VIN_LOW VIN_low threshold VIN falling VIN rising VIN_low hysteresis Response time VIN FREQUENCY FOLDBACK MONITOR (VIN_HIGH) Frequency foldback threshold VIN rising VIN falling Frequency foldback hysteresis Response time VIN OVERVOLTAGE SHUTDOWN MONITOR Overvoltage stop threshold VOVSP 37.0 38.0 39.0 V Overvoltage hysteresis VOVHY 0.5 1.0 1.5 V VIN = 13 V, EN = 0 V, TJ = 25°C IQ,SLEEP − 6.0 − mA VIN = 13 V, EN = 0 V, −40°C < TJ < 125°C IQ,SLEEP − 6.0 10 mA IQ − 30 40 mA IQ100 − 82 100 mA VDBIAS 2.0 − 2.4 V QUIESCENT CURRENT Quiescent current VIN = 13 V, EN = 5 V, No switching, TJ = 25°C VIN = 13 V, 100 mA load, VOUT = 5 V, VCCEXT = VOUT, EN = VIN, Tambient = 25°C (Not production tested. Measured on demo board, refer to application note section) DBIAS DBIAS voltage CDBIAS = 0.1 mF UNDERVOLTAGE LOCKOUT (Note 8) UVLO start threshold VIN rising VUVST 4.0 − 4.5 V UVLO stop threshold VIN falling VUVSP 3.2 − 3.5 V VUVHY − 0.9 − V − 0.8 V UVLO hysteresis ENABLE Logic low threshold voltage Will be disabled at maximum value VENLO 0 Logic high threshold voltage Will be enabled at minimum value VENHI 1.4 − − V Enable pin input Current VEN = 5 V EI,EN − 0.125 0.26 mA OUTPUT VOLTAGE Output voltage during regulation VOUT−GND resistance IOUT > 100 mA NCV891930MW00R2G 3.3 V (VSEL = GND) 5.0 V (VSEL = DBIAS) NCV891930MW01R2G 3.65 V (VSEL = GND) 4.0 V (VSEL = DBIAS) VOUT,REG EN = VENLO, VIN > 4.5 V V 3.234 4.90 3.30 5.00 3.366 5.10 3.577 3.92 3.65 4.00 3.723 4.08 RENLO,VOUT 70 100 130 W VLVSEL 0 − 0.8 V VSEL VSEL input low threshold voltage www.onsemi.com 6 NCV891930 ELECTRICAL CHARACTERISTICS (VEN = VBAT = VIN = 4.5 V to 37 V, VBST = VSW + (VDRV – 0.5V), CBST = 0.1 mF, CDRV = 1 mF. Min/Max values are valid for the temperature range −40oC < TJ < 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation. Parameter Test Conditions Symbol Min Typ Max Unit VHVSEL 2.0 − 3.3 V VSEL = DBIAS VI,SEL − 0.25 0.37 mA VOUT decreasing VOUT increasing KUVFAL KUVRIS 90 90.5 92.5 − 95 97 % Reset hysteresis (ratio of VOUT) KRES_HYS 0.5 − 2 % Noise−filtering delay tRES_FILT 5 − 25 ms 4 17 1.0 5 24 6 32 ms ms ms 1000 − − − − 600 VSEL VSEL input high threshold voltage VSEL pin input current RESET Reset threshold 1 (as a function of VOUT) Reset delay time IRSTB = 1 mA IRSTB = 500 mA IRSTB = 100 mA tRESET Reset delay modes Power good mode (no delay) Delay mode (see Detailed Operating Description) Reset output low level IRSTB = 1 mA VRESL − − 0.4 V Reset threshold 2 (as a function of VOUT) VOUT increasing VOUT decreasing KOVRIS KOVFAL 105 104 106.5 − 110 109 % VOUT Output Clamp Current VOUT = VOUT,reg(typ) + 10 % ICL,OUT 0.5 1.0 1.5 mA gM,OTA − 26.6 − mA ERROR AMPLIFIER Transconductance (Note 3) Internal to IC Compensation network Internal to IC NCV891930MW00DRG 3.3 V 5.0 V NCV891930MW01DRG 3.65 V 4.0 V RCOMP,OTA Internal to IC (refer to application note section for die distributed capacitance modeling information) mS kW − − 400 506 − − − 360 386 − − CCOMP,OTA − 190 − pF R0,OTA − 56.7 − MW NCV891930MW00DRG NCV891930MW01DRG Sa − − 29.4 39.0 − − mV/ms Switching frequency ROSC = open 4.5 V < VIN Vin_high X Synchronous mode, recirculation FET turns−off when −50 mV current sense voltage is detected. 1 MHz Disabled Enabled, 2 MHz Disabled Disabled Disabled Disabled Disabled Disabled Disabled No change in behaviour No PWM No PWM Logic−1 Pulse skip not allowed when VIN > Vin_high Soft−start X Forced PWM mode with pulse skip allowed, recirculation FET turns−off when when < 0 V current sense voltage is detected 2 MHz Vout undervoltage (KUV) X RSTB activated. Fixed frequency Vout overvoltage (KOV) X RSB activated. No PWM No change in No change in behaviour behaviour No PWM No Change in behaviour *GH off pulses will be skipped to maintain output voltage regulation whenever GH toff is less than toff,MIN occurs. www.onsemi.com 10 NCV891930 1 60 Rise Time (ns) CSS (mF) 50 0.1 GL GH 40 30 20 10 0.01 1 10 tSS (ms) 100 0 0 GL GL 25 I (mA) Q Fall Time (ns) GH GH 30 20 15 10 5 0 0 2 4 6 Load Capacitance (nF) 8 10 90 85 VCCEXT = OPEN 80 75 70 65 60 55 50 45 40 35 30 25 −50 −25 0 25 50 75 Temperature (°C) 9 79 8 78 7 77 VCSP,CSN (mV) 80 IQ,SLEEP (mA) 10 6 5 4 3 75 100 150 73 71 50 125 74 1 25 100 75 72 0 10 76 2 −25 8 Figure 7. Operating Quiescent Current vs Temperature (5 V/100 mA) Figure 6. Driver Fall Time vs Load Capacitance 0 −50 6 Figure 5. Driver Rise Time vs Load Capacitance 45 35 4 Load Capacitance (nF) Figure 4. Soft−Start Time vs Capacitance 40 2 70 −50 125 Temperature (°C) −25 0 25 50 75 100 Temperature (°C) Figure 8. Quiescent Current (Shutdown) vs Temperature Figure 9. Peak Current−Limit Threshold vs Temperature www.onsemi.com 11 125 NCV891930 100.5% 2.01 100.4% 2.008 Switching Frequency (MHz) 100.3% 100.2% VREF 100.1% 100.0% 99.9% 99.8% 99.7% 99.6% 99.5% −50 −25 0 25 50 75 Temperature (°C) 100 2.006 2.004 2.002 2 1.998 1.996 1.994 1.992 1.99 −50 125 Figure 10. VREF vs Temperature 25 50 Temperature (°C) 75 100 125 Figure 11. Oscillator Frequency vs Temperature 27 GH: High to Low 4.3 GL: Low to High 4.2 4.1 25 VIN FALLING 4 23 VIN RISING 3.9 V Non Overlap Delay (ns) 0 4.4 29 21 3.8 3.7 GH: Low to High 19 3.6 GL: High to Low 3.5 17 3.4 15 −50 −25 0 25 50 Temperature (°C) 75 100 3.3 −50 125 Figure 12. Non−Overlap Delay vs Temperature 5.1 5.06 0 25 50 Temperature (°C) 75 100 125 24 22 IDRV = 25 mA 20 5.04 18 tRESET (ms) 5.02 5 4.98 4.96 16 14 12 10 4.94 8 4.92 6 4.9 −50 −25 Figure 13. UVLO vs Junction Temperature 5.08 V −25 4 −25 0 25 50 75 100 125 0.1 Temperature (°C) 0.2 0.3 0.4 IRSTBx (mA) Figure 15. Reset Delay Time vs IRSTBx Figure 14. VDRV vs Temperature www.onsemi.com 12 0.5 NCV891930 VIN=8V VIN=18V VIN=10V VIN=20V VIN=12V VIN=22V VIN=14V VIN=34V VIN=6V VIN=16V 100 90 90 80 80 70 70 Efficiency (%) Efficiency(%) VIN=6V VIN=16V 100 60 50 40 30 VIN=14V VIN=34V 40 30 10 0 0.01 10 1000 VIN=12V VIN=22V 50 20 1 10 100 Output Current (mA) VIN=10V VIN=20V 60 20 0.1 VIN=8V VIN=18V 0 10000 0.01 Figure 16. 3.3 V Demo Board Efficiency (SYNCI = 0 V) 0.1 1 10 100 Output Current (mA) 1000 10000 Figure 17. 5 V Demo Board Efficiency (SYNCI = 0 V) DETAILED OPERATING DESCRIPTION General Preset internal slope and feedback loop compensation results in predetermined values for current sense resistors and output filtering. A capacitor technology mix of ceramic and aluminum polymer or solid aluminum electrolytic capacitors results in a cost effective solution. Non−solid aluminum electrolytic capacitors are not recommended due to their large cold temperature ESR properties. An all ceramic solution filter implementation using 10 mF capacitor (like the GCM32DR71C106KA37) was considered for Table 1 and Table 2 for a design objective of ±3% transient voltage for a 50% load transient. Tolerances used in determining the number of required capacitors were: • Initial tolerance ♦ −10% • Temperature tolerance • • −10% at 125°C DC bias voltage ♦ −0.6% for 3.3 V, −1.0% of 3.65 V, −1.5% for 4 V, −3.1% for 5 V AC RMS voltage ♦ −4.4% ♦ Additional tolerances such as aging may need to be considered during the design phase. At higher currents, optimal inductor and current sense resistor values may become limited. It may be necessary to parallel 3 resistor values to achieve the desired current sense resistor value. The manufacturer’s inductor tolerance and properties must be considered when determining the current sense resistor for desired current limiting under worst case component values. Table 1. MW891930MW00R2G VALUE RECOMMENDATIONS 3.3 V Option Output Current (A) 2 5 V Option MOSFET Inductor Value (mH) Current Sense Resistor (W) Output Capacitance (ceramic) (mF) Inductor Value (mH) Current Sense Resistor (W) Output Capacitance (Ceramic) (mF) NVTFS5C478NL 2.2 0.028 70 3.3 0.028 50 1.5 0.018 110 2.2 0.0195 80 0.0135 140 1.5 0.0135 110 NVMFD5C470NL 3 NVTFS5C478NL NVMFD5C470NL 4 NVTFS5C478NL 1.0 5 NVMFS5C468NL 0.80 0.011 180 1.2 0.011 120 6 NVMFS5C468NL 0.65 0.009 220 1.0 0.009 150 www.onsemi.com 13 NCV891930 Table 2. MW891930MW01R2G VALUE RECOMMENDATIONS 3.65 V Option Output Current (A) MOSFET (mH) Current Sense Resistor (Ω) 2 NVTFS5C478NL 2.2 0.028 1.5 Inductor Value 4 V Option (mH) Current Sense Resistor (Ω) Output Capacitance (Ceramic) (mF) 80 2.2 0.028 70 0.018 110 1.5 0.018 100 Output Capacitance (ceramic) (mF) Inductor Value NVMFD5C470NL 3 NVTFS5C478NL NVMFD5C470NL 4 NVTFS5C478NL 1.0 0.0135 150 1.2 0.0135 130 5 NVMFS5C468NL 0.80 0.011 190 1.0 0.011 170 6 NVMFS5C468NL 0.80 0.009 220 0.8 0.009 200 Input Voltage resulting from VIN, output voltage and operating losses, one or more GH turn−off may be skipped to maintain output regulation. Despite the default 2 MHz operating frequency, this skipped pulse will result in the power stage exhibiting a switching frequency of 1 MHz or less. To avoid skipping switching pulses and entering an uncontrolled mode of operation, the switching frequency is reduced by a factor of 2 when input voltage exceeds the VIN frequency foldback threshold (see Figure 18 below). Frequency reduction is automatically terminated when the input voltage drops back to below the VIN frequency voltage foldback threshold. This also helps limit the MOSFET switching power losses and reduce losses for generating the drive voltage for the Power Switches at high input voltage. Above the frequency foldback threshold, improved efficiency may be expected due to the lower switching frequency. An undervoltage lockout (UVLO) circuit monitors the input and can inhibit switching and reset the soft−start circuit if there is insufficient voltage for proper regulation. Depending on the output conditions (voltage option and loading), the NCV891930 may lose regulation and run in drop−out mode before reaching the UVLO threshold. When the input voltage is sufficiently low so that the part cannot regulate due to maximum duty cycle limitation, the high−side MOSFET can be kept on continuously for up to 32 clock cycles (16 μs), to help lower the minimum voltage at which the controller loses regulation. An overvoltage monitoring circuit automatically terminates switching and disables the output if the input exceeds 37 V (minimum). However, the NCV891930 can withstand input voltages up to 45 V. GL has a ~140 ns minimum pulse width requirement when VIN < VIN_LOW. Depending on the duty ratio requirement FSW (MHz) 2 1 3.2 4.5 37 18 20 39 45 VIN (V) Figure 18. NCV891930 Worst−Case Switching Frequency Profile vs Input Voltage www.onsemi.com 14 NCV891930 Output Voltage conditions when the SYNCI pin is logic−low. The VOUT pin sinks 1 mA when any of the following conditions are present: • SYNCI = logic−high • SYNCI is driven by an external clock • VIN < VIN_low threshold • VIN > frequency foldback threshold voltage The output may be programmed to VSEL_LO when VSEL is ground referenced. When VSEL is connected to DBIAS via an optional 10 kW resistor, the output voltage is programmed to VSEL_HI. The output voltage setting option must be selected prior to enabling the IC via the EN pin. The voltage setting option will be latched prior to initiation of soft−start. The voltage option latch will be reset whenever the EN pin is toggled or during a UVLO event. VCCEXT VIN supplies VDRV and logic power via the IC’s internal LDO. VCCEXT pin is ignored if connected to a voltage less than 5 V or is left unconnected. For improved efficiency, an external 5 V source may be connected to VCCEXT to permit bypassing of the internal LDO (Table 3). The LDO bypass efficiency improvement is reduced at lower currents when the IC enters pulse−skip mode. An IC power consumption reduction of about 250 mW has been measured on a demo board configured with NVMFS5C468NL power transistors at an input voltage of 13 V. IC−VIN A 1 mF decoupling capacitor is recommended between IC−VIN and ground. PCB layout inductance separating this decoupling capacitor and the input EMI capacitor may result in low amplitude high−Q ringing. A 1 W damping resistor between the PCB VIN and IC−VIN is recommended. Switching noise will be greater at the high side drain than at the input EMI ceramic filter capacitor. The trace providing voltage to IC−VIN should originate from the EMI ceramic filter capacitor. The VOUT pin sinks 0 mA under typical Table 3. NCV891930MW00R2G/AR2G 5 V DEMO BOARD TYPICAL IC POWER CONSUMPTION IMPROVEMENT VCCEXT = VOUT vs VCCCEXT = OPEN, IOUT > 1 A VIN (V) mW 6 8 10 12 14 16 18 9.1 88.7 151 213 279 386 448 When the NCV891930MW00R2G/AR2G is configured for a 5 V output (VSEL connected to DBIAS) and VCCEXT is connected to the power supply’s output, VFB and CSN traces must be independent from the VCCEXT power trace. VDRV circuitry gate drive current pulses circulate through the VCCEXT PCB trace. Voltage disturbance from the trace parasitic layout inductance will distort CSN and IC−VOUT measurements. The IC structure has a 2 series anode−cathode diode path between pins VCCEXT and VIN (Figure 19). If the controller VIN power source is disconnected while VCCEXT is connected to an independent external 5 V supply, the diode path will deliver current to the converter’s input. VIN pin may remain biased to VCCEXT minus 2 diode drops and could supply other devices sharing the same rail as the IC. To avoid unpredictable operating behaviour, the EN pin must be set to a logic−low state to disable PWM operation upon disconnection of the IC’s power source and independent VCCEXT power source must be disabled if the IC VIN rail is shared by other devices. Figure 19. VCCEXT to VIN Diode Path www.onsemi.com 15 NCV891930 Soft−Start Following activation of the EN pin, there will be eight ~250 ns GL pulses (500 kHz repetition rate) prior to initiation of the soft−start to charge the bootstrap capacitor. During this event, there will be no GH pulses. If VOUT is < ~0.2 V at EN activation, the pulses are not required and the logic may disable the eight GL pulses. Should the power supply output voltage foldback from current limiting, it is necessary to prevent the feedback opamp from clamping high to avoid output overshoot when current limiting ends. If the opamp feedback pin is less than 750 mV, the SSC pin voltage will be discharged to the opamp feedback voltage + 123 mV (Figure 20). Voltage returns to nominal regulation via soft−start behaviour. The NCV891930 features an externally adjustable soft−start function, which reduces inrush current and overshoot of the output voltage. Figure 20 shows a typical soft−start sequence. Soft−start is achieved by charging an external soft−start capacitor connected to the SSC pin via an internal 10 mA current source. Should the FB voltage slew rate be less than that of the SSC, the SSC pin will be clamped to V(FB) + 123 mV. Once the SSC voltage is greater than 0.75 V, the clamp is released. During soft−start, the SYNCI function is disabled and the controller will operate in diode−emulation mode. Pulse skip is allowed. The logic will enable the SYNCI function once SSC voltage exceeds 1.075 V. EN Nominal Output Voltage 75% of Nominal Voltage VOUT SSC −123 mV 1 V Reference + + FB − Lowest Dominates 2.2 V SSC 1V 123 mV FB (internal) Figure 20. Soft−Start Behaviour During Output Overload Current Limiting Event Expression tss may be used to calculate soft−start time for soft−start capacitor Cssc (Farads). t SS + t SSDLY ) C SSC 1V (s) 10 mA www.onsemi.com 16 (eq. 1) NCV891930 STATE DIAGRAM Figures 21 and 22 and illustrate the state diagram for the NCV891930. EN = LOW* EN = High, TJ < TSD – TSH,HYS, Vuv < VIN < Vov TJ > TSD Over temperature Protection Circuit Activated Shutdown Mode OVSD: VIN > Vov TJ > 85°C UVLO: VIN < Vuv Fault Logic Vcurrent _sense > VPCL Pulse Skipped Enabled SKIP GH PULSE VCCEXT > LDO Bypass Threshold IC Enabled VCCEXT < LDO Bypass Threshold Notes VSEL Voltage Option Lock *At any state, an EN low signal will bring the part into shutdown mode. ** At any state after the IC is enabled, the VCCEXT connection can be changed to bypass the internal LDO or not. Internal LDO Bypassed ** SYNCO, Spread Spectrum, and ROSC Functionality still Disabled SEND 8 GL Pulses Sent RESB and VCCEXT Active, RSTB = 0, Forced PWM Active, GL Disabled, No Spread Spectrum SSC Ramping Start Up Complete: SSC ≥ 1.075 V SSC > 1.075 V AND KUV < VOUT < KOV Default, ROSC Active, RSTB = 1 SSC < 1.075 V OR VOUT < KUV OR VOUT > KOV VIN and ROSC Dependent Frequency Logic RSTB = 0, GL Disabled SSC > 0.75 V VOUT < 0.75(VOUT) SSC Clamped to V(FB)+ 0.123 V Figure 21. NCV891930 State Diagram www.onsemi.com 17 NCV891930 VIN > VIN_HIGH VIN < VIN_LO W VIN_LO W VIN_HIGH VIN_LO W KUVRIS), an internal comparator enables a 1 mA current source discharge path on VOUT within typically 2.7 ms. The overvoltage comparator is set 7.5% above the 1 V feedback voltage reference (i.e. 1.075 V) and has a 68 mV hysteresis. Enable An EN pin ground referenced resistor is not required. The IC has a pull−down current (EI,EN). For low system IQ operating requirements, such a resistor would result in a larger input quiescent current consumption when the IC is in an enabled state. The NCV891930 is designed to accept either a logic−level signal or battery voltage as an Enable signal. However, if voltages above 45 V are expected, EN should be tied to VIN through a 10 kW resistor to limit the current flowing into the pin’s internal ESD clamp. A low signal on Enable induces a shutdown mode which shuts off the regulator and minimizes its supply current to less than 6 mA by disabling all functions. Pull−down RENLO_VOUT between IC−VOUT and IC−GND is present if VIN > 4.5 V to permit discharging the power supply output voltage. Once the IC is enabled, a soft−start is always initiated. The IC has internal filtering to prevent spurious operation from noise on EN. There is a tSSDLY delay between the EN command entering a logic−high state and initiation of soft−start activity on pin SSC. There is an approximately 15 μs delay between the EN command entering a logic−low state and cessation of PWM activity. 200 ns GH 70 ns GL 100 ns Figure 27. Gate Drive Waveforms for VSW < 0.4 V Within 70 ns of GH Going Low 200 ns GH GL > 100 ns Figure 28. Gate Drive Waveforms for VSW > 0.4 V After 70 ns of GH Going Low Feedback Voltage Error Amplifier An operational transconductance amplifier (OTA) is used to condition the feedback voltage information. The OTA output can sink/source up to 3 μA. During normal operation, the minimum error amplifier voltage operates between a minimum of 1.0 V and 2.2 V. During startup, there is no minimum clamp voltage on the OTA output. At light load, the logic will enter pulse−skip operating mode. During pulse−skip mode the minimum voltage clamp is 0.975 V, changing to 1.075 V during initial low frequency pulse burst (up to 3 pulses). The voltage feedback and compensation networks are represented in Figure 29. ZU(s) and ZL(s) are resistor networks used as the input voltage feedback divider. Ro and Co are the OTA output impedance characteristic. Zcomp(s) is the OTA compensation network establishing the cross−over frequency and phase margin. Block A(s) is a level shift block having an AC gain of 0.1875. The silicon implementation of the compensation resistor in ZU(s), ZL(s), and Zcomp(s) consists of numerous series connected high resistance segments. Each resistor segment has a very low parasitic capacitance to ground. On a cumulative basis, the distributed capacitances may not be neglected as they affect the feedback loop phase response at cross−over frequency. A feedback loop analysis making use of datasheet parameters Rcomp and Ccomp without taking into account the described distributed capacitances is to be avoided. t delay EN GH Figure 26. EN Low Response Behaviour The low IQ IC feature is active in diode−emulation mode only. With exception of the overtemperature protection function and output voltage monitoring function used to initiate GH pulse bursts for output voltage regulation, non−essential functions are turned−off to minimize quiescent current consumption. Duty Cycle and Maximum Pulse Width Limits Maximum GH duty ratio is defined by toff,MIN, the minimum permissible GH off time. When this maximum duty ratio is reached while VIN < VIN_LOW, one or more GH off cycle pulse will be skipped to permit maintaining output voltage regulation. Although the internal 2 MHz clock frequency remains unchanged, skipping a GH off pulse results in a measured reduction of the operating frequency. For instance, skipping a single GH off pulse results in a 1 MHz measured waveform frequency. www.onsemi.com 21 NCV891930 minimizing the body diode conduction time, while protecting against cross−conduction (shoot−through) of the MOSFETs. A block diagram of the non−overlap and gate drive circuitry used in the chip and related external components are shown in Figure 30. The GL driver is enabled when VSW is less than the non−overlap detection comparator threshold of 0.4 V. The GL driver response time is dependent on the comparator differential voltage that develops below the 0.4 V detection threshold; approximately 25 ns response time may be expected when operating in continuous conduction mode. To maintain output voltage regulation when SYNCI = 0 V (or open) and VINLx < VIN < VINH, GH on−time may be as low as 0 ns during non−pulse skipping mode operation. MOSFET response will depend on its Qg(tot) characteristics. If the SW pin voltage is still greater than 0.4 V 70 ns following the rising edge of the SYNCI pulse, the IC logic will send a GL pulse to force a recharge of the bootstrap capacitor. The GL pulse width will be no greater than the SYNCI pulse width minus 70 ns. The GL pulse width must be of sufficient duration to fully turn−on the low side MOSFET. The time duration required to turn−on the low side MOSFET will be dependent on the MOSFET’s gate charge specification. The GH driver is enabled when GL voltage is less than the non−overlap detection comparator threshold of 2 V. The GH driver response time is dependent on the comparator differential voltage that develops below the 0.4 V detection threshold; response time is approximately 40 ns. The web model contains the necessary information to establish analytical models for ZU(s), ZL(s), Zcomp(s) and A(s). ZL(s) and Zcomp(s) will be different between VSEL output voltage options. Vout ZU(s) VFB ZL(s) Vref − + Vc gm Ro A(s) Co Vctrl Zcomp (s) Figure 29. OTA Feedback and Compensation Block Diagram Bootstrap During startup, the bootstrap capacitor is charged by a sequence of eight 250 ns GL pulses having a 2 μs period before the SSC pin is allowed to ramp up. For additional details, refer to the Soft−Start detailed application information. Drivers The NCV891930 has a gate drivers to switch external N−Channel MOSFETs. This allows the NCV891930 to address high−power, as well as low−power conversion requirements. The gate drivers also include adaptive non−overlap circuitry. The non−overlap circuitry increases efficiency, which minimizes power dissipation, by www.onsemi.com 22 NCV891930 13 SYNCI 12 ROSC 8 VCCEXT VDRV BST 17 19 18 24 LDO BYPASS 5 V LDO S 14 DBIAS 16 V_CS 1 EN 6 NON OVERLAP PWMOUT INTERNAL RAILS SYNCI FB GH VDRV 22 VSW 21 GL 20 PGND 2 CSP 3 CSN 4 VOUT 15 VSEL Current Limit VNCL PWM/ PULSE SKIP BANDGAP VPCL SLOPE COMP TSD OVSD UVLO FAULT SOFTSTART 23 MIN ON TIME Q R OSC V_SO Q CSA ∑ VREF VCOMP + SYNC0 VIN FB − Z 9 SSC RSTB 10 11 GND RSTB Figure 30. Simplified Block Diagram A capacitor is placed from VSW to BST and an internal bootstrap diode is located between VDRV to BST to create a bootstrap supply on the BST pin for the high−side floating gate driver. This ensures that the voltage on BST is about 4.5 V higher than VSW to drive the high−side MOSFET. The boost capacitor supplies the charge used by the gate driver to charge up the input capacitance of the high−side MOSFET, and is typically chosen to be at least a decade larger than its gate capacitance. Since the BST capacitor recharges when the low−side MOSFET is on, pulling VSW down to ground, the NCV891930 has a minimum off−time. This also means that the BST capacitor cannot be arbitrarily large, since VDRV needs to be able to replenish charge during this minimum off−time so the high−side gate driver doesn’t run out of headroom. VDRV must supply charge to both the BST capacitor and the low−side driver, so the VDRV capacitor must be sufficiently larger than the BST capacitor. A 10:1 VDRV/BST capacitor ratio is effective. A 1 mF VDRV capacitor along with a 0.1 mF BST capacitor is recommended. Careful selection and layout of external components is required to realize the full benefit of the onboard drivers. The capacitors between VIN and GND and between BST and VSW must be placed as close as possible to the IC. The current paths for the GH and GL connections must be optimized to minimize PCB parasitic resistance and inductance. www.onsemi.com 23 NCV891930 SYNC Feature Diode−Emulation Mode V_SO is a supply voltage strictly intended for the SYNCO output driver and should never be used to power external circuitry. The V_SO ceramic decoupling capacitor a minimum of 5 V voltage rating. Ground this pin if not used. An external pulldown resistor is recommended at the SYNCI pin if the function is unused. The SYNCO pulse may be used to synchronize other NCV891930 ICs. If a part does not have its switching frequency controlled by the SYNCI input, the part will operate at the oscillator frequency. A rising edge of the SYNCI pulse causes an NCV891930 to send a GH pulse. If another rising edge does not arrive at the SYNCI pin, the NCV891930 oscillator will take control after the master reassertion time delay which may last up to 3 clock cycles if SYNCI is stopped at logic−low level, up to 4 cycles if SYNCI is stopped at logic−high level. During the master reassertion time, GH will be off and GL will be active−high (i.e. switch node tied to ground). As a result, SYNCI operating mode change is not advised. After soft−start event, SYNCO becomes active when SSC voltage > 1.075 V. VHSYNCI requires about 2 V headroom from VIN to for its rated amplitude. Amplitude will be reduced when VIN is below approximately 5 V. During pulse−skip mode, the oscillator enters sleep mode for low IQ operation power management and SYNCO is inactive. SYNCO functionality resumes when the IC exits pulse−skip mode. When active, SYNC0 is in phase with SYNCI (Figure 31). Rise/fall edge waveforms have a typical 10 ns delay relative to corresponding SYNCI waveform edges. SYNCO will be a fixed frequency 2 MHz signal under normal voltage when part is in current limit and VOUT drops by 7.5% (KUVFAL). The VOUT pin sinks 0 mA under typical conditions when the SYNCI pin is logic−low. The VOUT pin sinks 1 mA when any of the following conditions are present: • SYNCI = logic−high • SYNCI is driven by an external clock • VIN < VIN_low threshold • VIN > frequency foldback threshold voltage Diode−emulation mode is active when SYNCI is either open or grounded. A comparator in the current sense block detects the CSP−CSN voltage transition from a positive voltage (positive inductor current) to 0 V (0 A inductor current). When 0 A is detected, the bottom GL signal turns off the low side MOSFET to prevent negative inductor current. Pulse−Skip Mode Pulse−skipping is used at near discontinuous conduction mode operation as a method to improve low current operating efficiency. Pulse−skip PWM regulation is used to mimic discontinuous conduction mode (DCM) behaviour (Figure 32). The architecture does not use current sensing for pulse−skip detection. The current sense amplifier response time and its input voltage hysteretic characteristics would have resulted in potentially objectionable output voltage ripple. Instead, the internal voltage feedback OTA compensation output voltage (VCOMP) is used to monitor near−DCM operating condition. • When VCOMP reaches a predetermined lower voltage threshold, the IC control logic enters pulsed−skip mode to maintain regulation. Some output voltage ripple associated with the pulse skipping is to be expected • Low−IQ operating mode is entered during pulse−skipping event, permitting higher efficiency operation under low output power operation. The duration is dependent on operating conditions. When the controller exits pulse−skip mode, normal PWM regulation is preceded by up to three 500 kHz pulses (2 MHz/4) as internal logic comes out of low−IQ mode • As the OTA VCOMP is used for feedback control, the VCOMP will not remain constant, increasing to resume PWM activity Ch 1: Power supply output voltage (50 mV/div) Ch 2: Power supply input voltage (between input EMI filter and buck converter, 20 mV/div) Ch 3: Output inductor current (1 A/div) Ch 4: IC gate high (GH) (10 V/div) Ch 1: SYNCI (2 V/div) Ch 2: SYNCO (5 V/div) Figure 32. IC Pulse−Skip PWM Behaviour, Borderline Pulse−Skip Region Ch 3: GH (10 V/div) Ch 4: GL (5 V/div) Figure 31. SYNCO Behaviour www.onsemi.com 24 NCV891930 peak inductor current occurs after this propagation delay, duty ratio will decrease. The thermal shutdown protection circuitry is activated at TJ ≈ 85°C and remains active during pulse−skipping, consuming additional quiescent current. Oscillator ROSC resistance value will have no influence on fSW below 2 MHz. ROSC and fROSC may be calculated for a frequency range of 2 MHz (46 kW) to 2.5 MHz (9.01 kW) with the following expression. Feedback Loop Measurement The compensation network and voltage feedback OTA are internal to the IC. Monitoring points permitting measurements of the modulator control−to−output response and the OTA compensation network are not accessible. The open−loop−response in closed−loop−form may be measured by injecting a signal between the power supply output and IC−VOUT. The signal injection path must not share a power path; traces to IC−VCCEXT and IC−CSN must kept outside the signal injection path. When operating in diode−emulation mode, the OTA feedback loop is disabled when pulse skipping occurs and a hysteretic type mode control is activated. It may be found in literature that feedback loop measurements from small signal injection with hysteretic control yields meaningless information. R OSC + a⋅(f ROSC * b) c kW (eq. 3) Where a = 5.5689 b = 1.8638 c = −1.0380 fROSC expressed in MHz ȡ ȧ Ȣ f ROSC + 2 @ A ) B 1 ) ǒROSC C ȣMHz ȧ ǓȤ D (eq. 4) Where A = 0.93976 B = 3.6294 C = 0.93511 D = 1.04638 ROSC expressed in kW When operating under frequency foldback conditions, the fROSC frequency will be 1 MHz. Current Limiting and Overcurrent Protection Current limit activation propagation delay between the sense resistor reaching the threshold and the GH gate turning off is typically about 39 ns delay. Voltage regulation continues despite slight increase in peak inductor current as a consequence of this current limit propagation delay. If the Figure 33. fROSC vs ROSC www.onsemi.com 25 NCV891930 Spread Spectrum radiated emissions with some spread spectrum techniques. Spread spectrum is a method used to reduce the peak electromagnetic emissions of a switching regulator. In SMPS devices, switching translates to higher efficiency. As a consequence, the switching also leads to a higher EMI profile. We can greatly reduce some of the peak Time Domain Frequency Domain Unmodulated V t fc 3fc 5fc 7fc 9fc fc 3fc 5fc 7fc 9fc Modulated V t Figure 34. Spread Spectrum Comparison The NCV891930 has spread spectrum functionality for reduced peak radiated emissions. This IC uses a pseudo−random generator to set the oscillator frequency to one of 8 discrete frequency bins. Each digital bin represents a shift in frequency by 40 kHz over the range 2.0 MHz to 2.28 MHz. Over time, each bin is used an equal number of times to ensure an even spread of the spectrum. This reduces the peak energy at the fundamental 2 MHz frequency, and spreads it into a wider band. The period of each cycle will change inversely to the switching frequency but the duty cycle, however, will remain constant. Thermal Shutdown A thermal shutdown circuit inhibits switching and resets the soft−start circuit if internal temperature exceeds a safe level indicated by the thermal shutdown activation temperature (TSD). Switching is automatically restored when temperature returns to a safe level based on the thermal shutdown hysteresis (TSD,HYS). Table 5. PSEUDO−RANDOM FREQUENCY BINS 14% Pseudo Random Bin # Switching Frequency 0 2.00 MHz 1 2.04 MHz 2 2.08 MHz 3 2.12 MHz 4 2.16 MHz 5 2.20 MHz 6 2.24 MHz 7 2.28 MHz Efficiency During the brief time duration when both high−side and low−side transistors are turned−off, free−wheeling current flows through the low−side transistor’s intrinsic body diode. An optional Schottky diode across the low−side transistor may be used for an incremental efficiency improvement. Efficiency curves for NCV891930 5 V demo board (VCCEXT = VOUT) are shown in Figure 35. www.onsemi.com 26 NCV891930 VIN=6V VIN=16V VIN=8V VIN=18V VIN=10V VIN=20V VIN=12V VIN=22V VIN=14V VIN=34V 100 90 EFF (%) 80 70 60 50 40 0 1000 2000 3000 4000 5000 6000 Output Current (mA) Figure 35. Efficiency vs Load Current (5 V Demo Board, SYNCI = 0 V) Exposed Pad recommended to connect these two pins directly to the EPAD with a PCB trace. Recommended layout information may be found on the web accessible demo board information. The EPAD must be electrically connected to both the analog and the power electrical ground GND and PGND pins on the PCB for proper, noise−free operation. It is www.onsemi.com 27 NCV891930 APPLICATIONS INFORMATION Design Methodology case, the frequency can be programmed to a lower value with ROSC and then a higher−frequency signal can be applied to the SYNC pin to increase the frequency dynamically to avoid given frequencies. A spread spectrum signal could also be used for the SYNC input, as long as the lowest frequency in the range is above the programmed frequency set by ROSC. Additionally, the highest SYNC frequency must not exceed maximum switching frequency limits. There are two limits on the maximum allowable switching frequency: minimum off−time and minimum on−time. These set two different maximum switching frequencies, as follows: Choosing external components encompasses the following design process: 1. Operational parameter definition 2. Switching frequency selection (ROSC) 3. Output inductor selection 4. Current sense resistor selection 5. Output capacitor selection 6. Input capacitor selection 7. Thermal considerations (1) Operational Parameter Definition Before proceeding with the rest of the design, certain operational parameters must be defined. These are application dependent and include the following: VIN: input voltage, range from minimum to maximum with a typical value [V] VOUT: output voltage [V] IOUT: output current, range from minimum to maximum with initial start−up value [A] ICL: desired typical current limit [A] A number of basic calculations must be performed up−front to use in the design process, as follows: V OUT D MIN + D+ V IN(MAX) V OUT V IN(TYP) D MAX + V OUT V IN(MIN) f S(MAX)1 + f S(MAX)2 + 1 * D MAX T MinOff D MIN T MinOn (eq. 8) (eq. 9) where: fS(MAX)1: maximum switching frequency due to minimum off−time [Hz] TMinOff: minimum off−time [s] fS(MAX)2: maximum switching frequency due to minimum on−time [Hz] TMinOn: minimum on−time [s] Alternatively, the minimum and maximum operational input voltage can be calculated as follows: (eq. 5) (eq. 6) V IN(MIN) + (eq. 7) V IN(MAX) + where: DMIN: minimum duty cycle (ideal) [%] VIN(MAX): maximum input voltage [V] D: typical duty cycle (ideal) [%] VIN(TYP): typical input voltage [V] DMAX: maximum duty cycle (ideal) [%] VIN(MAX): minimum input voltage [V] These are ideal duty cycle expressions; actual duty cycles will be marginally higher than these values. Actual duty cycles are dependent on load due to voltage drops in the MOSFETs, inductor and current sense resistor. V OUT 1 * T MINOff⋅f s V OUT T MINOn⋅f s (eq. 10) (eq. 11) where: fS: switching frequency [Hz] The switching frequency is programmed by selecting the resistor connected between the ROSC pin and ground. The grounded side of this resistor should be directly connected to the GND pin. Avoid running any noisy signals beneath the resistor, as injected noise could cause frequency jitter. The graph in Figure 33 shows the required resistance to program the frequency. (3) Output Inductor Selection Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the power supply, a minimum inductor value is particularly important in space− constrained applications. From an electrical perspective, an inductor is chosen for a set amount of ripple current and to assure adequate transient response. Larger inductor values limit the switcher’s ability to slew current through the output inductor in response to output (2) Switching Frequency Selection (ROSC) Selecting the switching frequency is a trade−off between component size and power losses. Operation at higher switching frequencies allows the use of smaller inductor and capacitor values to achieve the same inductor current ripple and output voltage ripple. However, increasing the frequency increases the switching losses of the MOSFETs, leading to decreased efficiency, especially noticeable at light loads. Typically, the switching frequency is selected to avoid interfering with signals of known frequencies. Often, in this www.onsemi.com 28 NCV891930 expression to 0 W if there is no filter) IL(PK): peak inductor current at rated output current [A] K: design margin to account for inductor variation as well as extra current required to support load transient response. A value of ~120% is commonly used [%]. Alternative current measurement methods such as lossless inductor current sensing may be feasible but beyond the scope of this document. load transients, impacting incremental dynamic response. While the inductor is slewing current during this time, output capacitors must supply the load current. Therefore, decreasing the inductance allows for less output capacitance to hold the output voltage up during a load transient. A ripple current dIL equaling 20−40% of the output rated current is a typical objective when selecting an inductor value for a duty ratio D normally selected at the nominal input operating voltage. The inductor value may be calculated using the following expression: L+ V OUT⋅(1 * D) dI L⋅f s (5) Output Capacitor Selection When used in conjuncture with ceramic capacitors, aluminum polymer/hybrid bulk capacitors are recommended instead of aluminum electrolytic capacitors due to their low −40°C/25°C ESR ratio. Use of EMI bulk capacitors having a high −40°C/25°C ESR ratio may result in an ineffective output filter along with potential stability issues under cold temperature operating conditions. The output capacitor is a basic component for the fast response of the power supply. During the first few microseconds following a load step, it supplies the incremental load current. The controller immediately recognizes the load step and increases the duty cycle, but the current slew rate is limited by the inductor. During a load release, the output voltage will overshoot. The capacitance will decrease this undesirable response, decreasing the amount of voltage overshoot. The worst case is when initial current is at the current limit and the initial voltage is at the output voltage set point, calculating. The overshoot is: (eq. 12) Inductor saturation current is specified by inductor manufacturers as the current at which the inductance value has dropped a certain percentage from the nominal value, typically 10−30%. It is recommended to choose an inductor with saturation current sufficiently higher than the peak output current, such that the inductance is very close to the nominal value at the peak output current. This introduces a safety factor and allows for more optimized compensation. Inductor efficiency is another consideration when selecting an output inductor. Inductor losses include DC and AC winding losses as well as core losses. Core losses are proportional to the amplitude of the ripple current and operating frequency. AC winding losses are based on the AC resistance of the winding and the RMS ripple current through the inductor, which is much lower than the DC current. AC winding losses are due to skin and proximity effects and are typically much less than the DC losses, but increase with frequency. The DC winding losses in the inductor can be calculated with the following equation: P L(DC) + I OUT 2⋅R DC dV OS(MAX) + (eq. 13) C min + Current sensing for peak current mode control relies on the amplitude of the inductor current. The current is translated into a voltage via a current sense resistor placed in series with the output inductor located between the output inductor and capacitors. The resulting voltage is then measured differentially by a current sense amplifier, generating a single−ended output to use as a control signal. If a current sense p−filter is implemented as in Figure 24, the following expression may be used to determine the current sense resistor value. I ⋅K 2)V OUT 2*V OUT (eq. 15) L⋅I CL 2 dV OS(MAX)⋅ǒ2⋅V OUT ) dV OS(MAX)Ǔ (eq. 16) where: CMIN: minimum amount of capacitance to minimize voltage overshoot to dVOS(MAX) [F] dVOS(MAX): maximum allowed voltage overshoot during a load release to 0 A [V] A maximum amount of capacitance can be found based on the output inductor overshoot current and current limit. To calculate the output inductor startup overshoot current, the following approximation may be used (inductor ripple current not considered): (4) Current Sense Resistor Selection V PCL,N ) R SF2⋅I CSN CL Accordingly, a minimum amount of capacitance can be chosen for a maximum allowed output voltage overshoot: where: PL(DC) : DC winding losses in the output inductor RDC: DC resistance of the output inductor (DCR) Ri + ǸCL ⋅I I L(OS) + C OUT⋅V OUT t ss ) I OUT(i) (eq. 17) where: IL(OS): Output inductor overshoot current during startup [A] IOUT(i): Output current during startup [A] (eq. 14) L(PK) Where VPCL,N: positive current limit threshold voltage [V] RSF2: p−filter CSN−VOUT resistor [W] (set value in www.onsemi.com 29 NCV891930 During soft−start, the inductor current must provide current to the load as well as current to charge the output capacitor. The current limit defines the maximum current which the inductor is allowed to conduct. Setting the inrush current to the current limit places a limit on the maximum capacitor value (inductor ripple current not considered) as follows: C MAX + ǒI CL * IOUTǓ⋅tss where: PCIN = power loss from the input capacitors RESR(CIN) = effective series resistance of the input capacitance Due to large current transients through the input capacitors, electrolytic, polymer or ceramics should be used. Aluminum electrolytic specifications often require closer scrutiny due to poor ESR cold temperature characteristics. As a result of the large ripple current, it is common to place ceramic capacitors in parallel with the bulk electrolytic/polymer input capacitors to reduce switching voltage ripple. A value of 0.01 μF to 0.1 μF placed near the MOSFETs is also recommended. Output impedance magnitude of the EMI filter ZoutFILTER(f) must be much smaller than input impedance magnitude of the filtered converter ZinSMPS(f). (eq. 18) V OUT where: CMAX: maximum output capacitance [F] Capacitors should also be chosen to provide acceptable output voltage ripple with a DC load, in addition to limiting voltage overshoot during a dynamic response. Key specifications are equivalent series resistance (ESR) and equivalent series inductance (ESL). The output capacitors must have very low ESL for best transient response. The PCB traces will add to the ESL, but by positioning the output capacitors close to the load, this effect can be minimized and ESL neglected when determining output voltage ripple. ŤZoutFILTER(f)Ť