NDS8934

March 1996 NDS8934 Dual P-Channel Enhancement Mode Field Effect Transistor General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -3.8A, -20V. RDS(ON) = 0.07Ω @ VGS = -4.5V RDS(ON) = 0.1Ω @ VGS = -2.7V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. _________________________________________________________________________________ Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous (Note 1a) 6 3 7 2 8 1 NDS8934 Units -20 V -8 V -3.8 A -15 Power Dissipation for Dual Operation Power Dissipation for Single Operation TJ,TSTG 4 T A = 25°C unless otherwise noted - Pulsed PD 5 2 (Note 1a) (Note 1b) 1 (Note 1c) 0.9 Operating and Storage Temperature Range W 1.6 -55 to 150 °C (Note 1a) 78 °C/W (Note 1) 40 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case © 1997 Fairchild Semiconductor Corporation NDS8934.SAM Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -20 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA V IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 µA VDS = -10 V, VGS = 0 V, TJ = 70°C -5 µA IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA -1 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA RDS(ON) Static Drain-Source On-Resistance VGS = -4.5 V, ID = -3.8 A -0.5 TJ = 125°C -0.3 TJ = 125°C VGS = -2.7 V, ID = -3.2 A ID(on) gFS On-State Drain Current Forward Transconductance VGS = -4.5 V, VDS = -5 V -15 VGS = -2.7 V, VDS = -5 V -5 -0.7 -0.5 -0.8 0.06 0.07 0.085 0.14 0.082 0.1 Ω A VDS = 10 V, ID = -3.8 A 9 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 1120 pF 470 pF 145 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -5 V, ID = -1 A, VGEN = -4.5 V, RGEN = 6 Ω VDS = -10 V, ID = -3.8 A, VGS = -4.5 V 13 20 ns 53 70 ns 60 80 ns 33 40 ns 19 30 nC 2.4 nC 5.5 nC NDS8934.SAM Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -1.3 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A -0.75 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J −TA R θJ A(t ) = T J −TA R θJ C+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.. NDS8934.SAM Typical Electrical Characteristics 2 -20 = -4.5V -3.5 -3.0 -16 -2.7 R DS(on), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) GS -2.5 -12 -8 -2.0 -4 DRAIN-SOURCE ON-RESISTANCE V 1.8 VGS = -2.5V 1.6 -2.7 -3.0 1.4 -3.5 1.2 -4.0 -4.5 -5.0 1 -1.5 0 0.8 0 -1 -2 -3 V DS , DRAIN-SOURCE VOLTAGE (V) -4 0 -4 -8 I Figure 1. On-Region Characteristics. D -12 -16 -20 , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1.6 2 R DS(on), NORMALIZED V GS = -4.5V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE V G S = -4.5V I D = -3.8A 1.4 25°C 1 -55°C 0.5 150 0 -4 I Figure 3. On-Resistance Variation with Temperature. D -8 -12 , DRAIN CURRENT (A) -16 -20 Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = -10V T = -55°C J 25°C 125°C V th , NORMALIZED -16 -12 -8 -4 0 0 -0.5 -1 -1.5 -2 -2.5 -3 VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -3.5 -4 GATE-SOURCE THRESHOLD VOLTAGE -20 I D, DRAIN CURRENT (A) T J = 125°C 1.5 VDS = V GS 1.1 I D = -250µA 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS8934.SAM Typical Electrical Characteristics 20 10 I D = -250µA DRAIN-SOURCE BREAKDOWN VOLTAGE VGS = 0V -I , REVERSE DRAIN CURRENT (A) 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 2 1 T = 125°C J 0.1 -25 0 T J -55°C 0.01 0.001 25 50 75 100 , JUNCTION TEMPERATURE (°C) 125 150 0.0001 0 Figure 7. Breakdown Voltage Variation with Temperature. 0.2 0.4 0.6 0.8 1 1.2 1.4 -VSD , BODY DIODE FORWARD VOLTAGE (V) 1.6 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 5 2000 1500 I D = -3.8A -V GS , GATE-SOURCE VOLTAGE (V) C iss 1000 800 CAPACITANCE (pF) 25°C S BV DSS , NORMALIZED 1.1 1.08 C oss 600 400 C rss f = 1 MHz 200 V GS = 0 V 100 0.1 0.2 0.5 1 2 3 5 10 20 -V DS , DRAIN TO SOURCE VOLTAGE (V) V DS = -5.0V -10V -15V 4 3 2 1 0 0 5 10 15 Q g , GATE CHARGE (nC) 20 25 Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. VDS = -10V TJ = -55°C 15 25°C 125°C 10 5 g FS , TRANSCONDUCTANCE (SIEMENS) 20 0 0 -4 -8 ID -12 -16 -20 , DRAIN CURRENT (A) Figure 11. Transconductance Variation with Drain Current and Temperature. NDS8934.SAM Typical Thermal Characteristics 4.5 -I D , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 2.5 Total Power for Dual Operation 2 1a Power for Single Operation 1.5 1b 1 1c 4.5"x5" FR-4 Board TA = 25 o C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 12. SO-8 Dual Package Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 4 1a 3.5 1b 3 1c 4.5"x5" FR-4 Board 2.5 TA = 2 5 o C Still Air VG S = -4.5V 2 0 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.5 Figure 13. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. 30 10 10 RD -I D , DRAIN CURRENT (A) 3 S(O LIM N) IT 10 10 1 1m 0m 0u s s s ms 1s 10 0.3 V 0.1 GS s DC = -4.5V SINGLE PULSE R 0.03 θJ A = See Note 1c T A = 25°C 0.01 0.1 0.2 0.5 1 2 5 10 20 30 - V DS , DRAIN-SOURCE VOLTAGE (V) Figure 14. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0 .5 D = 0.5 0 .2 0.2 0 .1 0 .0 5 0 .0 2 0 .0 1 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.1 0.05 P(pk) 0.02 0.01 t1 Single Pulse 0 .0 0 5 t2 TJ - T = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 A 0 .0 0 2 0 .0 0 1 0 .0001 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8934.SAM TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4