NDS8958

July 1996 NDS8958 Dual N & P-Channel Enhancement Mode Field Effect Transistor General Description Features These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. N-Channel 5.3A, 30V, RDS(ON)=0.035Ω @ VGS=10V. P-Channel -4.0A, -30V, RDS(ON)=0.065Ω @ VGS=-10V. High density cell design or extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual (N & P-Channel) MOSFET in surface mount package. ________________________________________________________________________________ Absolute Maximum Ratings 5 4 6 3 7 2 8 1 T A= 25°C unless otherwise noted Symbol Parameter N-Channel P-Channel Units VDSS Drain-Source Voltage 30 -30 V VGSS Gate-Source Voltage 20 -20 V ID Drain Current - Continuous 5.3 -4 A 20 -15 (Note 1a) - Pulsed PD Power Dissipation for Dual Operation Power Dissipation for Single Operation TJ,TSTG 2 (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W NDS8958 Rev. C Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Type Min N-Ch 30 -30 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA P-Ch IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V N-Ch V V µA 10 µA P-Ch -1 µA TJ = 55°C VDS = -24 V, VGS = 0 V 1 -10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V All -100 nA V TJ = 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage N-Ch VDS = VGS, ID = 250 µA TJ = 125°C P-Ch VDS = VGS, ID = -250 µA TJ = 125°C RDS(ON) Static Drain-Source On-Resistance 1 1.6 2.8 0.7 1.2 2.2 -1 -1.6 -2.8 -0.7 -1.2 -2.2 0.033 0.035 0.046 0.063 N-Ch VGS = 10 V, ID = 5.3 A TJ = 125°C VGS = 4.5 V, ID = 4.4 A VGS = -10 V, ID = -4.0 A P-Ch TJ = 125°C VGS = -4.5 V, ID = -3.3 A ID(on) On-State Drain Current VGS = 10 V, VDS = 5 V gFS Forward Transconductance 0.046 0.05 0.052 0.065 0.075 0.13 0.085 0.1 N-Ch 20 VGS = -10 V, VDS = -5 V P-Ch -15 VDS = 10 V, ID = 5.3 A N-Ch 10.5 VDS = -10 V, ID = -4.0 A P-Ch 7 N-Channel VDS = 15 V, VGS = 0 V, f = 1.0 MHz N-Ch 720 P-Ch 690 N-Ch 370 Ω A S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance P-Channel VDS = -15 V, VGS = 0 V, f = 1.0 MHz P-Ch 430 N-Ch 250 P-Ch 160 pF pF pF NDS8958 Rev. C Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Type N-Channel VDD = 10 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω Min Typ Max Units N-Ch 12 20 ns P-Ch 9 20 N-Ch 13 30 SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time Turn - On Rise Time tr tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg P-Channel VDD = -10 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω Total Gate Charge Qgs Qgd Gate-Source Charge Gate-Drain Charge P-Ch 20 25 N-Ch 29 50 50 P-Ch 40 N-Ch 10 20 P-Ch 19 40 N-Channel VDS = 10 V, ID = 5.3 A, VGS = 10 V N-Ch 19 30 P-Ch 21 30 N-Ch 2.2 P-Channel VDS = -10 V, ID = -4.0 A, VGS = -10 V P-Ch 3.1 N-Ch 5.5 P-Ch 5.1 ns ns ns nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD trr N-Ch 1.3 P-Ch -1.3 Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) N-Ch 0.9 1.2 VGS = 0 V, IS = -1.3 A (Note 2) P-Ch -0.85 -1.2 Reverse Recovery Time VGS = 0 V, IF = 1.3 A, dIF/dt = 100 A/µs N-Ch 100 VGS = 0 V, IF = -1.3 A, dIF/dt = 100 A/µs P-Ch 100 A V ns Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD(t ) = T J− TA R θJA(t ) = T J −TA R θJC+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8958 Rev. C Typical Electrical Characteristics: N-Channel VGS =10V 20 3 6.0 5.0 VGS = 3.0V 4.5 R DS(ON), NORMALIZED 4.0 15 3.5 10 3.0 5 0 0 0.5 1 1.5 2 V DS , DRAIN-SOURCE VOLTAGE (V) 2.5 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 25 2.5 Figure 1. N-Channel On-Region Characteristic. 4.5 1.5 6.0 0 5 10 15 I D , DRAIN CURRENT (A) 20 25 2 1.4 VGS = 10V R DS(ON), NORMALIZED VG S =10V 1.2 1 0.8 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 10 Figure 2. N-Channel On-Resistance Variation with Gate Voltage and Drain Current. I D = 5.3A 0.6 -50 1.75 TJ = 125°C 1.5 1.25 25°C 1 -55°C 0.75 0.5 150 Figure 3. N-Channel On-Resistance Variation with Temperature. 0 5 10 15 I D , DRAIN CURRENT (A) 20 25 Figure 4. N-Channel On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = 10V TJ = -55°C 25°C 125°C V th, NORMALIZED 20 15 10 5 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 6 Figure 5. N-Channel Transfer Characteristic. GATE-SOURCE THRESHOLD VOLTAGE 25 ID , DRAIN CURRENT (A) 5.0 1 1.6 0 4.0 2 0.5 3 3.5 V DS = VGS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 125 150 TJ , JUNCTION TEMPERATURE (°C) Figure 6. N-Channel Gate Threshold Variation with Temperature. NDS8958 Rev. C Typical Electrical Characteristics: N-Channel (continued) 25 I D = 250µA 1.05 1 0.95 0.9 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 1 TJ = 125°C 25°C -55°C 0.1 0.01 0.001 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD , BODY DIODE FORWARD VOLTAGE (V) Figure 8. N-Channel Body Diode Forward Voltage Variation with Current and Temperature. Figure 7. N-Channel Breakdown Voltage Variation with Temperature. 2000 10 I D = 5.3A V GS , GATE-SOURCE VOLTAGE (V) 1500 1000 C iss C oss 500 200 f = 1 MHz C rss V GS = 0V 100 0.1 0.2 0.5 V DS 1 2 5 10 20 30 , DRAIN TO SOURCE VOLTAGE (V) Figure 9. N-Channel Capacitance Characteristics. V DS = 5V 10V 8 20V 6 4 2 0 0 5 10 15 Q g , GATE CHARGE (nC) 20 25 Figure 10. N-Channel Gate Charge Characteristics. 20 g FS, TRANSCONDUCTANCE (SIEMENS) CAPACITANCE (pF) VGS =0V 10 I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 V DS = 10V TJ = -55°C 16 25°C 12 125°C 8 4 0 0 5 10 15 20 25 I D , DRAIN CURRENT (A) Figure 11. N-Channel Transconductance Variation with Drain Current and Temperature. NDS8958 Rev. C Typical Electrical Characteristics: P-Channel (continued) -20 -15 -5.0 -4.5 R DS(on), NORMALIZED ID , DRAIN-SOURCE CURRENT (A) -6.0 -4.0 -10 -3.5 -5 -3.0 0 0 -1 -2 -3 V DS , DRAIN-SOURCE VOLTAGE (V) DRAIN-SOURCE ON-RESISTANCE 3 VGS = -10V VGS = -3.5V 2.5 Figure 12. P-Channel On-Region Characteristics. -4.5 2 -5.0 1.5 -6.0 -10 1 0.5 -4 - 4.0 0 R DS(on), NORMALIZED 1.2 1 0.8 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED -20 V GS = -10V V GS = -10V 1.4 0.6 -50 1.5 25°C 1 -55°C 0.5 150 TJ = 125°C 0 -4 I J Figure 14. P-Channel On-Resistance Variation with Temperature. D -8 -12 , DRAIN CURRENT (A) -16 -20 Figure 15. P-Channel On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = -10V T J = -55°C 125°C -15 V th , NORMALIZED 25°C -10 -5 -1 -2 -3 -4 -5 VGS , GATE TO SOURCE VOLTAGE (V) -6 Figure 16. P-Channel Transfer Characteristics. GATE-SOURCE THRESHOLD VOLTAGE -20 I D , DRAIN CURRENT (A) -16 2 I D = -4.0A 0 -8 -12 I D , DRAIN CURRENT (A) Figure 13. P-Channel On-Resistance Variation with Gate Voltage and Drain Current. 1.6 DRAIN-SOURCE ON-RESISTANCE -4 V DS = VGS 1.1 I D = -250µA 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 17. P-Channel Gate Threshold Variation with Temperature. NDS8958 Rev. C Typical Electrical Characteristics: P-Channel (continued) 20 5 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 -25 V GS = 0V 10 I D = -250µA -I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 1.08 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 18. P-Channel Breakdown Voltage Variation with Temperature. TJ = 125°C 1 -55°C 0.1 0.01 0.001 0 0.4 0.8 1.2 1.6 -VSD , BODY DIODE FORWARD VOLTAGE (V) 2 Figure 19. P-Channel Body Diode Forward Voltage Variation with Current and Temperature. 10 2000 , GATE-SOURCE VOLTAGE (V) ID = -4.0A 1000 C iss C oss 500 300 f = 1 MHz C rss VDS = -5V 8 -20V -10V 6 4 2 -V V GS = 0 V GS 200 100 0.1 0.2 0.5 1 2 5 10 30 -V DS , DRAIN TO SOURCE VOLTAGE (V) Figure 20. P-Channel Capacitance Characteristics. 0 0 5 10 15 Q g , GATE CHARGE (nC) 20 25 Figure 21. P-Channel Gate Charge Characteristic. 12 g FS, TRANSCONDUCTANCE (SIEMENS) CAPACITANCE (pF) 25°C VDS = -10V TJ = -55°C 9 25°C 125°C 6 3 0 0 -4 -8 -12 I D , DRAIN CURRENT (A) -16 -20 Figure 22. P-Channel Transconductance Variation with Drain Current and Temperature. NDS8958 Rev. C Typical Thermal Characteristics: N & P-Channel 6 I D , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 2.5 Total Power for Dual Operation 2 1a Power for Single Operation 1.5 1b 1 1c 4.5"x5" FR-4 Board TA = 25 o C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 1a 5 1b 4 1c 3 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 2 VG S = 1 0 V 0 Figure 23. SO-8 Dual Package Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in 2 ) Figure 24. N-Ch Maximum Steady-State Drain Current versus Copper Mounting Pad Area. 50 4.5 10 4 3.5 1b 1c 4.5"x5" FR-4 Board 2.5 5 R ( DS ) ON 1 V GS = 10V VG S = - 1 0 V 50 0.5 100 10 RD 5 S(O N) I LIM s s SINGLE PULSE 0.1 0.05 DC s s ms 0m 1s 10 0u R θJ A = See Note 1c T A = 25°C 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in 2 ) 20 1m 0.5 TA = 2 5 C 0 IT 10 Still Air 2 LIM 10 o 0.01 0.1 0.2 0.5 1 2 5 10 V DS , DRAIN-SOURCE VOLTAGE (V) 30 50 Figure 26. N-Channel Maximum Safe Operating Area. Figure 25. P-Ch Maximum Steady- State Drain Current versus Copper Mounting Pad Area. -ID , DRAIN CURRENT (A) 10 1a ID , DRAIN CURRENT (A) -I D , STEADY-STATE DRAIN CURRENT (A) 20 3 0.5 us T 1m 10 10 1 s ms 0m s 1s 0.5 10s VGS = -10V DC SINGLE PULSE 0.1 R 0.05 θJ A = See Note 1c T A = 25°C 0.01 0.1 0.2 0.5 1 2 5 10 30 50 - VDS , DRAIN-SOURCE CURRENT (V) Figure 27. P-Channel Maximum Safe Operating Area. NDS8958 Rev. C Typical Thermal Characteristics: N & P-Channel r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0 .5 D = 0.5 0 .2 0.2 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.1 0 .1 0.05 0 .0 5 P(pk) 0.02 0 .0 2 0.01 0 .0 1 t1 Single Pulse 0 .0 0 5 t2 TJ - T = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 A 0 .0 0 2 0 .0 0 1 0 .0001 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 28. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. ton VDD t d(on) R GEN tf 90% 90% V OUT D VGS tr RL V IN to f f t d(off) VO U T 10% 10% DUT G 90% V IN S 50% 50% 10% PULSE WIDTH Figure 29. N or P-Channel Switching Test Circuit. Figure 30. N or P-Channel Switching Waveforms. NDS8958 Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. D