NDS9953A

February 1996 NDS9953A Dual P-Channel Enhancement Mode Field Effect Transistor General Description Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -2.9A, -30V. RDS(ON) = 0.13Ω @ VGS = -10V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. ________________________________________________________________________________ Absolute Maximum Ratings 4 6 3 7 2 8 1 T A= 25°C unless otherwise noted Symbol Parameter VDSS VGSS ID Drain Current - Continuous PD Power Dissipation for Dual Operation NDS9953A Units Drain-Source Voltage -30 V Gate-Source Voltage ± 20 V ± 2.9 A (Note 1a) - Pulsed Power Dissipation for Single Operation ± 10 2 (Note 1a) 1.6 (Note 1b) 1 (Note 1c) TJ,TSTG 5 Operating and Storage Temperature Range W 0.9 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W © 1997 Fairchild Semiconductor Corporation NDS9953A.SAM Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -30 Typ Max Units -2 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V V -25 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V TJ = 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ = 125°C RDS(ON) Static Drain-Source On-Resistance -1 -1.6 -2.8 -0.85 -1.25 -2.5 0.11 0.13 0.15 0.21 VGS = -10 V, ID = -1.0 A TJ = 125°C VGS = -4.5 V, ID = -0.5 A TJ = 125°C ID(on) gFS On-State Drain Current Forward Transconductance VGS = -10 V, VDS = -5 V -10 VGS = -4.5 V, VDS = -5 V -1.5 0.17 0.2 0.24 0.32 Ω A VDS = -15 V, ID = -2.9 A 4 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 350 pF 260 pF 100 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -10 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω VDS = -10 V, ID = -2.9 A, VGS = -10 V 9 40 ns 21 40 ns 21 90 ns 8 50 ns 10 25 nC 1.6 nC 3.4 nC NDS9953A.SAM Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -1.2 A DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.25 A trr Reverse Recovery Time VGS = 0 V, IF = -1.25 A, dIF/dt = 100 A/µs -0.8 (Note 2) -1.3 V 100 ns Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = TJ −TA R θJ A(t ) = TJ −TA R θJ C+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS9953A.SAM Typical Electrical Characteristics -20 3 -8.0 -7.0 R DS(on) , NORMALIZED -6.0 -15 -5.5 -5.0 -10 -4.5 -4.0 -5 D -3.5 I -3.0 0 0 -1 V DS -2 -3 , DRAIN-SOURCE VOLTAGE (V) -4 DRAIN-SOURCE ON-RESISTANCE , DRAIN-SOURCE CURRENT (A) VGS = -10V R DS(on), NORMALIZED 1 0.8 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE V G S = -10V -5.5 -6.0 1.5 -7.0 -8.0 -10 1 0 -3 -6 -9 I D , DRAIN CURRENT (A) -12 -15 V GS = -10V TJ = 125°C 1.5 25°C 1 -55°C 0.5 150 Figure 3. On-Resistance Variation with Temperature. 0 -3 -6 -9 I D , DRAIN CURRENT (A) -12 -15 Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = -10V TJ = -55°C 25°C 125°C V th , NORMALIZED -8 -6 -4 -2 -1 -2 -3 -4 -5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -6 GATE-SOURCE THRESHOLD VOLTAGE -10 ID , DRAIN CURRENT (A) -5.0 2 I D = -2.9A 1.2 0 -4.5 Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1.6 0.6 -50 -4.0 2 0.5 -5 Figure 1. On-Region Characteristics. 1.4 VGS = -3.5V 2.5 VDS = V GS 1.1 I D = -250µA 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS9953A.SAM Typical Electrical Characteristics (continued) 10 I D = -250µA 5 1.08 -I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 1 0.5 T = 125°C J 25°C -55°C 0.1 0.01 0.001 0.2 Figure 7. Breakdown Voltage Variation with Temperature. 0.4 0.6 0.8 1 1.2 -VSD , BODY DIODE FORWARD VOLTAGE (V) 1.4 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 1000 10 -V GS , GATE-SOURCE VOLTAGE (V) 800 500 C iss CAPACITANCE (pF) V GS = 0V 300 C oss 200 f = 1 MHz 100 C rss V GS = 0V 50 0.1 0.2 0.5 1 2 5 10 -VDS , DRAIN TO SOURCE VOLTAGE (V) 30 I D = -2.9A V DS = -10V -20V 8 -15V 6 4 2 0 0 2 4 6 8 Q g , GATE CHARGE (nC) 10 12 Figure 10. Gate Charge Characteristic. Figure 9. Capacitance Characteristics. 6 TJ = -55°C 25°C 4 125°C 3 2 1 g FS , TRANSCONDUCTANCE (SIEMENS) V DS = -15V 5 0 0 -2 ID -4 -6 , DRAIN CURRENT (A) -8 -10 Figure 11. Transconductance Variation with Drain Current and Temperature. NDS9953A.SAM Typical Thermal Characteristics 5 I D , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 2.5 Total Power for Dual Operation 2 1a Power for Single Operation 1.5 1b 1 1c 4.5"x5" FR-4 Board TA = 25 o C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 30 10 -I D , DRAIN CURRENT (A) 3 RD S(O N) LI 1m T MI 10 10 1 1a 1b 2 1c 4.5"x5" FR-4 Board TA = 2 5 o C Still Air 1 VG S = - 1 0 V 0 0.1 0.2 0.3 0.4 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.5 0u s s ms s 1s 10 s DC 0.3 V GS = -10V 0.1 0m 3 Figure 13. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 12. SO-8 Dual Package Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 10 4 SINGLE PULSE R 0.03 θJ A = See Note 1c T A = 25°C 0.01 0.1 0.2 0.5 1 2 5 10 - V DS , DRAIN-SOURCE VOLTAGE (V) 30 50 Figure 14. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 R θJA (t) = r(t) * R θJA R JA = See Note 1c θ 0.1 0.05 P(pk) 0.02 0.01 t1 Single Pulse 0.005 0.002 0.001 0.0001 t2 TJ - TA = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 0.001 0.01 0.1 1 10 100 300 t1 , TIME (sec) Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS9953A.SAM TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. 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Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. E