NDT453N

September 1996 NDT453N N-Channel Enhancement Mode Field Effect Transistor General Description Features Power SOT N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. 8A, 30V. RDS(ON) = 0.028Ω @ VGS = 10V. RDS(ON) = 0.042Ω @ VGS = 4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ___________________________________________________________________________________________ D G Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous PD Maximum Power Dissipation D D S S T A= 25°C unless otherwise not (Note 1a) - Pulsed TJ,TSTG G NDT453N Units 30 V ±20 V ±8 A ±15 (Note 1a) 3 (Note 1b) 1.3 (Note 1c) 1.1 Operating and Storage Temperature Range W -65 to 150 °C (Note 1a) 42 °C/W (Note 1) 12 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case * Order option J23Z for cropped center drain lead. © 1997 Fairchild Semiconductor Corporation NDT453N Rev. D1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR Gate - Body Leakage, Reverse 30 V 1 µA 10 µA VGS = 20 V, VDS = 0 V 100 nA VGS = -20 V, VDS= 0 V -100 nA 3 V TJ= 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 8.0 A 1 TJ= 125°C 0.7 TJ= 125°C VGS = 4.5 V, ID = 6.7 A TJ= 125°C ID(on) gFS On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V 15 VGS = 4.5 V, VDS = 5 V 10 2 1.5 2.2 0.022 0.028 0.03 0.045 0.035 0.042 0.047 0.075 Ω A VDS = 15 V, ID = 8.0 A 14 S VDS = 15 V, VGS = 0 V, f = 1.0 MHz 890 pF 560 pF 190 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge 4.5 nC Qgd Gate-Drain Charge 9.5 nC VDD = 25 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω VDS = 15 V, ID = 8.0 A, VGS = 10 V 10 15 ns 20 35 ns 40 50 ns 35 50 ns 28 35 nC NDT453N Rev. D1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 2.3 A 0.8 1.3 V 100 ns DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 8.0 A trr Reverse Recovery Time VGS = 0 V, IS = 2 A, dIF/dt = 100A/µs (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = T J−TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 42oC/W when mounted on a 1 in2 pad of 2oz copper. b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper. c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDT453N Rev. D1 Typical Electrical Characteristics 3.5 25 =10V V GS = 3.5V 6.0 5.0 4.5 20 15 R DS(ON), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) GS 4.0 10 3.5 5 DRAIN-SOURCE ON-RESISTANCE V 3 4.0 2.5 4 .5 2 5.0 1.5 6.0 7.0 10 1 3.0 0 0 0.5 1 1.5 2 V DS , DRAIN-SOURCE VOLTAGE (V) 2.5 0.5 3 0 Figure 1. On-Region Characteristics. 25 30 25 30 2 I D = 8A R DS(on), NORMALIZED 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE V GS = 10 V VGS =10V 1.4 1.5 T J = 125°C 25°C 1 -55°C 0.5 150 0 Figure 3. On-Resistance Variation with Temperature. 5 10 15 20 I D , DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.3 20 V DS = 10V TJ = -55°C 125 25 V th, NORMALIZED 15 10 5 0 1 1.5 2 2.5 3 3.5 4 VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4.5 5 GATE-SOURCE THRESHOLD VOLTAGE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 10 15 20 I D , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1.6 ID , DRAIN CURRENT (A) 5 V DS = V GS 1.2 I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 TJ , JUNCTION TEMPERATURE (°C) Figure 6. Gate Threshold Variation with Temperature. NDT453N Rev. D1 Typical Electrical Characteristics (continued) 20 ID = 250µA 10 VGS =0V 5 1.1 I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.15 1.05 1 0.95 0.9 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 1 TJ = 125°C 25°C 0.1 -55°C 0.01 0.001 0.2 150 Figure 7. Breakdown Voltage Variation with Temperature. C iss CAPACITANCE (pF) 1000 C oss 500 f = 1 MHz V GS = 0V C rss VGS , GATE-SOURCE VOLTAGE (V) I D = 8A 1500 1 1.2 VDS = 5V 10V 15V 8 6 4 2 0 0.2 0.5 1 2 5 10 20 30 0 5 10 V DS , DRAIN TO SOURCE VOLTAGE (V) t on t d(on) 25 t d(off) tf 90% 90% V OUT VOUT 10% 10% INVERTED DUT G 30 t off tr RL D R GEN 20 Figure 10. Gate Charge Characteristics. VDD V IN 15 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. VGS 0.8 10 2000 100 0.1 0.6 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 2500 200 0.4 V SD , BODY DIODE FORWARD VOLTAGE (V) 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDT453N Rev. D1 Typical Electrical and Thermal Characteristics 25 3.5 STEADY-STATE POWER DISSIPATION (W) g FS, TRANSCONDUCTANCE (SIEMENS) V DS = 15V TJ = -55°C 20 25°C 15 125°C 10 5 0 0 5 10 15 20 1a 3 2.5 2 1.5 1b 1c 1 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) I D , DRAIN CURRENT (A) Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SOT-223 Maximum Steady- State Power Dissipation versus Copper Mounting Pad Area. 9 30 1a 8 10 R I D , DRAIN CURRENT (A) I D , STEADY-STATE DRAIN CURRENT (A) 1 7 6 1b 5 1c 4.5"x5" FR-4 Board Still Air ON IM )L IT 10 1m 10 3 10 1 10 VGS = 10V DC SINGLE PULSE R 0.1 0m 1s 0.3 TA = 2 5 o C 4 ( DS θJ A 0u s s ms s s = See Note 1c T A = 25°C VG S = 1 0 V 3 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 0.05 0.1 0.2 0.5 1 2 5 10 30 50 V DS , DRAIN-SOURCE VOLTAGE (V) Figure 16. Maximum Safe Operating Area. Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 R JA (t) = r(t) * R JA θ θ R JA = See Note 1 c θ P(pk) 0.01 t1 0.005 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R (t) θJA Duty Cycle, D = t 1 / t 2 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDT453N Rev. D1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. 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