NIS5101

NIS5101 SMART HotPlugt IC/Inrush Limiter/Circuit Breaker The SMART HotPlug Integrated Circuit combines the control function and power FET into a single IC that saves design time and reduces the number of components required for a complete hot swap application. It is designed to allow safe insertion and removal of electronic equipment to −48 V backplanes. This chip features simplicity of use combined with an integrated solution. The SMART HotPlug includes user selectable undervoltage and overvoltage lockout levels. It also has adjustable current limiting that can be reduced from the maximum level with a single resistor. Operation at the maximum current level requires no extra external components. An internal temperature shutdown circuit greatly increases the reliability of this device. Features http://onsemi.com MARKING DIAGRAM 8 1 7 S−PAK EX SUFFIX CASE 553AA NIS5101EX AYWWG • • • • • • • • • • • • • • • Integrated Power Device 100 V Operation Thermal Limit Protection Adjustable Current Limit No External Current Shunt Required Undervoltage and Overvoltage Lockouts 6.5 A Continuous Operation UIS Rated Main/Mirror MOSFET Current Ratio 820:1 Pb−Free Packages are Available VoIP (Voice over Internet Protocol) Servers −48 V Telecom Systems +24 V Wireless Base Station Power Central Office Switching Electronic Circuit Breaker 7 Input + X = 1 for Thermal Latch or 2 for Thermal Auto−retry A = Assembly Location Y = Year WW = Work Week G = Pb−Free Device ORDERING INFORMATION Device NIS5101E1T1 NIS5101E1T1G Package S−PAK Latch Off S−PAK Latch Off (Pb−Free) S−PAK Auto−Retry S−PAK Auto−Retry (Pb−Free) Shipping† 2000 Units/Reel 2000 Units/Reel Typical Applications NIS5101E2T1 NIS5101E2T1G 2000 Units/Reel 2000 Units/Reel Voltage Regulator Thermal Shutdown 4, 8 Drain †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 6 UVLO/ ENABLE Undervoltage Lockout 5 OVLO Overvoltage Shutdown Current Limit 3 Current Limit Input − 1, 2 Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2006 1 November, 2006 − Rev. 21 Publication Order Number: NIS5101/D NIS5101 PIN FUNCTION DESCRIPTION Pin 1, 2 3 4, 8 5 6 7 Symbol Input − Current Limit Drain OVLO UVLO/ENABLE Input + Description Negative input voltage to the device. This is used as the internal reference for the IC. This pin is shorted to the Input − pin for maximum current limit setting. If a reduced current limit level is desired, a series resistor is added between this pin and the Input − pin. Drain of power FET, which is also the switching node for the load. The overvoltage shutdown point is programmed by a resistor from this pin to the Input + supply. A resistor from Input + to the UVLO pin adjusts the voltage at which the device will turn on. An open drain device can be connected to this pin, which will inhibit operation, when in its low impedance state. Positive input voltage to the device. MAXIMUM RATINGS Rating Input Voltage, Operating (Input + to Input −) Transient (1 second) Steady−State Drain Voltage, Operating (Drain to Input −) Transient (1 second) Steady−State Drain Current, Continuous (TA = 25°C, 2.0 in2 Cu, double−sided board, 1 oz.) Operating Temperature Range Non−Operating Temperature Range Lead Temperature, Soldering (10 Seconds) Drain Current, Peak (Internally Limited) Thermal Resistance, Junction−to−Air 0.5 in2 copper 1.0 in2 copper Power Dissipation @ TA = 25°C 0.5 in2 copper 1.0 in2 copper ESD Immunity for Device Handling (All Pins) ESD Immunity Board Level (Note 1) Lightning, Surge (8 x 20 msec) (Note 1) Symbol Vin −0.3 to 110 −0.3 to 100 VDD −0.3 to 110 −0.3 to 100 IDavg Tj Tj TL Ipk RqJA 75 43 Pmax 1.4 2.4 HBM JESD22−A114−B IEC 61000−4−2 (Level 3) IEC 61000−4−5 (Level 3) 2.0 6.0 2.0 48 kV kV kV A W 6.5 −40 to 145 −55 to 175 260 20 A °C °C °C A °C/W V Value Unit V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Applied between Input + and Input − pins only, and using an external 68 V bi−directional TVS device (P6SMB68AT3) connected across these pins. http://onsemi.com 2 NIS5101 ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise noted.) Characteristic POWER FET Charging Time (Turn−On to Rated Max Current) ON Resistance Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) Sense Voltage Tolerance (Vinput = 48 V, RextILIMIT = 20 W) Output Capacitance (VDS = 48 Vdc, VGS = 0 Vdc, f = 10 kHz) THERMAL LIMIT Shutdown Junction Temperature (Note 4) Hysteresis (Note 4) OVER/UNDERVOLTAGE Turn−On Voltage (RextUVLO = R) Hysteresis (RextUVLO = R) Turn−On Voltage (RextUVLO = 270 kW) Hysteresis (RextUVLO = 270 kW) Zener Voltage (UVLO Pin Voltage at Turn−On) OVLO Threshold (Input + Increasing, RextOVLO = R) OVLO Threshold (Input + Increasing, RextOVLO = 300 kW) OVLO Hysteresis (Input + Decreasing, RextOVLO = 300 kW) CURRENT LIMIT Short Circuit Current Limit (RextILIMIT = 20 W) (Note 5) Overload Current Limit (RextILIMIT = 20 W) (Notes 4 and 5) TOTAL DEVICE Bias Current (Operational) (Vinput = 48 V, RUVLO = R) Bias Current (Non−Operational) (Vinput = 30 V, RUVLO = R) Minimum Operating Voltage (RUVLO = 30 kW) 2. 3. 4. 5. IBias IBias Vinmin − − − 1.4 800 18 − − − mA mA V ILIM1 ILIM2 3.5 5.4 4.2 6.0 5.0 6.6 A A Von Vhyst Von Vhyst VZ VOV VOV VOVhyst 41.5 6.3 29 3.5 14.3 100 65 3.0 46 8.0 33 5.0 16 − 74 4.7 50.5 9.7 37 6.5 17.5 − 83 6.4 V V V V V V V V TSD Thyst 125 35 135 40 145 45 °C °C tchg RDSon IDSS VSense − − − − − − 5.0 43 10 3.0 326 − 50 − − − ms mW mA % pF Symbol Min Typ Max Unit Pulse Test: Pulse width 300 ms, duty cycle 2%. Switching characteristics are independent of operating junction temperatures. Verified by design. Please refer to explanation about the device’s current limit operation in short circuit and overload conditions. http://onsemi.com 3 NIS5101 TYPICAL PERFORMANCE CURVES (TA = 25°C unless otherwise noted) 100 45 40 10 ILimit (A) Overload 25°C Overload 120°C Short Circuit −40°C Short Circuit 25°C Short Circuit 120°C UVLO TRIP POINT (V) Overload −40°C 35 30 25 Turn−Off −40°C 20 15 10 Turn−Off 25°C Turn−Off 120°C 100 UVLO_Rext (kW) 1000 Turn−On −40°C Turn−On 25°C Turn−On 120°C 1 0.1 1 10 Rext_ILimit (W) 100 1000 Figure 2. Current Limit Adjustment (For Main/Mirror MOSFET Current Ratio explanation, see page 11) 100 90 OVLO TRIP POINT (V) 80 70 60 50 40 30 20 10 100 OVLO_Rext (kW) 1000 Turn−On 25°C OVLO TRIP POINT (V) Turn−Off 25°C 100 90 80 70 60 50 40 30 20 10 Figure 3. UVLO Adjustment Turn−Off 120°C Turn−On 120°C 100 OVLO_Rext (kW) 1000 Figure 4. OVLO Adjustment, TJ = 255C 100 90 OVLO TRIP POINT (V) 80 70 60 50 40 30 20 10 100 OVLO_Rext (kW) 1000 Turn−On −40°C CASE TEMPERATURE (°C) Turn−Off −40°C 115 105 95 85 75 65 55 45 35 25 1 Figure 5. OVLO Adjustment, TJ = 1205C 0.5 in2 Cu area 1 in2 Cu area 2 in2 Cu area Device Reaching Thermal Shutdown 2 3 4 5 6 7 CONTINUOUS CURRENT (A) Figure 6. OVLO Adjustment, TJ = −405C Figure 7. Continuous Current vs. Case Temperature (Test performed on a double sided copper board, 1 oz) http://onsemi.com 4 NIS5101 TYPICAL APPLICATION CIRCUIT & OPERATION WAVEFORMS (TA = 25°C unless otherwise noted) RUVLO Input + UVLO/EN NIS5101 Drain OVLO Current Limit Input − + DC−DC Converter + + ROVLO Rlimit Figure 8. Typical Application Load Capacitor 470 mF GND Bounce Bus Voltage Load Voltage Load Current 1 A/div −48 V Figure 9. Turn On Waveforms for 470 mF Load Capacitor http://onsemi.com 5 NIS5101 Load Capacitor 4200 mF GND Bus Voltage Load Voltage Load Current 1 A/div −48 V Device Reaching Thermal Shutdown Figure 10. Typical Operation Waveforms of the Auto−Retry Device Load Voltage Load Capacitor 4200 mF Gnu Bus Voltage Load Current 1 A/div −48 V Device Reaching Thermal Shutdown Figure 11. Typical Operation Waveforms of the Latch Off Device http://onsemi.com 6 NIS5101 ADDITIONAL APPLICATION CIRCUITS FOR DIFFERENT FUNCTIONS Input + UVLO/EN NIS5101 Drain OVLO + Current Limit Input − RL + CL Pwr Good NUD3048 Pwr Good NUD3048 Figure 12. Power Good Signal Circuit 100 k Input + UVLO/EN NIS5101 + + OVLO Current Limit Input − NUD3048 MM3Z5V1 Drain Pwr GD + DC−DC Converter Figure 13. Power Good Signal Referenced to Drain ROVLO 422 k Input + OVLO NIS5101 Drain UVLO/EN Current Limit Input − + 100 mF RL + RUVLO + Cdelay Rlimit 20 W 50 RUVLO = Open 40 DELAY TIME (mS) 30 RUVLO = 470k 20 10 RUVLO = 200k 0 0 40 80 120 160 200 Cdelay_UVLO pin (nF) Figure 14. Increased Delay Time Circuit http://onsemi.com 7 NIS5101 TYPICAL DEVICE PERFORMANCE FOR DIFFERENT SYSTEM INDUCTANCE VALUES System Inductance RUVLO Input + UVLO/EN NIS5101 Drain OVLO Current Limit Input − + Load + + ROVLO Rlimit Figure 15. System Inductance Test Circuit 10 SYSTEM INDUCTANCE (mH) 1 0.1 0.01 0 1 2 3 4 5 6 7 8 9 10 CURRENT (AMPS) Figure 16. Total System Inductance vs. Current http://onsemi.com 8 NIS5101 OPERATION DESCRIPTION Turn−on The SMART HotPlug monitors the input voltage by sensing the voltage across the Input + to Input − pins. When the UVLO voltage has been reached, the internal circuitry slowly charges the gate of the internal SENSEFET™. There will be a slight delay of several milliseconds before the SENSEFET begins conduction. This may be increased by adding a capacitor to the UVLO pin. For a discussion of this, see application note AND8115/D. The SENSEFET will increase the load current with a controlled di/dt until the current limit level has been reached. At this point the SENSEFET will enter a constant current mode of operation until the load capacitor has been fully charged. If the thermal limit threshold is reached before the capacitor reaches its final charge level, the device will shut down until the die temperature reaches 95°C and then restart, if it is the auto−retry device. The thermal latching version must not be allowed to reach the thermal shutdown level at turn−on as this will cause it to latch in an off state. During the capacitor charging period, the dv/dt of the capacitor is: I dv dt + LIMIT CLOAD Faults Once the load capacitance is charged, the SENSEFET will become fully enhanced as long as the current does not reach the current limit threshold, or is shut−down due to an overvoltage, undervoltage or thermal fault. Both the UVLO and OVLO circuits incorporate hysteresis to assure clean turn−on and turn−offs with no chatter. The thermal latching circuit will require the input power to be recycled to resume operation after a fault. The current limit is always active, so any transient or overload will always be limited. Circuit Description Undervoltage Lockout: The UVLO circuit holds the chip off when the input voltage is less than the turn−on limit. It includes internal hysteresis to assure clean on/off switching. An internal divider sets the turn−on voltage level at 46 V. This voltage can be reduced by adding an external resistor from the UVLO pin to the Input + pin. The equivalent circuit is shown in Figure 17. Drain Input + RUVLO 200 k UVLO/ ENABLE 100 k Vz ZD1 Vreg 12.5 V 50 k Input − Figure 17. Undervoltage Lockout Circuit http://onsemi.com 9 NIS5101 The theoretical equation for the UVLO turn−on voltage is: RUVLO (kW) + 215 Vin * 2970 46.8 * Vin Where Vin is the desired turn−on voltage, and RUVLO is the programming resistance from the UVLO pin to the Input + pin. The UVLO trip point voltage calculated through the theoretical formula may show small variations with respect to Figure 3, therefore it is recommended to use the formulas gotten from the UVLO characterization, which are shown below: RUVLO (kW) = e [(y+4.4706) / 6.4484]; for TJ = 25°C RUVLO (kW) = e [(y+4.6185) / 6.8525]; for TJ = 120°C RUVLO (kW) = e [(y+5.7642) / 6.7234]; for TJ = −40°C where “y” is the desired UVLO value. Drain Vreg Input + 280 k OVLO 400 k 11 V 40 k To reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the UVLO pin to the Input – pin. This will create a low pass filter with a cutoff frequency of f. The required capacitance on this pin is: C+ 1 2p · f 150 k ) RUVLO · 200 k RUVLO)200 k Overvoltage Lockout: The overvoltage shutdown circuit is an optional protection feature that can be disabled by simply grounding the OVLO pin. This circuit contains an internal Zener diode/resistor combination in series with the gate of a FET. When the input + to input − voltage reaches a level sufficient to apply the required gate voltage to the FET, operation of the SMART HotPlug will be inhibited. There is a hysteresis circuit built in that will eliminate on/off bursts due to noise on the input. The equivalent circuit is shown in Figure 18. The equation for the OVLO trip point is: 290 Vin * 3200 ROVLO (kW) + 113.7 * Vin Where ROVLO is the overvoltage programming resistor from the OVLO pin to Input +, and Vin is the desired trip point for the overvoltage shutdown to occur. The OVLO trip point voltage calculated through the theoretical formula may show small variations with respect to Figures 4, 5 and 6, therefore it is recommended to use the formulas gotten from the OVLO characterization, which are shown below: ROVLO (kW) = e [(y+69.6) / 24.82]; for TJ = 25°C ROVLO (kW) = e [(y+60.56) / 23.27]; for TJ = 120°C ROVLO (kW) = e [(y+66.47) / 23.52]; for TJ = −40°C where “y” is the desired OVLO value. Similar to the undervoltage lockout circuit, the noise sensitivity of this circuit can be reduced by adding a capacitor from the OVLO pin to Input −. The capacitor required for the desired pole frequency is: COVLO + (1 ) 31.3 · 10−6 · ROVLO) 2pf · ROVLO 400 k Input − Figure 18. Overvoltage Lockout Circuit Temperature Limit: The temperature limit circuit senses the temperature of the Power FET and removes the gate drive if the maximum level is exceeded. There is a nominal hysteresis of 40°C for this circuit. After a thermal shutdown, the device will automatically restart when the temperature drops to a safe level as determined by the hysteresis. Current Limit: The SMART HotPlug uses a SENSEFET to measure the Drain Current. The behavior of the SENSEFET in a short circuit condition varies from that in an overload because there is sufficient voltage across the drain to source terminals for the sense current to follow the ratio of the sense cells to main FET cells. This is not the case when the device is fully enhanced, since there are only a few millivolts from drain to source. In this condition, the sense voltage follows a different set of equations. http://onsemi.com 10 NIS5101 An overload condition is one in which the FET is fully enhanced and operating at it’s minimum RDSon. A short circuit condition occurs when either the load has shorted or upon turn on, as the load capacitor to the hot swap device initially looks like a short circuit. A single resistor will determine both the short circuit and overload current. For example, a 110 W resistor would result in a 1 A current limit when charging the capacitance at turn on, but once the FET is fully enhanced, it would allow the load to operate at a current up to 2.5 A. Once the 2.5 A limit is reached, any further reduction in load impedance will result in a short circuit condition and the current will be reduced to 1 amp. As with all SMART HotPlug devices, the current limit will never shut down the limiter. Only the thermal limit will stop the flow of current to the load. Once the current is stopped due to the thermal limit, it will remain off until input power is recycled for the latching version, or it will continuously retry to start again if it is the auto−retry version. The ILimit graph shown in Figure 2 was generated from the data of the ILimit characterization, the formulas for each of the curves and temperatures are shown below: RILimit (W) = (56.55 / y)1.20; for TJ = 25C RILimit (W) = (52.91 / y)1.22; for TJ = 120°C RILimit (W) = (44.80 / y)1.33; for TJ = −40°C where “y” is the desired ILimit value. Main/Mirror MOSFET Current Ratio. The ratio varies with current and sense resistance. The key parameter that 100 it is important to know is that the current sense reference voltage of the device is 50 mV. Knowing this information, it is possible to use Figure 2 on the datasheet for the current limit to calculate the ratio for any condition. For ”normal” operating condition, the overload curve would apply. If a 100 W for the ILimit resistor is used, the sense current would be 50 mV/ 100 W at the current limit level, which results in 500 mA. The drain current is 2.7 A under this condition, so the ratio is 5400:1. Same analysis can be made for “short circuit” conditions, the only difference is that the short circuit curve of Figure 2 is used to do the ratio calculations instead. There is a 5 W resistor in series with the sense cells. This has a tolerance of about 10% and should be taken into account when making the above calculations. Turn−on Surge: During the turn−on event, there is a large amount of energy dissipated due to the linear operation of the power device. The energy rating is the amount of energy that the device can absorb before the thermal limit circuit will shut the unit down. This is very important specially for the latch off device as it determines the maximum load capacitance that the device can charge before the thermal limit shuts the device down. The calculation of this is not very simple as it depends on several factors such as the input voltage (Vin), load capacitance (CL), current limit settings (ILimit) and device’s thermal transient response, therefore, it is recommended to do lab evaluations for these purposes. Figure 19 shows the device’s thermal transient response for minimum pad. THETA J(t) (°C/W) 10 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 TIME (seconds) Figure 19. Thermal Transient Response http://onsemi.com 11 NIS5101 PACKAGE DIMENSIONS S−PAK−7 EX SUFFIX CASE 553AA−01 ISSUE O A A1 U V H NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH AND METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF PLATING THICKNESS. 5. FOOT LENGTH MEASURED AT INTERCEPT POINT BETWEEN DATUM A AND LEAD SURFACE. INCHES MIN MAX 0.365 0.375 0.350 0.360 0.310 0.320 0.070 0.080 0.025 0.031 0.010 BSC 0.050 BSC 0.410 0.420 0.030 0.050 0.001 0.005 0.035 0.045 0.010 BSC 0.031 0.041 0_ 6_ 0.256 BCS 0.316 BSC 0.010 BSC MILLIMETERS MIN MAX 9.27 9.52 8.89 9.14 7.87 8.13 1.78 2.03 0.63 0.79 0.25 BSC 1.27 BSC 10.41 10.67 0.76 1.27 0.03 0.13 0.89 1.14 0.25 BSC 0.79 1.04 0_ 6_ 6.50 BSC 8.03 BSC 0.25 BSC K E M B D 7 PL G DETAIL A L C N C L W P R −A− DETAIL A DIM A A1 B C D E G H K L M N P R U V W The product described herein (NIS5101), may be covered by one or more of the following U.S. patents: 6,781,502; 7,099,135. Other patents may be pending. SENSEFET and SMART HotPlug are trademarks of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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