NIS5112
Electronic Fuse
The NIS5112 is an integrated switch utilizing a high side N−channel
FET driven by an internal charge pump. This switch features a
MOSFET which allows for current sensing using inexpensive chip
resistors instead of expensive, low impedance current shunts.
It is designed to operate in 12 V systems and includes a robust
thermal protection circuit.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
Integrated Power Device
Power Device Thermally Protected
No External Current Shunt Required
Enable/Timer Pin
Adjustable Slew Rate for Output Voltage
9 V to 18 V Input Range
30 mW Typical
Internal Charge Pump
ESD Ratings: Human Body Model (HBM); 4000 V
These are Pb−Free Devices
8
SOIC−8 NB
CASE 751
8
1
1
112x
AYWWG
G
x
= L for thermal latch off
= H for thermal auto−retry
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Typical Applications
• Hard Drives
ORDERING INFORMATION
Package
Shipping†
NIS5112D1R2G
SOIC−8
Latch Off
(Pb−Free)
2500
Tape & Reel
NIS5112D2R2G
SOIC−8
Auto−Retry
(Pb−Free)
2500 /
Tape & Reel
Device
8
VCC
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Charge
Pump
Voltage
Regulator
Current
Limit
Current Limit
4
Overvoltage
Clamp
Source
5, 6, 7
Thermal
Latch
Voltage
Slew Rate
Enable/
Timer
Enable/Timer
3
GND
1
dV/dt
2
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2011
April, 2017 − Rev. 10
1
Publication Order Number:
NIS5112/D
NIS5112
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
Function
Description
3
Enable/Timer
A high level signal on this pin allows the device to begin operation. Connection of a capacitor will delay
turn on for timing purposes. A low input signal inhibits the operation.
1
Ground
4
ILimit
5,6,7
Source
2
dV/dt
A capacitor from this pin to ground programs the slew rate of the output at turn on. This capacitor is
discharged by an internal discharge circuit when the device is disabled via the enable pin.
8
VCC
Positive input voltage to the device.
Negative input voltage to the device. This is used as the internal reference for the IC.
A resistor between this pin and the source pin sets the current limit level.
Source of power FET, which is also the switching node for the load.
Table 2. MAXIMUM RATINGS (Maximum ratings are those, that, if exceeded, may cause damage to the device. Electrical
characteristics are not guaranteed over this range)
Rating
Symbol
Value
Unit
Input Voltage, Operating,
Steady−State (Input+ to Input−)
Transient (Conditions 1 ms)
Vin
−0.3 to 18
−0.3 to 25
V
Drain Voltage, Operating,
Steady−State (Drain to Input−)
Transient (Conditions 1 ms)
VDD
−0.3 to 18
−0.3 to 25
V
Drain Current, Peak (Internally Clamped)
IDpk
25
A
Drain Current, Continuous (TA=25°C), (Note 2)
IDavg
5.3
A
Thermal Resistance, Junction−to−Air
0.5 in2 Copper
1.0 in2 Copper
QJA
120
110
°C/W
°C/W
Thermal Resistance, Junction−to−Lead (Pin 8)
QJL
27
°C/W
Power Dissipation (TA = 25°C) (Note 1)
Pmax
1.0
W
Operating Temperature Range (Note 2)
TJ
−40 to 175
°C
Nonoperating Temperature Range
TJ
−55 to 175
°C
Lead Temperature, Soldering (10 Sec)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on FR−4 board, 1 in sq pad, 1 oz coverage.
2. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as
specified.
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2
NIS5112
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, RLIMIT = 56 W TJ = 25°C)
Characteristics
Symbol
Min
Typ
Max
Unit
Delay Time (Enabling of Chip to Beginning of Conduction (10% of IPK))
Tdly
−
5.0
−
ms
Charging Time (Beginning of Conduction to 90% of Vout)
CdV/dt = 1 mF, Cload = 1000 mF
tchg
−
64
−
ms
RDSon
−
23.5
28
37
27.5
32
43.5
−
−
−
−
−
−
120
120
200
−
396
−
pF
POWER FET
ON Resistance
(ID = 2 A, TJ = −20°C) (Note 3)
(ID = 2 A, TJ = 25°C)
(ID = 2 A, TJ = 100°C) (Note 3)
Off State Output Voltage
(Vin = 12 Vdc, Enable Low, Vdc, TJ = −20°C) (Note 3)
(Vin = 12 Vdc, Enable Low, TJ = 25°C)
(Vin = 12 Vdc, Enable Low, TJ = 100°C) (Note 3)
Voff
Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 10 kHz)
mW
mV
THERMAL LATCH
Shutdown Temperature (Note 3)
TSD
125
135
145
°C
Thermal Hysteresis (Auto Retry Only) (Note 3)
Thyst
−
40
−
°C
2.45
2.5
2.7
−
−
−
−
−
−
−
−
−
−
−
−
1.8
1.9
2.0
67
70
71
80
83
84
90
92
96
14
14
13
15.5
15
14.5
17
16.2
16
2.05
2.0
1.7
2.7
2.5
2.3
3.2
3.0
2.7
3.7
3.5
3.4
4.6
4.4
4.3
5.5
5.3
5.2
0.130
0.15
0.170
67
70
71
80
83
84
90
92
96
ENABLE/TIMER
Enable Voltage (Turn−on)
(Rload = 2 K, TJ = −20°C) (Note 3)
(Rload = 2 K, TJ = 25°C)
(Rload = 2 K, TJ = 100°C) (Note 3)
VENon
Enable Voltage (Turn−off)
(Rload = 2 K, TJ = −20°C) (Note 3)
(Rload = 2 K, TJ = 25°C)
(Rload = 2 K, TJ = 100°C) (Note 3)
VENoff
Charging Current (Current Sourced into Timing Cap)
(TJ = −20°C) (Note 3)
(TJ = 25°C)
(TJ = 100°C) (Note 3)
ICharge
V
V
mA
OVERVOLTAGE CLAMP
Output Clamping Voltage
(VCC = 18 V, TJ = −20°C) (Note 3)
(VCC = 18 V, TJ = 25°C)
(VCC = 18 V, TJ = 100°C) (Note 3)
VClamp
V
CURRENT LIMIT
Short Circuit Current Limit,
(RextILimit = 56 W, TJ = −20°C) (Note 3)
(RextILimit = 56 W, TJ = 25°C)
(RextILimit = 56 W, TJ = 100°C) (Note 3)
ILim−SS
Overload Current Limit, (Note 3)
(RextILimit = 56 W, TJ = −20°C)
(RextILimit = 56 W, TJ = 25°C)
(RextILimit = 56 W, TJ = 100°C)
ILim−OL
A
A
dV/dt CIRCUIT
Slew Rate
(CdV/dt = 1 mf)
dV/dt
Charging Current (Current Sourced into dV/dt Cap)
(TJ = −20°C) (Note 3)
(TJ = 25°C)
(TJ = 100°C) (Note 3)
IdV/dt
Max Capacitor Voltage
Vmax
−
−
VCC
V
Bias Current (Device Operational, Load Open, Vin = 12 V)
IBias
−
1.45
2.0
mA
Minimum Operating Voltage
Vmin
−
−
9.0
V
V/ms
mA
TOTAL DEVICE
3. Verified by design.
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3
NIS5112
100
140
TA = 25°C
120
100
POWER (W)
ILimit (A)
10
ILIMIT_OL
1
80
60
40
ILIMIT_SS
0
1/2 in2, 1 oz copper,
double sided board
10
100
20
0
1000
1
10
RextILimit (W)
100
TIME (ms)
Figure 2. Current Limit Adjustment
Figure 3. Overload vs. Shutdown Time
Source
+12 V
56 W
Current Limit
NIS5112
Enable signal is compatible
with open collector devices
as well as most families.
Enable/
Timer GND
dV/dt
Load
1 mF
Enable
GND
(Typical operating conditions: Vin = 12 V, RILimit = 56 W, CdV/dt = 1 mF)
Figure 4. Typical Application Circuit
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4
1000
10000
NIS5112
Input Voltage
Output Voltage
Slew Rate = 0.14 V/ms
Load Current
Figure 5. Turn−on Waveforms for a Resistive Load of 10 W (CdV/dt = 1 mf)
Input Voltage
Output Voltage
Slew Rate = 0.14 V/ms
Load Current (i = C dV/dt)
Figure 6. Turn−on Waveforms for a Load Capacitance of 3,300 mf (CdV/dt = 1 mf)
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5
NIS5112
Input Voltage
Vout Regulated at 15 V
Load Current
Figure 7. Turn−on Waveforms for an Overvoltage Condition (10 W Resistive Load)
10 ms/div
(2 V/div)
(1 A/div)
Figure 8. Current Waveforms for Overload, Short Circuit and Thermal Shutdown
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6
NIS5112
DEVICE OPERATION
Basic Operation
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
current, die temperature, turn−on di/dt and turn−on dV/dt, as
well as an enable/timer function.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The dV/dt of the output voltage can be
programmed by the addition of a capacitor to the dV/dt pin,
or if left open, the output current will be limited by the
internally controlled di/dt.
The device will remain on as long as the temperature does
not exceed the 135°C limit that is programmed into the chip.
The current limit circuit does not shut down the part but will
reduce the conductivity of the FET to maintain a constant
current as long as it remains at the set level. The input
overvoltage clamp also does not shut down the part, but will
limit the output voltage to 15 V in the event that the input
exceeds that level.
The device can be turned on and off by the enable/timer
function, which can also be used to reset the device after a
thermal fault if the thermal latch version is chosen.
An internal charge pump provides bias for the gate voltage
of the internal N−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage (VCC) and ground.
Source
80 mA
R
+
−
R
Enable
dV/dt
Figure 9. dV/dt Circuit
Overvoltage Clamp
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the output
voltage exceeds 15 V, the gate drive of the main FET is
reduced to limit the output. This is intended to allow
operation through transients while protecting the load. If an
overvoltage condition exists for many seconds, the device
may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
dV/dt
This circuit is comprised of an operational amplifier and
current source as shown in Figure 9. The enable circuit
controls a FET that keeps the slew−rate capacitor discharged
any time the device is disabled. When the enable pin is
released (low−to−high transition) or when power is applied
with the enable pin in a high state, the dV/dt capacitor begins
to charge due to the 80 mA in the current source. The
amplifier controls the output voltage and tracks the voltage
on the dV/dt cap scaled by a factor of 2. The output voltage
will continue to ramp higher until it reaches the input
voltage, or until the 15 V clamp limits it.
The equation for the output slew rate is
dV/dt = (I/CdV/dt) x 2.
Where:
I – is 80 mA (internal current source)
CdV/dt – is the desired dV/dt capacitor value.
The dV/dt ramp begins with a small step of about 200 mV.
This step causes a current surge into the output load
capacitance which can be seen in Figure 6. The peak level
of this surge will be limited to the overload level of the
current limit.
Enable/Timer
The enable/timer pin can function either as a direct enable
pin, or as a time delay. In the enable mode, an open collector
device is connected to this pin. When the device is in its low
impedance mode, this pin is low and the operation of the chip
is disabled. If a time delay is required, a capacitor is added
to this pin.
If a capacitor is added without an open collector device,
the turn on will be delayed from the time at which the UVLO
voltage is reached. If an open collector device is also used,
the delay will start from the time that it goes into its high
impedance state. The capacitor is charged by an internal
current source of 80 mA (typical).
The nominal trip voltage of the comparator is 2.5 V and
was designed to be compatible with most logic families. In
general, logic gates can be tied directly to this pin, but it is
recommended that this be tested.
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7
NIS5112
Thermal Protection Circuit
The temperature limit circuit senses the temperature of the
Power FET and removes the gate drive if the maximum level
is exceeded. The NIS5112 device has two different thermal
limit versions, auto−retry and latch off.
There is an inherent delay in the turn on of the electronic
fuse, due to the method of gate drive used. The gate of the
power FET is charged through a high impedance resistor,
and from the time that the gate starts charging until the time
that it reaches its threshold voltage, there will be no
conduction. Once the gate reaches its threshold voltage, the
output current will begin a controlled ramp up phase.
This delay will be added to any timing delay due to the
enable/timer circuit. Figure 10 shows a simplified diagram
of the enable/timer circuit.
Auto−Retry Version
The device will shut down when the thermal limit
threshold is reached (TJ = 135°C, typical) and will not turn
back on until the die temperature reduces down to 95°C
(40°C hysteresis, typical). It will keep auto−retrying until
the fault condition is removed or power is turned−off.
Latch−Off Version
Enable/
Timer
For the latch−off version, the device will shut down when
the thermal limit threshold is reached (TJ = 135°C, typical)
and will remain off until power is reset.
80 mA
2.5 V
+
−
Enabled
Figure 10. Simplified Schematic Diagram of the
Enable/Timer Circuit
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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© Semiconductor Components Industries, LLC, 2019
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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