NLAS4051SDTR2G

NLAS4051S Analog Multiplexer/ Demultiplexer TTL Compatible, Single−Pole, 8−Position Plus Common Off The NLAS4051S is an improved version of the MC14051 and MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology for lower RDS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to ±3.0 V to pass a 6.0 VPP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie VEE, pin 7 to ground. For dual supply operation, VEE is tied to a negative voltage, not to exceed maximum ratings. Features • Improved RDS(on) Specifications • Pin for Pin Replacement for MAX4051 and MAX4051A • One Half the Resistance Operating at 5.0 V Single or Dual Supply Operation ♦ Single 2.5−5.0 V Operation, or Dual ±3.0 V Operation ♦ With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic, No Translators Needed ♦ Address and Inhibit Logic are Over−Voltage Tolerant and May Be Driven Up +6.0 V Regardless of VCC Improved Linearity Over Standard HC4051 Devices ♦ • • Space Saving TSSOP Package • This is a Pb−Free Device VCC 16 1 NO1 MARKING DIAGRAM 16 16 NLAS 4051 ALYWG G 1 TSSOP−16 DT SUFFIX CASE 948F A L Y W G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NLAS4051SDTR2G TSSOP−16 2500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NO2 NO4 NO0 NO6 ADDC ADDB ADDA 15 14 13 12 2 3 NO3 COM http://onsemi.com 4 5 NO7 NO5 11 10 6 7 Inhibit VEE 9 8 GND Figure 1. Pin Connection (Top View) © Semiconductor Components Industries, LLC, 2008 May, 2008 − Rev. 0 1 Publication Order Number: NLAS4051S/D NLAS4051S TRUTH TABLE NO0 Address Inhibit C B A ON SWITCHES* NO1 1 X don’t care X don’t care X don’t care All switches open NO2 0 0 0 0 COM−NO0 0 0 0 1 COM−NO1 0 0 1 0 COM−NO2 0 0 1 1 COM−NO3 0 1 0 0 COM−NO4 0 1 0 1 COM−NO5 0 1 1 0 COM−NO6 0 1 1 1 COM−NO7 NO3 COM NO4 NO5 NO6 NO7 ADDC ADDB ADDA *NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction. LOGIC Inhibit Figure 2. Logic Diagram ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Parameter Symbol Value Unit Negative DC Supply Voltage (Referenced to GND) VEE −7.0 to )0.5 V Positive DC Supply Voltage (Note 1) (Referenced to GND) (Referenced to VEE) VCC −0.5 to )7.0 −0.5 to )7.0 V VIS VEE −0.5 to VCC )0.5 V (Referenced to GND) VIN −0.5 to 7.0 V I $50 mA TSTG −65 to )150 °C Lead Temperature, 1 mm from Case for 10 Seconds TL 260 °C Junction Temperature under Bias TJ )150 °C Thermal Resistance JA 164 °C/W Power Dissipation in Still Air PD 450 mW MSL Level 1 FR UL 94 V−0 @ 0.125 in VESD u2000 u200 u1000 V ILATCHUP $300 mA Analog Input Voltage Digital Input Voltage DC Current, Into or Out of Any Pin Storage Temperature Range Moisture Sensitivity Flammability Rating ESD Withstand Voltage Latchup Performance Oxygen Index: 30% − 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125°C (Note 5) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The absolute value of VCC $|VEE| ≤ 7.0. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. http://onsemi.com 2 NLAS4051S ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Negative DC Supply Voltage (Referenced to GND) VEE −5.5 GND V Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) VCC 2.5 2.5 5.5 6.6 V VIS VEE VCC V VIN 0 5.5 V TA −55 125 °C tr, tf 0 0 100 20 ns/V Analog Input Voltage Digital Input Voltage (Note 6) (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.0 V $ 0.3 V VCC = 5.0 V $ 0.5 V 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level. DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) Symbol Condition Parameter Guaranteed Limit VCC V −55 to 25°C v85°C v125°C Unit Minimum High−Level Input Voltage, Address and Inhibit Inputs VIH 2.5 3.0 4.5 5.5 1.75 2.1 3.15 3.85 1.75 2.1 3.15 3.85 1.75 2.1 3.15 3.85 V Maximum Low−Level Input Voltage, Address and Inhibit Inputs VIL 2.5 3.0 4.5 5.5 .45 0.9 1.35 1.65 .45 0.9 1.35 1.65 .45 0.9 1.35 1.65 V VIN = 6.0 or GND IIN 0 V to 6.0 V $0.1 $1.0 $1.0 A Address, Inhibit and VIS = VCC or GND ICC 6.0 4.0 40 80 A Maximum Input Leakage Current, Address or Inhibit Inputs Maximum Quiescent Supply Current (per Package) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS − Analog Section Symbol Parameter Guaranteed Limit VCC V VEE V −55 to 25°C v85°C v125°C Unit RON 3.0 4.5 3.0 0 0 −3.0 86 37 26 108 46 33 120 55 37  Test Conditions Maximum “ON” Resistance (Note 7) VIN = VIL or VIH VIS = (VEE to VCC) |IS| = 10 mA (Figures 4 thru 9) Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VIN = VIL or VIH, VIS= 2.0 V VIS = ½ (VCC − VEE), VIS= 3.0 V |IS| = 10 mA, VIS= 2.0 V RON 3.0 4.5 3.0 0 0 −3.0 15 13 10 20 18 15 20 18 15  ON Resistance Flatness |IS| = 10 mA VCOM = 1, 2, 3.5 V VCOM = 2, 0, 2 V Rflat(ON) 4.5 3.0 3.0 4 2 4 2 5 3  Maximum Off−Channel Leakage Current Switch Off VIN = VIL or VIH VIO = VCC −1.0 V or VEE +1.0 V (Figure 17) INC(OFF) INO(OFF) 6.0 3.0 0 −3.0 0.1 0.1 5.0 5.0 100 100 nA Maximum On−Channel Leakage Current, Channel− to−Channel Switch On VIO = VCC −1.0 V or VEE +1.0 V (Figure 17) ICOM(ON) 6.0 3.0 0 −3.0 0.1 0.1 5.0 5.0 100 100 nA 7. At supply voltage (VCC) approaching 2.5 V the analog switch on−resistance becomes extremely non−linear. Therefore, for low voltage operation it is recommended that these devices only be used to control digital signals. http://onsemi.com 3 NLAS4051S ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC CHARACTERISTICS (Input tr = tf = 3 ns) Guaranteed Limit Parameter Minimum Break−Before− Make Time Symbol Test Conditions VIN = VIL or VIH VIS = VCC RL = 300  CL = 35 pF (Figure 19) −55 to 25°C VCC V VEE V Min Typ* v85°C v125°C Unit 3.0 4.5 3.0 0.0 0.0 −3.0 1.0 1.0 1.0 6.5 5.0 3.5 − − − − − − ns tBBM *Typical Characteristics are at 25°C. AC CHARACTERISTICS (CL = 35 pF, Input tr = tf = 3 ns) Guaranteed Limit VCC V VEE V tTRANS 2.5 3.0 4.5 3.0 Turn−on Time (Figures 14, 15, 20, and 21) Inhibit to NO or NC tON Turn−off Time (Figures 14, 15, 20, and 21) Inhibit to NO or NC tOFF Symbol Parameter Transition Time (Address Selection Time) (Figure 18) −55 to 25°C Min v85°C Typ Max 0 0 0 −3.0 22 20 16 16 40 28 23 23 2.5 3.0 4.5 3.0 0 0 0 −3.0 22 18 16 16 2.5 3.0 4.5 3.0 0 0 0 −3.0 22 18 16 16 Min v125°C Max Min Max Unit 45 30 25 25 50 35 30 28 ns 40 28 23 23 45 30 25 25 50 35 30 28 ns 40 28 23 23 45 30 25 25 50 35 30 28 ns Typical @ 255C, VCC = 5.0 V Maximum Input Capacitance, Select Inputs Analog I/O CIN 8 CNO or CNC 10 Common I/O CCOM 10 Feedthrough C(ON) 1.0 pF ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Parameter Condition Symbol Typ VCC V VEE V 25°C Unit Maximum On−Channel Bandwidth or Minimum Frequency Response VIS = ½ (VCC − VEE) Source Amplitude = 0 dBm (Figures 10 and 22) BW 3.0 4.5 6.0 3.0 0.0 0.0 0.0 −3.0 80 90 95 95 MHz Off−Channel Feedthrough Isolation f =100 kHz; VIS = ½ (VCC − VEE) Source = 0 dBm (Figures 12 and 22) VISO 3.0 4.5 6.0 3.0 0.0 0.0 0.0 −3.0 −93 −93 −93 −93 dB Maximum Feedthrough On Loss VIS = ½ (VCC − VEE) Source = 0 dBm (Figures 10 and 22) VONL 3.0 4.5 6.0 3.0 0.0 0.0 0.0 −3.0 −2 −2 −2 −2 dB Charge Injection VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 , CL= 1000 pF, Q = CL * VOUT (Figures 16 and 23) Q 5.0 3.0 0.0 −3.0 9.0 12 pC Total Harmonic Distortion THD + Noise fIS = 1 MHz, RL = 10 K, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 13) 6.0 3.0 0.0 −3.0 0.10 0.05 http://onsemi.com 4 THD % NLAS4051S 100 100 10 2.0 V 80 0.1 RON () ICC (nA) 1 0.01 VCC = 3.0 V 0.001 40 3.0 V 4.5 V VCC = 5.0 V 0.00001 −40 −20 0 20 60 80 100 0 −4.0 120 −2.0 0 2.0 4.0 6.0 Temperature (°C) VIS (VDC) Figure 3. ICC versus Temp, VCC = 3 V and 5 V Figure 4. RON versus VCC, Temp = 255C 50 100 90 125°C 125°C 85°C 40 80 25°C 70 RON () 60 50 85°C 40 25°C 30 20 −55°C 30 20 10 −55°C 10 0 0.5 1.0 1.5 0 2.0 0.5 1.0 1.5 2.0 2.5 VCom (V) Figure 5. Typical On Resistance VCC = 2.0 V, VEE = 0 V Figure 6. Typical On Resistance VCC = 3.0 V, VEE = 0 V 25 20 15 15 RON () 20 25°C 10 3.0 125°C 125°C 85°C 85°C 10 25°C −55°C −55°C 5 5 0 0 0 VCom (V) 25 RON () 5.5 V 20 0.0001 RON () 60 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VCom (V) VCom (V) Figure 7. Typical On Resistance VCC = 4.5 V, VEE = 0 V Figure 8. Typical On Resistance VCC = 5.5 V, VEE = 0 V http://onsemi.com 5 4.0 4.5 NLAS4051S 25 125°C 85°C RON () 20 15 10 −55°C 25°C 5 0 −4 −2 0 VCom (V) 2 4 50 90 40 72 30 54 PHASE SHIFT 18%/DIV (dB) BANDWIDTH (dB) Figure 9. Typical On Resistance VCC = 3.3 V, VEE = −3.3 V 20 10 0 −10 BANDWIDTH (ON−RESPONSE) −20 −30 −40 −50 36 18 0 PHASE SHIFT −18 −36 −54 −72 −90 0.1 1.0 10 100 0.1 FREQUENCY (mHz) 1.0 10 100 FREQUENCY (mHz) Figure 10. Bandwidth, VCC = 5.0 V Figure 11. Phase Shift, VCC = 5.0 V 0 0 −20 −30 DISTORTION (%) OFF ISOLATION 10 dB/DIV −10 −40 −50 −60 −70 3.0 5.5 0.1 4.5 $3.3 −80 −90 −100 0.1 1.0 10 0.01 100 10 FREQUENCY (mHz) 100 1000 10000 10000 FREQUENCY (mHz) Figure 12. Off Isolation, VCC = 5.0 V Figure 13. Total Harmonic Distortion http://onsemi.com 6 NLAS4051S 30 30 TA = 25°C VCC = 4.5 V 25 20 20 TIME (ns) TIME (ns) 25 15 tON (ns) 10 15 tOFF (ns) 5 0 2.5 3 3.5 4 4.5 10 tON 5 tOFF 0 −55 5 −40 25 85 125 VCC (VOLTS) Temperature (°C) Figure 14. tON and tOFF versus VCC Figure 15. tON and tOFF versus Temp 3.0 100 2.5 10 VCC = 5 V LEAKAGE (nA) Q (pC) 2.0 1.5 1.0 0.5 VCC = 3 V 0 1 ICOM(OFF) 2 3 4 VCC = 5.0 V INO(OFF) 0.001 5 −55 −20 25 70 85 125 VCOM (V) TEMPERATURE (°C) Figure 16. Charge Injection versus COM Voltage Figure 17. Switch Leakage versus Temperature VCC 0.1 F ICOM(ON) 0.1 0.01 0 −0.5 1 VCC Output VEE VOUT 300  50% Input 50% 0V 35 pF VCC 90% Output Address Select Pin VEE 10% ttrans Figure 18. Channel Selection Propagation Delay http://onsemi.com 7 ttrans NLAS4051S VCC DUT VCC Input Output GND VOUT 0.1 F 300  tBMM 35 pF 90% 90% of VOH Output Address Select Pin GND Figure 19. tBBM (Time Break−Before−Make) VCC DUT Input VCC 0.1 F 50% 0V Output VOUT Open 50% 300  VOH 35 pF 90% 90% Output GND Enable Input tON tOFF Figure 20. tON/tOFF VCC VCC Input DUT Output 50% 300  VOUT Open 50% 0V VCC 35 pF Output Input 10% VOL Enable tOFF Figure 21. tON/tOFF http://onsemi.com 8 10% tON NLAS4051S 50  DUT Reference Transmitted Input Output 50  Generator 50  Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. ǒVVOUT Ǔ for VIN at 100 kHz IN V VONL = On Channel Loss = 20 Log ǒ OUTǓ for VIN at 100 kHz to 50 MHz VIN VISO = Off Channel Isolation = 20 Log Bandwidth (BW) = the frequency 3 dB below VONL Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL DUT VCC VIN Output Open GND CL Output Off Off On VIN Figure 23. Charge Injection: (Q) TYPICAL OPERATION +5.0 V 16 VEE GND +3.0 V VCC 16 VEE 7 8 GND VCC 7 8 −3.0 V Figure 24. 5.0 Volts Single Supply VCC = 5.0 V, VEE = 0 Figure 25. Dual Supply VCC = 3.0 V, VEE = −3.0 V http://onsemi.com 9 VOUT MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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