NLSF3T125MNR2

NLSF3T125 Quad Bus Buffer with 3−State Control Inputs The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NLSF3T125 requires the 3−state control input (OE) to be set High to place the output into the high impedance state. The T125 inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The NLSF3T125 input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com 1 QFN−16 CASE 485G MARKING DIAGRAM ÇÇÇ ÇÇÇ 16 1 NLSF T125 ALYW G G Features • • • • • • • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates Pb−Free Package is Available* FUNCTION TABLE Output A OE Y H L X L L H H L Z ORDERING INFORMATION Device NLSF3T125MNR2 NLSF3T125MNR2G Package Shipping† QFN−16 3000/Tape & Reel QFN−16 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NLSF3T125 Inputs A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) . *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 4 1 Publication Order Number: NLSF3T125/D NLSF3T125 Active−Low Output Enables 16 A1 1 Y1 15 OE1 5 4 A2 Y2 3 OE2 7 8 A3 Y3 9 OE3 10 12 A4 Y4 13 OE4 Figure 1. Logic Diagram OE1 VCC A1 16 15 14 OE4 Exposed Pad (EP) 13 Y1 1 12 A4 NC 2 11 NC OE2 3 10 Y4 A2 4 9 5 6 Y2 7 GND Y3 OE3 8 A3 Figure 2. QFN − 16 Pinout (Top View) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Parameter Symbol Value Unit DC Supply Voltage VCC – 0.5 to + 7.0 V DC Input Voltage Vin – 0.5 to + 7.0 V Vout – 0.5 to + 7.0 – 0.5 to VCC + 0.5 V Input Diode Current IIK − 20 mA Output Diode Current (VOUT < GND; VOUT > VCC) IOK ± 20 mA DC Output Current, per Pin Iout ± 25 mA DC Supply Current, VCC and GND Pins ICC ± 75 mA Power Dissipation in Still Air PD 500 mW Tstg – 65 to + 150 °C DC Output Voltage Storage Temperature Output in 3−State High or Low State QFN Packages Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. NLSF3T125 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply Voltage Parameter VCC 2.0 5.5 V DC Input Voltage Vin 0 5.5 V Vout 0 0 5.5 VCC V TA − 40 + 85 °C tr, tf 0 20 ns/V DC Output Voltage Output in 3−State High or Low State Operating Temperature VCC = 5.0 V ±0.5 V Input Rise and Fall Time DC ELECTRICAL CHARACTERISTICS Parameter Test Conditions Symbol Minimum High−Level Input Voltage 2.3 V ± 0.3 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V VIH Maximum Low−Level Input Voltage 2.3 V ± 0.3 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V VIL Minimum High−Level Output Voltage VIN = VIH or VIL VOL @ IOL, 50 mA VIN = VIH or VIL IOH = − 50 mA VOH Maximum Low−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = − 2.0 mA IOH = − 4.0 mA IOH = − 8.0 mA VOL @ IOL, 50 mA VIN = VIH or VIL IOL = 50 mA VOL VIN = VIH or VIL IOL = 2.0 mA IOL = 4.0 mA IOL = 8.0 mA VCC (V) TA ≤ 85°C TA = 25°C Min Typ Max 0.5 VCC 0.4 VCC 0.44 VCC Min 0.5 VCC 0.4 VCC 0.44 VCC 0.3 VCC 0.18 VCC 0.18 VCC 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 1.82 2.58 3.94 Max 2.0 3.0 4.5 2.0 3.0 4.5 0.0 0.0 0.0 TA ≤ 125°C Min Max 0.5 VCC 0.4 VCC 0.44 VCC 0.3 VCC 0.18 VCC 0.18 VCC V 0.3 VCC 0.18 VCC 0.18 VCC 1.9 2.9 4.4 1.9 2.9 4.4 1.72 2.48 3.80 1.60 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 2.0 3.0 4.5 0.36 0.36 0.36 0.44 0.44 0.44 0.52 0.52 0.52 V Maximum Input Leakage Current VIN = 5.5 V or GND IIN 0 to 5.5 ± 0.1 ± 1.0 ± 1.0 mA Maximum Quiescent Supply Current VIN = VCC or GND ICC 5.5 2.0 20 40 mA Quiescent Supply Current Input: VIN = 3.4 V ICCT 5.5 1.35 1.50 1.65 mA Maximum 3−State Leakage Current VIN = VIH or VIL VOUT = VCC or GND IOZ 5.5 ±0.25 ±2.5 ±2.5 mA Output Leakage Current VOUT = 5.5 V IOPD 0.0 0.5 5.0 10 mA http://onsemi.com 3 NLSF3T125 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ Î ÎÎ Î ÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = ≤ 85°C TA ≤ 125°C Typ Max Min Max Min Max Unit TA = 25°C Test Conditions Symbol Min VCC = 2.3 ± 0.3 V CL = 15 pF tPLH, tPHL 1.0 14.5 16.9 1.0 18.1 1.0 19.2 ns 1.0 1.0 5.6 8.1 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 12.0 16.0 ns 1.0 1.0 3.8 5.3 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 8.5 10.5 1.0 14.8 16.2 1.0 17.4 1.0 19.3 ns 1.0 1.0 5.4 7.9 8.0 11.5 1.0 1.0 9.5 13.0 1.0 1.0 11.5 15.0 ns 1.0 1.0 3.6 5.1 5.1 7.1 1.0 1.0 6.0 8.0 1.0 1.0 7.5 9.5 1.0 15.4 18.0 1.0 19.8 1.0 22.0 ns 1.0 9.5 13.2 1.0 15.0 1.0 18.0 ns 1.0 6.1 8.8 1.0 10.0 1.0 12.0 ns ns Parameter Maximum Propagation Delay, A to Y VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF Maximum Output Enable TIme, OE to Y VCC = 2.3 ± 0.3 V CL = 15 pF VCC = 3.3 ± 0.3 V CL = 15 pF RL = 1.0 kW CL = 50 pF tPZL, tPZH VCC = 5.0 ± 0.5 V CL = 15 pF RL = 1.0 kW CL = 50 pF Maximum Output Disable Time, OE to Y VCC = 2.3 ± 0.3 V CL = 15 pF VCC = 3.3 ± 0.3 V CL = 50 pF RL = 1.0 kW tPLZ, tPHZ VCC = 5.0 ± 0.5 V CL = 50 pF RL = 1.0 kW Output−to−Output Skew VCC = 3.3 ± 0.3 V CL = 50 pF (Note 1) tOSLH, tOSHL VCC = 5.0 ± 0.5 V CL = 50 pF (Note 1) Maximum Input Capacitance Cin 4 Maximum Three−State Output Capacitance (Output in High Impedance State) Cout 6 1.5 1.5 2.0 1.0 1.0 1.5 10 10 10 pF pF Typical @ 25°C, VCC = 5.0V Power Dissipation Capacitance (Note 2) CPD 15 pF 1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per buffer). CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Symbol Typ Max Unit Quiet Output Maximum Dynamic VOL VOLP 0.3 0.8 V Quiet Output Minimum Dynamic VOL VOLV − 0.3 − 0.8 V Minimum High Level Dynamic Input Voltage VIHD 3.5 V Maximum Low Level Dynamic Input Voltage VILD 1.5 V Characteristic http://onsemi.com 4 NLSF3T125 SWITCHING WAVEFORMS OE 3.0V 1.5V A tPHL tPLH 1.5V Y GND tPZL GND Y VOH tPLZ HIGH IMPEDANCE 1.5V tPZH VOL VOL + 0.3V tPHZ VOH − 0.3V 1.5V Y Figure 3. HIGH IMPEDANCE Figure 4. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST 3.0V 1.5V DEVICE UNDER TEST CL* *Includes all probe and jig capacitance OUTPUT 1 kW CL * CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit http://onsemi.com 5 NLSF3T125 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C PIN 1 LOCATION ÇÇ ÇÇ ÇÇ D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 SEATING PLANE A1 C D2 16X e L 5 NOTE 5 EXPOSED PAD 8 4 9 E2 16X K 12 1 16 16X 13 b 0.10 C A B 0.05 C e BOTTOM VIEW NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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