NTD20N03L27T4G

NTD20N03L27, NVD20N03L27 MOSFET –Power, N-Channel, DPAK 20 A, 30 V This logic level vertical power MOSFET is a general purpose part that provides the “best of design” available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The drain−to−source diode has a ideal fast but soft recovery. Features • • • • • • • • Ultra−Low RDS(on), Single Base, Advanced Technology SPICE Parameters Available Diode is Characterized for use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperatures High Avalanche Energy Specified ESD JEDAC rated HBM Class 1, MM Class A, CDM Class 0 NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant http://onsemi.com 20 A, 30 V, RDS(on) = 27 mW N−Channel D G S 4 1 2 Typical Applications Power Supplies Inductive Loads PWM Motor Controls Replaces MTD20N03L in many Applications MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 30 Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 30 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) VGS VGS ±20 ±24 ID ID 20 16 60 Adc PD 74 0.6 1.75 W W/°CW TJ, Tstg −55 to 150 °C EAS 288 mJ Drain Current − Continuous @ TA = 25_C − Continuous @ TA = 100_C − Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25_C Derate above 25°C Total Power Dissipation @ TC = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 24 A, VDS = 34 Vdc) Thermal Resistance − Junction−to−Case − Junction−to−Ambient − Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds IDM 3 DPAK CASE 369C STYLE 2 RqJC RqJA RqJA 1.67 100 71.4 TL 260 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain Vdc AYWW 20 N3LG • • • • 2 1 3 Drain Gate Source Apk °C/W °C A 20N3L Y WW G = Assembly Location* = Device Code = Year = Work Week = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 6 1 Publication Order Number: NTD20N03L27/D NTD20N03L27, NVD20N03L27 1. When surface mounted to an FR4 board using the minimum recommended pad size and repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 2 NTD20N03L27, NVD20N03L27 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Drain−to−Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Min Typ Max Unit 30 − − 43 − − − − − − 10 100 − − ±100 1.0 − 1.6 5.0 2.0 − − − 28 23 31 27 − − 0.48 0.40 0.54 − gFS − 21 − mhos pF OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ =150°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 2) (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 2) (VGS = 5.0 Vdc, ID = 20 Adc) (VGS = 5.0 Vdc, ID = 10 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 2) (VDS = 5.0 Vdc, ID = 10 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance Ciss − 1005 1260 Coss − 271 420 Crss − 87 112 td(on) − 17 25 tr − 137 160 td(off) − 38 45 tf − 31 40 QT − 13.8 18.9 Q1 − 2.8 − Q2 − 6.6 − − − 1.0 0.9 1.15 − trr − 23 − ta − 13 − tb − 10 − QRR − 0.017 − SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDD = 20 Vdc, ID = 20 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 2) (VDS = 48 Vdc, ID = 15 Adc, VGS = 10 Vdc) (Note 2) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 2) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS =15 Adc, VGS = 0 Vdc, dlS/dt = 100 A/ms) (Note 2) Reverse Recovery Stored Charge VSD Vdc ns mC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. ORDERING INFORMATION Package Shipping† NTD20N03L27T4G DPAK (Pb−Free) 2500 / Tape & Reel NVD20N03L27T4G* DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. http://onsemi.com 3 NTD20N03L27, NVD20N03L27 VGS = 8 V 30 VGS = 4.5 V VGS = 5 V 25 20 VGS = 3.5 V VGS = 6 V 15 VGS = 3 V 10 TJ = 25°C 5 0 0.2 0.04 0.4 0.6 1 0.8 VGS = 2.5 V 1.2 1.4 1.6 1.8 28 24 TJ = 100°C 20 16 TJ = 25°C TJ = −55°C 12 8 4 1 1.5 2 2.5 3 3.5 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 100°C TJ = 25°C 0.025 0.02 TJ = −55°C 0.015 0.01 0.03 5 4.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.03 TJ = 25°C VGS = 5 V 0.025 0.02 VGS = 10 V 0.015 0.005 0 32 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = 5 V 0.035 VDS > = 10 V 36 0 0.5 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS = 4 V ID, DRAIN CURRENT (AMPS) 35 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 40 VGS = 10 V 2 1.6 1.4 5 8 12 15 18 22 25 28 32 35 38 0 4 8 12 16 20 24 28 32 36 40 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Drain Current and Temperature Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1000 ID = 10 A VGS = 5 V 1.2 1 0.8 0.6 −50 0.01 −IDSS, LEAKAGE (nA) −ID, DRAIN CURRENT (AMPS) 40 −25 0 25 50 75 100 125 TJ = 125°C 100 TJ = 100°C 10 1 150 VGS = 0 V 0 3 6 9 12 15 18 21 24 27 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 30 C, CAPACITANCE (pF) 2500 VGS, GATE−TO−SOURCE VOLTAGE (V) NTD20N03L27, NVD20N03L27 VGS − VDS 200 1500 Ciss 1000 500 Coss Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 23 25 Q 10 8 VGS 6 Q1 4 Q2 2 0 ID = 20 A TJ = 25°C 0 2 4 6 8 10 12 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 1000 IS, SOURCE CURRENT (AMPS) 20 tr 100 tf td(off) 10 1 td(on) 1 VDS = 20 V ID = 20 A VGS = 5.0 V TJ = 25°C 10 16 14 12 10 8 6 4 2 0 0.0 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 350 ID = 24 A 300 250 200 150 100 50 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 14 VGS = 0 V TJ = 25°C 18 RG, GATE RESISTANCE (W) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) 12 150 1.0 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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