NTD4810NHT4G

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Other names and brands may be claimed as the property of others. NTD4810NH Power MOSFET 30 V, 54 A, Single N−Channel, DPAK/IPAK Features Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Low RG These are Pb−Free Devices http://onsemi.com RDS(on) MAX V(BR)DSS 10 mW @ 10 V 30 V D • CPU Power Delivery • DC−DC Converters N−Channel MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) G Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±20 V ID 10.8 A Parameter Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C Continuous Drain Current (RqJA) (Note 2) TA = 25°C TA = 85°C S 4 4 4 8.4 PD 2.0 W 1 2 1 3 TA = 85°C 6.7 TA = 25°C PD 1.28 W TC = 25°C ID 54 A TC = 85°C Power Dissipation (RqJC) (Note 1) A 8.6 TC = 25°C 50 W TA = 25°C IDM 120 A TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C IS 41 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 0.3 mH, IL(pk) = 21 A, RG = 25 W) EAS 66 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C tp=10ms Operating Junction and Storage Temperature Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3 IPAK CASE 369AC (Straight Lead) 4 Drain 4 Drain 2 1 Drain 3 Gate Source 2 3 IPAK CASE 369D (Straight Lead DPAK) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 42 PD Current Limited by Package DPAK CASE 369AA (Bent Lead) STYLE 2 1 2 3 AYWW 48 10NHG ID AYWW 48 10NHG Steady State Continuous Drain Current (RqJC) (Note 1) Pulsed Drain Current 54 A 16.7 mW @ 4.5 V Applications Power Dissipation (RqJA) (Note 2) ID MAX 4 Drain AYWW 48 10NHG • • • • • 1 2 3 Gate Drain Source A Y WW 4810NH G 1 2 3 Gate Drain Source = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 4 1 Publication Order Number: NTD4810NH/D NTD4810NH THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 3.0 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 75 Junction−to−Ambient − Steady State (Note 2) RqJA 117 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS V 27 Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA VGS = 0 V, VDS = 24 V TJ = 25°C mV/°C 1.0 TJ = 125°C mA 10 "100 nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 2.5 5.2 VGS = 10 to 11.5 V ID = 30 A ID = 15 A 7.8 VGS = 4.5 V ID = 30 A 14.1 ID = 15 A 13.2 VDS = 15 V, ID = 10 A 8.0 V mV/°C 10 mW 16.7 9.0 S 1225 pF CHARGES AND CAPACITANCES Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, VDS = 12 V Output Capacitance Coss Reverse Transfer Capacitance Crss 145 Total Gate Charge QG(TOT) 8.9 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS VGS = 4.5 V, VDS = 15 V, ID = 30 A 2.5 VGS = 11.5 V, VDS = 15 V, ID = 30 A 22.5 nC 10.6 ns Gate−to−Drain Charge Total Gate Charge QGD QG(TOT) 280 12 nC 3.6 3.9 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 19.2 11.7 tf 3.6 td(on) 6.2 tr 18 td(off) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 18.5 2.2 http://onsemi.com 2 ns NTD4810NH ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.88 1.2 V TJ = 125°C 0.79 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 13.4 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 9.1 4.3 QRR 6.7 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.75 PACKAGE PARASITIC VALUES TA = 25°C 1.88 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTD4810NH TYPICAL PERFORMANCE CURVES 70 10 V 8V 6V 50 4.5 V TJ = 25°C 4.2 V 5V 40 4V 30 3.8 V 20 3.5 V 10 3.2 V 3V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5.5 5 60 50 40 30 TJ = 125°C 20 TJ = 25°C 10 TJ = −55°C 0 6 1 4 3 5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.025 ID = 30 A TJ = 25°C 0.023 0.021 0.019 0.017 0.015 0.013 0.011 0.009 0.007 4 6 5 7 8 9 10 11 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.025 TJ = 25°C 0.020 VGS = 4.5 V 0.015 0.010 VGS = 11.5 V 0.005 0 15 20 25 30 40 35 45 50 55 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100,000 2.0 VGS = 0 V ID = 30 A VGS = 10 V 10,000 1.5 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 60 1.0 0.5 0 −50 −25 TJ = 150°C 1000 TJ = 125°C 100 10 0 25 50 75 100 125 150 175 4 8 12 16 20 24 28 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 32 NTD4810NH TYPICAL PERFORMANCE CURVES 15 VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 1750 Ciss 1250 1000 Crss 750 500 Coss 250 0 15 Crss 10 5 0 5 VGS VDS 10 15 25 20 30 VDS 12 VGS 8 6 Q2 Q1 4 3 0 0 0 2 4 6 8 10 12 14 16 18 20 QG, TOTAL GATE CHARGE (nC) 22 24 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 30 1000 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 30 A VGS = 11.5 V 100 tr tf td(off) 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) 25 100 15 10 5 100 ms 1 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 10 ms VGS = 20 V SINGLE PULSE TC = 25°C 0.6 0.7 0.8 0.9 1.0 1.1 Figure 10. Diode Forward Voltage vs. Current 1000 10 0.5 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 VGS = 0 V TJ = 25°C 20 0 0.4 1 I D, DRAIN CURRENT (AMPS) 16 QT 9 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) t, TIME (ns) 20 TJ = 25°C 12 Ciss 1500 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 2000 70 ID = 21 A 60 50 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 100 125 50 75 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4810NH TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 0.1 10 100 PULSE WIDTH (ms) 1 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4810NHT4G DPAK (Pb−Free) 2500 Tape & Reel NTD4810NH−1G IPAK (Pb−Free) 75 Units/Rail NTD4810NH−35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) 75 Units/Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4810NH PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C A A E b3 c2 B 4 L3 Z D 1 2 H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z L4 b2 e c b 0.005 (0.13) M C H L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4810NH PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G H D 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− 3 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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