NTD20P06L, NTDV20P06L
MOSFET – Power, Single,
P-Channel, DPAK
-60 V, -15.5 A
Features
•
•
•
•
Withstands High Energy in Avalanche and Commutation Modes
Low Gate Charge for Fast Switching
AEC Q101 Qualified − NTDV20P06L
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) TYP
ID MAX
(Note 1)
−60 V
130 mW @ −5.0 V
−15.5 A
Applications
• Bridge Circuits
• Power Supplies, Power Motor Controls
• DC−DC Conversion
P−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Gate−to−Source
Voltage
Continuous
Value
Unit
VDSS
−60
V
VGS
$20
V
Non−Repetitive
tp v10 ms
VGSM
$30
Continuous
Drain Current
Steady State
TC = 25°C
ID
−15.5
A
Power Dissipation
Steady State
TC = 25°C
PD
65
W
IDM
$50
A
Operating Junction and Storage Temperature
TJ,
TSTG
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 25 V, VGS = 5 V, IPK = 15 A,
L = 2.7 mH, RG = 25 W)
EAS
304
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Pulsed Drain
Current
tp = 10 ms
S
MARKING DIAGRAMS
4
1 2
Symbol
Max
Unit
Junction−to−Case (Drain)
RqJC
2.3
°C/W
Junction−to−Ambient – Steady State (Note 1)
RqJA
80
Junction−to−Ambient – Steady State (Note 2)
RqJA
110
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq. pad size
(Cu area = 1.127 in sq. [1 oz] including traces)
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.412 in sq.)
3
DPAK
CASE 369C
STYLE 2
4
1
THERMAL RESISTANCE RATINGS
Parameter
G
4
Drain
AYWW
T20
P06LG
Drain−to−Source Voltage
Symbol
2
1
3
Drain
Gate
Source
4
Drain
AYWW
T20
P06LG
Parameter
2
3
IPAK/DPAK
CASE 369D
STYLE 2
20P06L
A
Y
WW
G
1 2 3
Gate Drain Source
Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2019 − Rev. 8
1
Publication Order Number:
NTD20P06L/D
NTD20P06L, NTDV20P06L
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−60
−74
V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
−64
mV/°C
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VGS = 0 V,
VDS = −60 V
TJ = 25°C
−1.0
TJ = 150°C
−10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = −250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Gate Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
Drain−to−Source On−Voltage
VDS(on)
−1.0
−1.5
−2.0
3.1
VGS = −5.0 V, ID = −7.5 A
0.130
VGS = −5.0 V, ID = −15 A
0.143
VDS = −10 V, ID = −7.5 A
11
VGS = −5.0 V,
ID = −7.5 A
V
mV/°C
0.150
W
S
TJ = 25°C
−1.2
TJ = 150°C
−1.9
V
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
1190
207
300
66
120
15
26
nC
11
20
ns
90
180
28
50
70
135
TJ = 25°C
1.5
2.5
TJ = 150°C
1.3
VGS = 0 V, f = 1 MHz, VDS = −25 V
QG(TOT)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
pF
740
VGS = −5.0 V, VDS = −48 V,
ID = −18 A
4.0
7.0
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
VGS = −5.0 V, VDD = −30 V,
ID = −15 A, RG = 9.1 W
tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, IS = −15 A
60
VGS = 0 V, dIS/dt = 100 A/ms,
IS = −12 A
QRR
V
ns
39
21
0.13
nC
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%
4. Switching characteristics are independent of operating junction temperatures
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
2
NTD20P06L, NTDV20P06L
TYPICAL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
30
VGS = −5 V
VGS = −8 V
25
VGS = −7 V
VGS = −4.5 V
20
VGS = −4 V
15
VGS = −3.5 V
10
VGS = −3 V
5
TJ = 25°C
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(W)
TJ = −55°C
VGS = −5.5 V
VGS = −9 V
1
2
3
4
5
6
7
8
9
20
10
VDS w 10 V
0
3
4
5
6
7
Figure 2. Transfer Characteristics
VGS = −5 V
TJ = 125°C
0.25
0.2
0.15
TJ = 25°C
0.1
TJ = −55°C
0.05
0
5
10
15
20
25
0.15
VGS = −10 V
0.1
0.075
0.05
0.025
0
0
−ID, LEAKAGE (nA)
0.6
3
6
9
12
15
18
−ID, DRAIN CURRENT (A)
VGS = 0 V
ID = −7.5 A
VGS = −5 V
0.8
24
VGS = −5 V
0.125
10000
1
21
0.2
0.175
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1.2
9
TJ = 25°C
Figure 3. On−Resistance versus Drain Current
and Temperature
1.4
8
0.25
0.225
30
−ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
Figure 1. On−Region Characteristics
0.3
1.6
1
−VDS, GATE−TO−SOURCE VOLTAGE (V)
0.35
1.8
TJ = 125°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.4
0
TJ = 25°C
10
0.5
0.45
30
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
35
40
VGS = −6 V
VGS = −10 V
−ID, DRAIN CURRENT (A)
40
0.4
TJ = 150°C
1000
TJ = 125°C
100
10
0.2
0
−50
1
−25
0
25
50
75
100
125
150
5
10
15
20
25
30
35
40
45
50
55
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
60
NTD20P06L, NTDV20P06L
C, CAPACITANCE (pF)
2400
2200
2000
VDS = 0 V
1800
1600
1400
Ciss
1200
Crss
1000
800
TJ = 25°C
VGS = 0 V
Ciss
600
Coss
400
200
0
Crss
−10
−5
0
−VGS
5
10
15
20
25
−VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (V)
Figure 7. Capacitance Variation
60
ID = −15 A
TJ = 25°C
50
6.25
5.0
40
QG
VDS
3.75
Qgs
VGS
QGD
30
2.5
20
1.25
10
0
0
0
4
8
12
VDS, DRAIN−TO−SOURCE VOLTAGE
(V)
−VGS, GATE−TO−SOURCE VOLTAGE
(V)
7.5
16
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge
1000
20
−IS, SOURCE CURRENT (A)
t, TIME (nS)
VDD = −30 V
ID = −15 A
VGS = −5 V
tR
100
tF
td(off)
10
td(on)
1
1
10
Rg, GATE RESISTANCE (W)
100
VGS = 0 V
TJ = 25°C
15
10
5
0
0
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
0.25
0.5
0.75
1
1.25
1.5
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
1.75
Figure 10. Diode Forward Voltage versus
Current
www.onsemi.com
4
−ID, DRAIN CURRENT (A)
1000
VGS = −15 V
Single Pulse
TC = 25°C
100
100
10
1
10 ms
1
dc
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1
1
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
NTD20P06L, NTDV20P06L
350
ID = −15 A
300
250
200
150
100
50
0
100
25
Rqjc(°C/W), EFFECTIVE TRANSIENT THERMAL RESPONSE
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
10
D = 0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
0.01
0.000001
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
t, TIME (s)
Figure 13. Thermal Response
ORDERING INFORMATION
Device
Shipping†
Package
NTD20P06LG
NTD20P06LT4G
NTDV20P06LT4G
75 Units / Rail
2500 / Tape & Reel
DPAK
(Pb−Free)
2500 / Tape & Reel
NTDV20P06LT4G−VF01
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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