NTHS5443

NTHS5443 Power MOSFET −20 V, −4.9 A, P−Channel ChipFETt Features • • • • Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb−Free Package is Available http://onsemi.com V(BR)DSS −20 V RDS(on) TYP 56 mW @ −4.5 S ID MAX −4.9 A Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Drain−Source Voltage Gate−Source Voltage Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C Pulsed Drain Current Continuous Source Current (Note 1) Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C Operating Junction and Storage Temperature Range Symbol VDS VGS ID −4.9 −3.5 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 °C D8 D7 D6 S5 −4.9 "15 −3.6 −3.6 −2.6 A A W 1 5 secs Steady State Unit V G −20 "12 D V A P−Channel MOSFET 8 ChipFET CASE 1206A STYLE 1 PIN CONNECTIONS 1D 2D 3D 4G 1 2 3 4 MARKING DIAGRAM 8 7 6 5 A4 MG G −55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). A4 = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTHS5443T1 NTHS5443T1G Package ChipFET ChipFET (Pb−Free) Shipping† 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 1 July, 2005 − Rev. 6 Publication Order Number: NTHS5443T1/D NTHS5443 THERMAL CHARACTERISTICS Characteristic Maximum Junction−to−Ambient (Note 2) tv5s Steady State Maximum Junction−to−Foot (Drain) Steady State Symbol RqJA Typ 40 80 15 Max 50 95 20 °C/W Unit °C/W RqJF ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Static Gate Threshold Voltage Gate−Body Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS VDS = VGS, ID = −250 mA VDS = 0 V, VGS = "12 V VDS = −16 V, VGS = 0 V VDS = −16 V, VGS = 0 V, TJ = 85°C On−State Drain Current (Note 3) Drain−Source On−State Resistance (Note 3) ID(on) rDS(on) VDS v −5.0 V, VGS = −4.5 V VGS = −4.5 V, ID = −3.6 A VGS = −3.6 V, ID = −3.3 A VGS = −2.5 V, ID = −2.7 A Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) Dynamic (Note 4) Total Gate Charge Gate−Source Charge Gate−Drain Charge Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Source−Drain Reverse Recovery Time QG QGS QGD td(on) tr td(off) tf trr IF = −1.1 A, di/dt = 100 A/ms VDD = −10 V, RL = 10 W ID ^ −1.0 A, VGEN = −4.5 V, RG = 6 W VDS = −10 V, VGS = −4.5 V, ID = −3.6 A 7.5 0.9 2.2 8.5 14 38 30 30 12 2.8 − 13 21 57 45 60 ns ns nC gfs VSD VDS = −10 V, ID = −3.6 A IS = −1.1 A, VGS = 0 V −15 0.056 0.065 0.095 10 −0.8 −1.2 0.065 0.074 0.110 S V −0.6 "100 −1.0 −5.0 A W V nA mA Symbol Test Condition Min Typ Max Unit 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 NTHS5443 TYPICAL ELECTRICAL CHARACTERISTICS 10 −ID, DRAIN CURRENT (AMPS) −6 V −2.4 V 10 −2.2 V −ID, DRAIN CURRENT (AMPS) TJ = 25°C −2 V 8 VDS ≥ −10 V −5 V 8 −4 V 6 −3.4 V −2.8 V −2.6 V 6 4 −1.8 V −1.6 V VGS = −1.4 V 4 125°C 25°C TJ = −55°C 0.5 1 1.5 2 2.5 3 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 2 0 0 0.5 1 1.5 2 2 0 2.5 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.2 ID = −3.6 A TJ = 25°C 0.15 0.08 Figure 2. Transfer Characteristics TJ = 25°C 0.06 VGS = −4.5 V VGS = −6 V 0.04 0.1 0.05 0 0 1 2 3 4 5 6 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.02 1 2 3 4 5 6 7 8 9 10 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = −3.6 A VGS = −4.5 V −IDSS , LEAKAGE (nA) 1.4 1000 10,000 Figure 4. On−Resistance versus Drain Current and Gate Voltage VGS = 0 V TJ = 150°C 1.2 1 100 TJ = 100°C 0.8 0.6 −50 10 −25 0 25 50 75 100 125 150 0 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTHS5443 TYPICAL ELECTRICAL CHARACTERISTICS −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1800 VDS = 0 V 1500 C, CAPACITANCE (pF) 1200 900 600 300 0 10 5 −VGS −VDS 0 5 10 15 20 Coss Crss Ciss VGS = 0 V TJ = 25°C 5 QG 11 10 9 8 3 QGS 2 QGD ID = −3.6 A TJ = 25°C QGD/QGS = 3.1 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 QG, TOTAL GATE CHARGE (nC) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4 1 0 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 1000 VDD = −10 V ID = −1.0 V VGS = −4.5 V t, TIME (ns) 100 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge td(off) tf 10 tr td(on) 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1 Duty Cycle = 0.5 0.2 0.1 0.05 0.02 Single Pulse 0.0001 0.001 0.01 0.1 1 10 100 1000 t2 DUTY CYCLE, D = t1/t2 t1 PDM PER UNIT BASE = RqJA = 80°C/W TJM − TA = PDMZqJA(t) SURFACE MOUNTED 0.1 0.01 SQUARE WAVE PULSE DURATION (sec) Figure 10. Normalized Thermal Transient Impedance, Junction−to−Ambient http://onsemi.com 4 NTHS5443 PACKAGE DIMENSIONS ChipFETt CASE 1206A−03 ISSUE G D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MIN 1.00 0.25 0.10 2.95 1.55 MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.014 0.011 0.071 0.075 5° NOM MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c A 0.05 (0.002) 0.017 0.079 STYLE 1: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. DRAIN SOLDERING FOOTPRINT* 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 2.032 0.08 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches 0.178 0.007 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches Basic Styles 1 and 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 NTHS5443 ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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