NTHS5443T1G

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Other names and brands may be claimed as the property of others. NTHS5443 MOSFET – Power, P-Channel, ChipFET -20 V, -4.9 A Features • • • • Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX −20 V 56 mW @ −4.5 −4.9 A Applications S • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards G MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol 5 secs Steady State Unit Drain−Source Voltage VDS −20 V Gate−Source Voltage VGS "12 V Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C Pulsed Drain Current ID IDM IS Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C PD TJ, Tstg −4.9 2.5 1.3 1 A "15 −3.6 A W 1.3 0.7 −55 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). ChipFET CASE 1206A STYLE 1 8 −3.6 −2.6 PIN CONNECTIONS MARKING DIAGRAM D 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 S 5 4 G 4 A4 MG G Operating Junction and Storage Temperature Range P−Channel MOSFET A −4.9 −3.5 Continuous Source Current (Note 1) D 6 5 A4 = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Package Shipping† NTHS5443T1 ChipFET 3000/Tape & Reel NTHS5443T1G ChipFET (Pb−Free) 3000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 May, 2019 − Rev. 6 1 Publication Order Number: NTHS5443T1/D NTHS5443 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction−to−Ambient (Note 2) tv5s Steady State RqJA Maximum Junction−to−Foot (Drain) Steady State RqJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = −250 mA −0.6 Gate−Body Leakage IGSS VDS = 0 V, VGS = "12 V "100 nA Zero Gate Voltage Drain Current IDSS VDS = −16 V, VGS = 0 V −1.0 mA VDS = −16 V, VGS = 0 V, TJ = 85°C −5.0 Static Gate Threshold Voltage V On−State Drain Current (Note 3) ID(on) VDS v −5.0 V, VGS = −4.5 V Drain−Source On−State Resistance (Note 3) rDS(on) VGS = −4.5 V, ID = −3.6 A VGS = −3.6 V, ID = −3.3 A 0.056 0.065 0.065 0.074 VGS = −2.5 V, ID = −2.7 A 0.095 0.110 gfs VDS = −10 V, ID = −3.6 A 10 VSD IS = −1.1 A, VGS = 0 V −0.8 −1.2 V 7.5 12 nC 0.9 2.8 2.2 − 8.5 13 14 21 38 57 30 45 30 60 Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) −15 A W S Dynamic (Note 4) Total Gate Charge QG Gate−Source Charge QGS Gate−Drain Charge QGD Turn−On Delay Time td(on) Rise Time Turn−Off Delay Time tr td(off) Fall Time tf Source−Drain Reverse Recovery Time trr VDS = −10 V, VGS = −4.5 V, ID = −3.6 A VDD = −10 V, RL = 10 W ID ^ −1.0 A, VGEN = −4.5 V, RG = 6 W IF = −1.1 A, di/dt = 100 A/ms 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 ns ns NTHS5443 TYPICAL ELECTRICAL CHARACTERISTICS −6 V −ID, DRAIN CURRENT (AMPS) −5 V 8 −4 V 6 −2.4 V −2.2 V −3.4 V −2.8 V −2.6 V TJ = 25°C 10 −ID, DRAIN CURRENT (AMPS) 10 −2 V −1.8 V 4 −1.6 V 2 VGS = −1.4 V 0 0.5 1 1.5 2 2.5 3 25°C TJ = −55°C 1 1.5 2 2.5 3 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.1 0.05 0 2 1 4 3 6 5 0.08 TJ = 25°C 0.06 VGS = −4.5 V VGS = −6 V 0.04 0.02 1 2 3 4 5 6 7 8 9 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 10 10,000 ID = −3.6 A VGS = −4.5 V VGS = 0 V −IDSS , LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 125°C 2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.15 1.2 1 0.8 0.6 −50 4 0.5 ID = −3.6 A TJ = 25°C 1.4 6 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.2 0 8 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 VDS ≥ −10 V −25 0 25 50 75 100 125 150 TJ = 150°C 1000 100 TJ = 100°C 10 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 NTHS5443 Ciss C, CAPACITANCE (pF) 1500 VDS = 0 V VGS = 0 V TJ = 25°C 1200 Crss 900 600 Coss 300 0 10 5 5 0 −VGS −VDS 10 15 20 5 11 QG 10 9 4 8 7 3 6 QGS 5 QGD 2 4 ID = −3.6 A TJ = 25°C QGD/QGS = 3.1 1 0 0 1 2 3 4 5 6 7 QG, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 2 1 8 0 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1800 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 VDD = −10 V ID = −1.0 V VGS = −4.5 V t, TIME (ns) 100 td(off) tf tr 10 td(on) 1 1 10 100 RG, GATE RESISTANCE (OHMS) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 9. Resistive Switching Time Variation versus Gate Resistance 1 Duty Cycle = 0.5 0.2 0.1 0.01 0.1 PDM 0.05 t1 0.02 t2 DUTY CYCLE, D = t1/t2 Single Pulse 0.0001 0.001 0.01 0.1 1 10 PER UNIT BASE = RqJA = 80°C/W TJM - TA = PDMZqJA(t) SURFACE MOUNTED 100 SQUARE WAVE PULSE DURATION (sec) Figure 10. Normalized Thermal Transient Impedance, Junction−to−Ambient http://onsemi.com 4 1000 NTHS5443 PACKAGE DIMENSIONS ChipFETt CASE 1206A−03 ISSUE G D 8 7 q 6 L 5 HE 5 6 7 8 4 3 2 1 E 1 e1 2 3 4 e b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM DIM A b c D E e e1 L HE q c A 0.05 (0.002) MIN 1.00 0.25 0.10 2.95 1.55 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.014 0.011 0.071 0.075 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 STYLE 1: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. DRAIN SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 0.178 0.007 0.711 0.028 mm Ǔ ǒinches 0.66 0.026 Basic SCALE 20:1 Styles 1 and 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm Ǔ ǒinches NTHS5443 ChipFET is a trademark of Vishay Siliconix. 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