NTLJD4116NT1G

NTLJD4116N Power MOSFET Features 30 V, 4.6 A, mCoolt Dual N−Channel, 2x2 mm WDFN Package • WDFN Package Provides Exposed Drain Pad for Excellent Thermal • • • • • Conduction 2x2 mm Footprint Same as SC−88 Lowest RDS(on) Solution in 2x2 mm Package 1.5 V RDS(on) Rating for Operation at Low Voltage Gate Drive Logic Level Low Profile (< 0.8 mm) for Easy Fit in Thin Environments This is a Pb−Free Device V(BR)DSS http://onsemi.com RDS(on) MAX 70 mW @ 4.5 V 30 V 90 mW @ 2.5 V 125 mW @ 1.8 V 250 mW @ 1.5 V D 4.6 A ID MAX (Note 1) Applications • DC−DC Converters (Buck and Boost Circuits) • Low Side Load Switch • Optimized for Battery and Load Management Applications in • Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc. Level Shift for High Side Load Switch G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Steady State t≤5s Power Dissipation (Note 1) Steady State t≤5s Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current TA = 25°C Steady State TA = 85°C TA = 25°C PD IDM TJ, TSTG IS TL ID TA = 25°C TA = 85°C TA = 25°C PD TA = 25°C 2.3 2.5 1.8 0.71 20 −55 to 150 2.0 260 W A °C A °C G1 D2 A Symbol VDSS VGS ID Value 30 ±8.0 3.7 2.7 4.6 1.5 W Unit V V A 1 S N−CHANNEL MOSFET MARKING DIAGRAM WDFN6 CASE 506AN 1 2 JFMG G 3 6 5 4 JF = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS D1 S1 1 2 D2 3 4 S2 6 5 D1 G2 t p = 10 m s Operating Junction and Storage Temperature Source Current (Body Diode) (Note 2) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) (Top View) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. ORDERING INFORMATION Device NTLJD4116NT1G Package WDFN6 (Pb−Free) Shipping † 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 1 May, 2006 − Rev. 4 Publication Order Number: NTLJD4116N/D NTLJD4116N THERMAL RESISTANCE RATINGS Parameter SINGLE OPERATION (SELF−HEATED) Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 4) Junction−to−Ambient – t ≤ 5 s (Note 3) DUAL OPERATION (EQUALLY HEATED) Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 4) Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA RqJA RqJA 58 133 40 °C/W RqJA RqJA RqJA 83 177 54 °C/W Symbol Max Unit 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). http://onsemi.com 2 NTLJD4116N MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = 4.5, ID = 2.0 A VGS = 2.5, ID = 2.0 A VGS = 1.8, ID = 1.8 A VGS = 1.5, ID = 1.5 A Forward Transconductance gFS VDS = 5.0 V, ID = 2.0 A CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Gate Resistance SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) tf TJ = 25°C TJ = 125°C VGS = 4.5 V, VDD = 15 V, ID = 2.0 A, RG = 2.0 W 4.8 11.8 14.2 1.7 ns CISS COSS CRSS QG(TOT) QG(TH) QGS QGD RG VGS = 4.5 V, VDS = 15 V, ID = 2.0 A 427 VGS = 0 V, f = 1.0 MHz, VDS = 15 V 51 32 5.4 0.5 0.8 1.24 0.37 W 6.5 nC pF VGS = VDS, ID = 250 mA 0.4 0.7 2.8 47 56 88 133 4.5 70 90 125 250 S 1.0 V mV/°C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, ID = 250 mA ID = 250 mA, Ref to 25°C TJ = 25°C TJ = 85°C 30 18.1 1.0 10 100 nA V mV/°C mA Symbol Test Conditions Min Typ Max Unit VDS = 24 V, VGS = 0 V VDS = 0 V, VGS = ±8.0 V DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time VSD tRR ta tb QRR VGS = 0 V, dISD/dt = 100 A/ms, IS = 2.0 A VGS = 0 V, IS = 2.0 A 0.78 0.62 10.5 7.6 2.9 5.0 nC ns 1.2 V 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTLJD4116N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 5 ID, DRAIN CURRENT (AMPS) VGS = 1.7 V to 8 V TJ = 25°C ID, DRAIN CURRENT (AMPS) 1.6 V 4 1.5 V 6 VDS ≥ 10 V 4 3 2 1.4 V 1.3 V 1.2 V 2 TJ = 25°C TJ = 100°C 1 0 0 1 2 3 4 0 5 0 0.5 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = −55°C 1.5 2 2.5 3 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.07 VGS = 4.5 V 0.06 TJ = 100°C 0.14 0.13 0.12 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 1 2 VGS = 4.5 V 3 4 5 VGS = 2.5 V VGS = 1.8 V TJ = 25°C 0.05 TJ = 25°C 0.04 TJ = −55°C 0.03 0.02 1.0 1.5 2.0 2.5 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage 100,000 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 ID = 2 A VGS = 4.5 V 1.4 VGS = 0 V 10,000 TJ = 150°C 1000 TJ = 100°C 100 1.2 1.0 0.8 0.6 −50 IDSS, LEAKAGE (nA) −25 0 25 50 75 100 125 150 10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 NTLJD4116N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V 5 QT 4 VDS VGS 18 15 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 C, CAPACITANCE (pF) 800 600 Ciss 400 200 0 5 VGS 0 VDS 5 10 15 20 Crss Coss TJ = 25°C 12 3 9 2 QGS QGD 6 1 0 0 1 ID = 2.0 A TJ = 25°C 2 3 4 5 QG, TOTAL GATE CHARGE (nC) 6 3 0 25 30 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 1000 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 2.0 A VGS = 4.5 V t, TIME (ns) 100 td(off) tf tr 10 td(on) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 3 VGS = 0 V TJ = 150°C 2 TJ = 25°C TJ = 125°C 1 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0.3 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.9 Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 −ID, DRAIN CURRENT (AMPS) Figure 10. Diode Forward Voltage versus Current 10 TC = 25°C TJ = 150°C SINGLE PULSE 10 ms 100 ms 1 ms 1 10 ms *See Note 2 on Page 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc 0.1 0.01 1 10 100 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 NTLJD4116N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) EFFECTIVE TRANSIENT THERMAL RESISTANCE 1000 100 D = 0.5 0.2 0.1 *See Note 2 on Page 1 P(pk) D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 10 0.05 0.02 1 0.01 SINGLE PULSE 0.1 0.000001 0.00001 0.0001 0.001 t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.1 t, TIME (s) 1 10 100 1000 Figure 12. Thermal Response http://onsemi.com 6 NTLJD4116N PACKAGE DIMENSIONS WDFN6, 2x2 CASE 506AN−01 ISSUE B D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L J MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.77 2.00 BSC 0.90 1.10 0.65 BSC 0.25 REF 0.20 0.30 0.15 REF PIN ONE REFERENCE E 2X 0.10 C 2X 0.10 C 0.10 C 6X 0.08 C D2 6X L 1 3 6X K mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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ÍÍÍ ÍÍÍ ÍÍÍ A3 A1 D2 e 2X E2 6 4 A C SEATING PLANE 6X SOLDERMASK DEFINED MOUNTING FOOTPRINT* 2.30 6X 0.35 4X 0.43 1 0.65 PITCH b 6X 0.25 B 2X NOTE 3 6X J 0.10 C A 0.05 C BOTTOM VIEW 0.72 1.05 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTLJD4116N/D