NTLJS4159NT1G

NTLJS4159N Power MOSFET 30 V, 7.8 A, Single N−Channel, 2x2 mm WDFN Package Features • WDFN Package Provides Exposed Drain Pad for Excellent Thermal • • • • • Conduction 2x2 mm Footprint Same as SC−88 Lowest RDS(on) in 2x2 mm Package 1.8 V RDS(on) Rating for Operation at Low Voltage Logic Level Gate Drive Low Profile (< 0.8 mm) for Easy Fit in Thin Environments This is a Pb−Free Device www.onsemi.com RDS(on) MAX V(BR)DSS ID MAX (Note 1) 35 mW @ 4.5 V 30 V 7.8 A 45 mW @ 2.5 V 55 mW @ 1.8 V S Applications • DC−DC Conversion • Boost Circuits for LED Backlights • Optimized for Battery and Load Management Applications in G Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc. • Low Side Load Switch D N−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±8.0 V ID 6.0 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C 4.4 t≤5s TA = 25°C 7.8 Steady State t≤5s Continuous Drain Current (Note 2) PD TA = 25°C PD 0.70 W IDM 28 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) (Note 2) IS 3.0 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Pulsed Drain Current Steady State TA = 85°C TA = 25°C tp = 10 ms Operating Junction and Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. © Semiconductor Components Industries, LLC, 2006 August, 2016 − Rev. 5 1 MARKING DIAGRAM WDFN6 CASE 506AP 1 6 2 JBMG 5 G 3 4 PIN CONNECTIONS A 2.6 D JB = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 3.3 3.6 Power Dissipation (Note 2) Pin 1 W 1.92 ID TA = 25°C S D 1 D 2 G 3 D S 6 D 5 D 4 S (Top View) ORDERING INFORMATION Device Package Shipping† NTLJS4159NT1G WDFN6 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTLJS4159N/D NTLJS4159N THERMAL RESISTANCE RATINGS Symbol Max Junction−to−Ambient – Steady State (Note 3) Parameter RqJA 65 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 38 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 180 Unit °C/W 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min 30 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = 250 mA, Ref to 25°C Zero Gate Voltage Drain Current IDSS VDS = 24 V, VGS = 0 V Gate−to−Source Leakage Current V 20 mV/°C TJ = 25°C 1.0 TJ = 65°C 1.0 TJ = 85°C 5.0 IGSS VDS = 0 V, VGS = ±8.0 V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA Negative Gate Threshold Temperature Coefficient VGS(TH)/TJ ±100 mA nA ON CHARACTERISTICS (Note 5) Drain−to−Source On−Resistance RDS(on) Forward Transconductance gFS 0.4 0.7 1.0 3.18 V mV/°C VGS = 4.5, ID = 2.0 A 20.3 35 VGS = 2.5, ID = 2.0 A 25.8 45 VGS = 1.8, ID = 1.8 A 35.2 55 VDS = 16 V, ID = 2.0 A 5.3 S 1045 pF mW CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 0 V, f = 1.0 MHz, VDS = 15 V 115.5 45.3 Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 2.7 RG 3.65 W td(ON) 6.8 ns Gate Resistance 12.1 VGS = 4.5 V, VDS = 15 V, ID = 2.0 A 13 nC 1.2 1.9 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDD = 15 V, ID = 2.0 A, RG = 3.0 W tf 12.4 26 5.1 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage Reverse Recovery Time VSD TJ = 25°C 0.71 TJ = 125°C 0.58 tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 2.0 A 15 VGS = 0 V, dISD/dt = 100 A/ms, IS = 1.0 A QRR 9.0 www.onsemi.com 2 V 35 ns 6.0 7.0 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTLJS4159N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) TJ = 25°C 1.5 V 5 1.4 V 4 3 1.3 V 2 1.2 V 1 0 0.5 1 1.5 2 2.5 3 4 3.5 4.5 5 5.5 VDS ≥ 10 V 6 4 TJ = 25°C 2 TJ = 100°C 0 6 0 Figure 2. Transfer Characteristics TJ = 100°C 0.025 TJ = 25°C 0.02 TJ = −55°C 0.015 0.01 0.005 1.0 1.5 3.0 2.5 2.0 0.05 TJ = 25°C 0.04 VGS = 1.8 V 0.03 VGS = 2.5 V 0.02 VGS = 4.5 V 0.01 0 1 2 3 ID, DRAIN CURRENT (AMPS) 4 5 6 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage 100000 ID = 2 A VGS = 4.5 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 3 2.5 2 Figure 1. On−Region Characteristics VGS = 4.5 V 1.4 1.5 1 0.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.03 1.6 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 6 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 8 VGS = 1.6 V to 8 V ID, DRAIN CURRENT (AMPS) 7 1.2 1.0 VGS = 0 V 10000 TJ = 125°C 1000 TJ = 85°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 100 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage www.onsemi.com 3 20 NTLJS4159N C, CAPACITANCE (pF) VDS = 0 V VGS = 0 V TJ = 25°C 2400 1800 Ciss 1200 Crss 600 Coss 0 5 VGS 0 VDS 5 15 10 20 25 30 QT 4 3 1000 IS, SOURCE CURRENT (AMPS) td(off) 100 tf tr td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V TJ = 25°C 3 2 1 0.4 0.01 See Note 2 on Page 1 10 ms 100 ms 10 ms SINGLE PULSE TC = 25°C TJ = 150°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.5 0.6 0.7 0.8 Figure 10. Diode Forward Voltage versus Current 1 ms 0.1 0 16 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 1 4 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 8 12 4 8 QG, TOTAL GATE CHARGE (nC) 0 0 0.3 100 QGD ID = 3.0 A TJ = 25°C 4 I D, DRAIN CURRENT (AMPS) t, TIME (ns) QGS 1 0 16 12 2 Figure 7. Capacitance Variation VDD = 15 V ID = 3.0 A VGS = 4.5 V VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 20 5 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 3000 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) dc 10 1 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 4 NTLJS4159N EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 1000 100 D = 0.5 0.2 0.1 10 0.05 P(pk) 0.02 0.01 1 0.1 0.000001 See Note 2 on Page 1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 Figure 12. Thermal Response www.onsemi.com 5 1 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AP−01 ISSUE B DATE 26 APR 2006 SCALE 4:1 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 1. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4. 2. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG. A B ÍÍÍ ÍÍÍ ÍÍÍ E PIN ONE REFERENCE DIM A A1 A3 b b1 D D2 E E2 e K L L2 J J1 0.10 C 2X 2X 0.10 C A3 0.10 C A 7X 0.08 C A1 C D2 6X L GENERIC MARKING DIAGRAM* SEATING PLANE 4X 1 1 6 2 XX M 5 3 4 e L2 3 b1 XX = Specific Device Code M = Date Code 6X 0.10 C A E2 B *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.05 C NOTE 5 K 6 4 b J J1 SOLDERMASK DEFINED MOUNTING FOOTPRINT 6X 0.10 C A 0.05 C B NOTE 3 2.30 BOTTOM VIEW STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 0.51 0.61 2.00 BSC 1.00 1.20 2.00 BSC 1.10 1.30 0.65 BSC 0.15 REF 0.20 0.30 0.20 0.30 0.27 REF 0.65 REF STYLE 2: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR 1.10 6X 6X 0.35 0.43 1 0.60 1.25 0.35 0.34 0.65 PITCH DOCUMENT NUMBER: DESCRIPTION: 98AON20860D 6 PIN WDFN 2X2, 0.65P 0.66 DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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