NTLUS3192PZ
Advance Information
Power MOSFET
−20 V, −4.2 A, mCoolt Single P−Channel,
ESD, 1.6x1.6x0.55 mm UDFN Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
•
•
•
•
•
Conduction
Low Profile UDFN 1.6 x 1.6 x 0.55 mm for Board Space Saving
Lowest RDS(on) in 1.6x1.6 Package
ESD Protected
This is a Halide Free Device
This is a Pb−Free Device
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MOSFET
V(BR)DSS
−20 V
Applications
• High Side Load Switch
• PA Switch and Battery Switch
• Optimized for Power Management Applications for Portable
RDS(on) MAX
ID MAX
85 mW @ −4.5 V
−3.0 A
115 mW @ −2.5 V
−1.5 A
160 mW @ −1.8 V
−0.5 A
250 mW @ −1.5 V
−0.2 A
S
Products, such as Cell Phones, PMP, DSC, GPS, and others
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Units
Drain-to-Source Voltage
VDSS
−20
V
Gate-to-Source Voltage
VGS
±8.0
V
Continuous Drain
Current (Note 1)
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Power Dissipation
(Note 1)
Steady
State
TA = 25°C
t≤5s
Continuous Drain
Current (Note 2)
Steady
State
ID
TA = 85°C
A
−3.4
MARKING
DIAGRAM
−2.4
−4.2
PD
TA = 25°C
TA = 25°C
1
−2.2
0.6
W
Pulsed Drain Current
tp = 10 ms
IDM
−17
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 2)
IS
−1.0
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
ESD
1000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
1
AA MG
G
(Note: Microdot may be in either location)
−1.6
PD
May, 2009 − Rev. P3
1
AA = Specific Device Code
M = Date Code
G = Pb−Free Package
TA = 25°C
© Semiconductor Components Industries, LLC, 2009
UDFN6
CASE 517AU
mCOOLt
A
Power Dissipation (Note 2)
Gate-to-Source ESD Rating
(HBM) per JESD22−A114F
6
W
1.5
2.3
ID
TA = 85°C
Operating Junction and Storage
Temperature
D
P−Channel MOSFET
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTLUS3192PZ/D
NTLUS3192PZ
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Units
Junction-to-Ambient – Steady State (Note 3)
RθJA
85
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
55
RθJA
200
Junction-to-Ambient – Steady State min Pad (Note 4)
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
−20
Typ
Max
Units
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, ref to 25°C
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
IDSS
VGS = 0 V,
VDS = −20 V
V
14
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−10
IGSS
VDS = 0 V, VGS = ±8.0 V
VGS(TH)
VGS = VDS, ID = −250 mA
10
mA
mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
−0.4
VGS(TH)/TJ
RDS(on)
Forward Transconductance
−1.0
2.5
VGS = −4.5 V, ID = −3.0 A
gFS
65
V
mV/°C
85
mW
VGS = −2.5 V, ID = −1.5 A
90
115
VGS = −1.8 V, ID = −0.5 A
120
160
VGS = −1.5 V, ID = −0.2 A
160
250
VDS = −5.0 V, ID = −0.2 A
2.0
S
450
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
VGS = 0 V, f = 1 MHz,
VDS = −10 V
85
65
5.5
VGS = −4.5 V, VDS = −10 V;
ID = −3.0 A
8.5
nC
0.3
0.8
1.6
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
td(ON)
26
tr
69
Rise Time
Turn-Off Delay Time
td(OFF)
Fall Time
VGS = −4.5 V, VDD = −10 V,
ID = −3.0 A, RG = 1 W
tf
ns
225
200
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
3.
4.
5.
6.
VGS = 0 V,
IS = −1.0 A
TJ = 25°C
0.72
TJ = 85°C
0.7
11
VGS = 0 V, dISD/dt = 100 A/ms,
IS = −1.0 A
QRR
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2
V
ns
8.0
3.0
6.0
Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu.
Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
1.2
nC
NTLUS3192PZ
TYPICAL CHARACTERISTICS
20
−ID, DRAIN CURRENT (A)
−3.5 V
14
−2.5 V
12
10
−2.0 V
8
−1.8 V
6
−1.5 V
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4
0.175
0.150
ID = −3.0 A
0.125
ID = −0.2 A
1.5
2.0
2.5
3.0
3.5
4.0
−VGS, GATE VOLTAGE (V)
2
4.5
0.5
1.0
1.5
2.0
2.5
−1.5 V
0.225
TJ = 25°C
−1.8 V
0.200
3.0
−2.5 V
0.175
0.150
0.125
0.100
VGS = −4.5 V
0.075
0.050
0.025
0
0
2
4
6
8
10
12
14
16
18
20
−ID, DRAIN CURRENT (A)
100,000
VGS = −4.5 V
ID = −3.0 A
−IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
0
TJ = −55°C
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
1.4
TJ = 125°C
0.250
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
TJ = 25°C
3
Figure 2. Transfer Characteristics
TJ = 25°C
1.0
5
Figure 1. On−Region Characteristics
0.200
0.050
6
−VGS, GATE−TO−SOURCE VOLTAGE (V)
0.225
0.075
7
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.250
0.100
VDS ≤ −10 V
8
1
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
9
−4.0 V
16
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10
−3.0 V
VGS = −4.5 V
18
1.3
1.2
1.1
1.0
0.9
TJ = 150°C
10,000
TJ = 125°C
1000
TJ = 85°C
100
0.8
0.7
−50
−25
0
25
50
75
100
125
150
10
0
5
10
15
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
20
NTLUS3192PZ
VGS = 0 V
TJ = 25°C
f = 1 MHz
C, CAPACITANCE (pF)
600
Ciss
500
400
300
200
Coss
100
0
Crss
0
2
4
6
8
10
12
14
18
16
20
5
10
4
6
QGS
2
QGD
0
0
4
VDS = −10 V
TJ = 25°C
ID = −3.0 A
1
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
2
0
5.0 5.5
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
VGS = −4.5 V
VDD = −10 V
ID = −3.0 A
−IS, SOURCE CURRENT (A)
1000
t, TIME (ns)
8
3
Figure 7. Capacitance Variation
td(off)
tf
100
tr
td(on)
1
10
TJ = 150°C
TJ = 25°C
0.1
100
TJ = 125°C
1
TJ = −55°C
0.2
0.4
0.6
0.8
1.0
1.2
1.4
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
0.80
225
0.75
ID = −250 mA
200
0.70
175
POWER (W)
0.65
−VGS(th) (V)
VGS
VDS
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
12
QT
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
700
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
0.60
0.55
0.50
0.45
150
125
100
75
0.40
50
0.35
0.30
−50
25
−25
0
25
50
75
100
125
0
1.E−05
150
1.E−03
1.E−01
1.E+01
1.E+03
TJ, JUNCTION TEMPERATURE (°C)
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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4
NTLUS3192PZ
TYPICAL CHARACTERISTICS
−ID, DRAIN CURRENT (A)
100
VGS = −8 V
Single Pulse
TC = 25°C
10
10 ms
100 ms
1
1 ms
10 ms
0.1
0.01
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
dc
10
100
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
90
RqJA = 85°C/W
80
70
60
50
Duty Cycle = 0.5
40
30
20 0.2
0.05
0.02
0.01
10 0.1
0
1E−06
Single Pulse
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 14. FET Thermal Response
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS3192PZTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3192PZTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6 1.6x1.6, 0.5P
CASE 517AU−01
ISSUE O
6
DATE 16 OCT 2008
1
SCALE 4:1
A
B
D
2X
PIN ONE
REFERENCE
2X
0.10 C
ÉÉ
ÉÉ
E
DETAIL A
OPTIONAL
CONSTRUCTION
A
DETAIL B
0.05 C
(A3)
A1
0.05 C
A1
C
SIDE VIEW
F
3
1
DETAIL B
SEATING
PLANE
D2
DETAIL A
G
6X
XX MG
G
XX = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
b
D1
0.10 C A B
0.05 C
BOTTOM VIEW
NOTE 3
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
0.82
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
1.60 BSC
1.60 BSC
0.50 BSC
0.62
0.72
0.15
0.25
0.57
0.67
0.55 BSC
0.25 BSC
0.20
0.30
−−−
0.15
1
E2
0.10 C A B
4
A3
DIM
A
A1
A3
b
D
E
e
D1
D2
E2
F
G
L
L1
GENERIC
MARKING DIAGRAM*
L
6
MOLD CMPD
OPTIONAL
CONSTRUCTION
e
0.10 C A B
6X
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
NOTE 4
L1
L
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
0.16
0.43
0.68
2X
0.35
1.90
0.28
1
0.50 PITCH
6X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON35147E
UDFN6, 1.6X1.6, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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