NTMFD4901NF
MOSFET – Power, Dual,
N-Channel with Integrated
Schottky, SO8FL
30 V, High Side 18 A / Low Side 30 A
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Features
•
•
•
•
•
Co−Packaged Power Stage Solution to Minimize Board Space
Low Side MOSFET with Integrated Schottky
Minimized Parasitic Inductances
Optimized Devices to Reduce Power Losses
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V(BR)DSS
RDS(ON) MAX
Q1 Top FET
30 V
6.5 mW @ 10 V
18 A
10 mW @ 4.5 V
Q2 Bottom
FET
30 V
2.35 mW @ 10 V
30 A
3.5 mW @ 4.5 V
D1
Applications
• DC−DC Converters
• System Voltage Rails
• Point of Load
ID MAX
(2, 3, 4, 9)
(1) G1
S1/D2 (10)
(8) G2
S2 (5, 6, 7)
PIN CONNECTIONS
5 S2
D1 4
D1 3
9
D1
D1 2
6 S2
10
S1/D2
7 S2
8 G2
G1 1
(Bottom View)
MARKING
DIAGRAM
1
DFN8
CASE 506BX
4901NF
AYWZZ
1
4901NF
A
Y
W
ZZ
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 6
1
Publication Order Number:
NTMFD4901NF/D
NTMFD4901NF
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain−to−Source Voltage
Q1
Drain−to−Source Voltage
Q2
Gate−to−Source Voltage
Q1
Gate−to−Source Voltage
Q2
Continuous Drain Current RqJA (Note 1)
TA = 25°C
Q1
Symbol
Value
Unit
VDSS
30
V
VGS
±20
V
ID
13.5
TA = 85°C
TA = 25°C
9.7
Q2
23.4
TA = 85°C
TA = 25°C
Power Dissipation RqJA (Note 1)
16.9
Q1
PD
Q2
Continuous Drain Current RqJA ≤ 10 s (Note 1)
TA = 25°C
Q1
Steady
State
ID
TA = 25°C
30.3
TA = 25°C
Q1
PD
Q1
ID
TA = 25 °C
17.9
TA = 25°C
tp = 10 ms
Operating Junction and Storage Temperature
A
12.9
Q1
PD
Q2
Pulsed Drain Current
W
10.3
7.4
Q2
TA = 85°C
Power Dissipation RqJA (Note 2)
3.45
3.45
TA = 85°C
TA = 25°C
A
21.8
Q2
Continuous Drain Current RqJA (Note 2)
W
18.2
13.1
Q2
TA = 85°C
Power Dissipation RqJA ≤ 10 s (Note 1)
1.90
2.07
TA = 85°C
TA = 25°C
A
Q1
W
1.20
IDM
60
TJ, TSTG
−55 to +150
°C
IS
3.4
A
Q2
Q1
1.10
A
100
Q2
Source Current (Body Diode)
Q1
Q2
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche Energy (TJ = 25C, VDD
= 50 V, VGS = 10 V, IL = XX Apk, L = 0.1 mH, RG = 25 W)
4.9
dV/dt
6
V/ns
28.8
mJ
24 A
Q1
EAS
48 A
Q2
EAS
115
TL
260
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size of 100 mm2.
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2
NTMFD4901NF
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Junction−to−Ambient – Steady State (Note 3)
FET
Symbol
Value
Q1
RqJA
65.9
Q2
Junction−to−Ambient – Steady State (Note 4)
60.5
Q1
RqJA
113.2
Q2
Junction−to−Ambient – (t ≤ 10 s) (Note 3)
Unit
°C/W
104
Q1
RqJA
36.2
Q2
36.2
3. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size of 100 mm2.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
FET
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
Q1
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
VGS = 0 V, ID = 1 mA
30
Drain−to−Source Breakdown Voltage Temperature
Coefficient
Q1
Zero Gate Voltage Drain
Current
Q1
Typ
Max
Unit
OFF CHARACTERISTICS
Q2
Q2
V(BR)DSS
/ TJ
IDSS
Q2
Gate−to−Source Leakage
Current
Q1
mV /
°C
18
15
VGS = 0 V,
VDS = 24 V
TJ = 25°C
1
TJ = 125°C
10
TJ = 25°C
500
VGS = 0 V,
VDS = 24 V
IGSS
V
VGS = 0 V, VDS = ±20 V
±100
Q2
mA
nA
±100
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Q1
VGS(TH)
VGS = VDS, ID = 250 mA
Q2
Negative Threshold Temperature Coefficient
Q1
Drain−to−Source On Resistance
Q1
Q2
VGS(TH) /
TJ
RDS(on)
Q2
Forward Transconductance
Q1
gFS
1.2
2.2
1.2
2.2
mV /
°C
4.5
4.0
VGS = 10 V
ID = 10 A
5.2
6.5
VGS = 4.5 V
ID = 10 A
8.0
10
VGS = 10 V
ID = 20 A
1.9
2.35
VGS = 4.5 V
ID = 20 A
2.8
3.5
VDS = 1.5 V, ID = 10 A
Q2
28
45
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
V
mW
S
NTMFD4901NF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
FET
Symbol
Test Condition
Min
Typ
Max
Unit
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Capacitance
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1150
CISS
COSS
2950
VGS = 0 V, f = 1 MHz, VDS = 15 V
1100
pF
105
CRSS
82
9.7
QG(TOT)
20
1.1
QG(TH)
VGS = 4.5 V, VDS = 15 V; ID = 10 A
QGS
2.7
3.3
nC
7.3
3.7
QGD
QG(TOT)
360
5.3
VGS = 10 V, VDS = 15 V; ID = 10 A
19.1
42.7
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Q1
Q2
Q1
tr
Q2
Q1
Q2
9.0
td(ON)
14
15
VGS = 4.5 V, VDS = 15 V,
ID = 10 A, RG = 3.0 W
td(OFF)
Q1
14
ns
25
4.0
tf
Q2
16
7.0
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
6.0
td(ON)
tr
10
14
VGS = 10 V, VDS = 15 V,
ID = 10 A, RG = 3.0 W
td(OFF)
15
17
32
3.0
tf
5.0
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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4
ns
NTMFD4901NF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
FET
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
0.75
1.0
TJ = 125°C
0.62
TJ = 25°C
0.45
TJ = 125°C
0.37
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
VGS = 0 V,
IS = 3 A
Q1
Forward Voltage
VSD
Q2
Reverse Recovery Time
Q1
Q2
Q1
Charge Time
Q2
Q1
Discharge Time
Q2
Reverse Recovery Charge
Q1
Q2
VGS = 0 V,
IS = 2 A
0.70
V
23
tRR
40
12
ta
VGS = 0 V, dIS/dt = 100 A/ms, IS = 3 A
tb
21
ns
11
19
12
QRR
40
nC
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance
Gate Inductance
Gate Resistance
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
0.38
LS
0.65
0.054
LD
TA = 25°C
LG
0.007
1.5
1.5
0.8
RG
0.8
nH
nH
nH
W
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping†
NTMFD4901NFT1G
DFN8
(Pb−Free)
1500 / Tape & Reel
NTMFD4901NFT3G
DFN8
(Pb−Free)
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q1
3.8 V
ID, DRAIN CURRENT (A)
35
50
3.6 V
3.4 V
4.5 V
10 V
30
TJ = 25°C
25
20
3.0 V
10
2.8 V
5
VGS = 2.4 V
0
1
2
3
4
TJ = 125°C
25
20
15
10
TJ = 25°C
TJ = −55°C
0
1
2
3
4
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
3
4
5
6
7
8
9
10
0.010
T = 25°C
0.009
0.008
VGS = 4.5 V
0.007
0.006
0.005
VGS = 10 V
0.004
0.003
0
5
10
15
20
25
30
35
40
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Resistance
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
10,000
ID = 10 A
VGS = 10 V
TJ = 150°C
IDSS, LEAKAGE (nA)
1.8
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
30
0
5
ID = 10 A
TJ = 25°C
2
35
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.020
0.002
40
5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
3.2 V
15
VDS ≥ 5 V
45
ID, DRAIN CURRENT (A)
40
1.4
1.2
1.0
1,000
TJ = 125°C
100
0.8
0.6
−50
−25
0
25
50
75
100
125
150
10
VGS = 0 V
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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6
30
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q1
Ciss
1200
1000
800
Coss
600
400
Crss
200
0
5
10
15
20
25
30
QT
9
8
7
6
5
4
Qgs
Qgd
3
2
1
0
ID = 10 A
TJ = 25°C
0
2
4
6
8
10
12
14
18
16
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
20
10
1000
VGS = 10 V
VDD = 15 V
ID = 10 A
9
td(off)
100
tr
10
td(on)
tf
1
11
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IS, SOURCE CURRENT (A)
0
t, TIME (ns)
TJ = 25°C
VGS = 0 V
VGS = 0 V
8
7
6
5
4
3
TJ = 25°C
2
1
1
10
0
0.0
100
0.1
0.3
0.2
0.4
0.5
0.6
0.7
0.8
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
C, CAPACITANCE (pF)
1400
VGS, GATE−TO−SOURCE VOLTAGE (V)
1600
100
10 ms
10
100 ms
1 ms
10 ms
0 V ≤ VGS ≤ 20 V
SINGLE PULSE
TA = 25°C
Single Pulse
1
0.1
0.01
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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7
100
0.9
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q1
100
Thermal Resistance, RqJA
(°C/W)
D = 0.5
10
1
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
t, TIME (s)
Figure 12. Thermal Response
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8
1
10
100
1000
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q2
3.4 V
45
3.0 V
35
30
25
2.8 V
20
15
10
5
VGS = 2.4 V
0
1
2
3
4
5
TJ = 125°C
30
20
TJ = 25°C
10
TJ = −55°C
0.005
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
3
10
3.5
0.0035
0.0030
VGS = 4.5 V
0.0025
0.0020
VGS = 10 V
0.0015
0.0010
0
5
10
15
20
25
30
35
40
45
50
ID, DRAIN CURRENT (A)
Figure 16. On−Resistance vs. Drain Current
and Gate Voltage
1E−2
ID = 20 A
VGS = 10 V
TJ = 150°C
IDSS, LEAKAGE (A)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2.5
0.0040
Figure 15. On−Resistance vs. Gate−to−Source
Resistance
1.4
1.2
1.0
1E−3
TJ = 125°C
1E−4
1E−5
0.8
0.6
−50
2
Figure 14. Transfer Characteristics
0.010
1.6
1.5
1
Figure 13. On−Region Characteristics
0.015
1.8
0.5
0
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 10 A
TJ = 25°C
2
40
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.020
0
VDS ≥ 5 V
50
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
60
TJ = 25°C
4.5 V
10 V
40
ID, DRAIN CURRENT (A)
3.2 V
ID, DRAIN CURRENT (A)
50
TJ = 25°C
−25
0
25
50
75
100
125
150
1E−6
0
5
10
15
VGS = 0 V
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 17. On−Resistance Variation with
Temperature
Figure 18. Drain−to−Source Leakage Current
vs. Voltage
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9
30
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q2
Ciss
3000
2500
2000
Coss
1500
1000
500
Crss
0
5
10
15
20
25
30
11
QT
10
9
8
7
6
5
4
Qgd
Qgs
3
2
1
0
ID = 10 A
TJ = 25°C
0
5
10
15
20
25
30
35
45
40
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 19. Capacitance Variation
Figure 20. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
1000
VGS = 10 V
VDD = 15 V
ID = 10 A
9
IS, SOURCE CURRENT (A)
0
t, TIME (ns)
TJ = 25°C
VGS = 0 V
td(off)
100
tr
td(on)
10
tf
8
VGS = 0 V
TJ = 25°C
7
6
5
4
3
2
1
1
1
10
100
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 21. Resistive Switching Time Variation
vs. Gate Resistance
Figure 22. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
C, CAPACITANCE (pF)
3500
VGS, GATE−TO−SOURCE VOLTAGE (V)
4000
100
10 ms
10
100 ms
1 ms
10 ms
0 V ≤ VGS ≤ 20 V
SINGLE PULSE
TA = 25°C
Single Pulse
1
0.1
0.01
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 23. Maximum Rated Forward Biased
Safe Operating Area
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10
100
NTMFD4901NF
TYPICAL CHARACTERISTICS − Q2
100
Thermal Resistance, RqJA
(°C/W)
D = 0.5
10
1
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
t, TIME (s)
Figure 24. Thermal Response
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11
1
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual−Asymmetrical)
CASE 506BX
ISSUE D
DATE 24 JUN 2014
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE
TERMINALS.
5. DIMENSIONS b AND L ARE MEASURED AT THE PACKAGE SURFACE
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
7. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
2X
0.20 C
D
A
D1
8
ÉÉ
ÉÉ
1
2
2X
0.20 C
5
E1 E
4X
h
NOTE 6
PIN ONE
IDENTIFIER
B
NOTE 6
7
6
3
c
4
DIM
A
A1
b
b1
c
D
D1
D2
E
E1
E2
E3
e
h
k
k1
k2
L
A1
NOTE 7
TOP VIEW
0.10 C
DETAIL A
A
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
e
DETAIL B
e/2
1
SEATING
PLANE
4
8X
E3
k
k1
k2
E2
8
0.10
REF
DETAIL B
5
D2
BOTTOM VIEW
8X
MILLIMETERS
MAX
MIN
1.10
0.90
0.00
0.05
0.41
0.61
0.41
0.61
0.23
0.33
5.00
5.30
4.50
5.10
3.50
4.22
6.00
6.30
5.50
6.10
2.27
2.67
0.82
1.22
1.27 BSC
−−−
12 _
0.39
0.59
0.56
0.76
0.73
0.93
0.35
0.55
GENERIC
MARKING DIAGRAM*
1
XXXXXX
AYWZZ
XXXXXX= Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
b
0.10
C A B
0.05
C
NOTE 3
*This information is generic. Please refer
to device data sheet for actual part
marking.
6X b1
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
L
PACKAGE
OUTLINE
STYLE 1:
PIN 1. GATE 1
2. DRAIN 1
3. DRAIN 1
4. DRAIN 1
5. SOURCE 2
6. SOURCE 2
7. SOURCE 2
8. GATE 2
9. DRAIN 1
10. SOURCE 1/DRAIN 2
5.35
8X
0.69
8X
0.64
1.97
2.68
6.45
2.33
1.22
4X
1.27
PITCH
0.69
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON54291E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL−ASYMMETRICAL)
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ON Semiconductor and
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