NTMS4503NR2

NTMS4503N Power MOSFET 28 V, 14 A, N−Channel, SOIC−8 Features • • • • Low RDS(on) High Power and Current Handling Capability Low Gate Charge Pb−Free Package is Available http://onsemi.com V(BR)DSS Applications • • • • 7.0 mW @ 10 V 28 V DC/DC Converters Motor Drives Synchronous Rectifier − POL Buck Low−Side ID Max (Note 1) RDS(on) Typ 14 A 8.8 mW @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 28 V Gate−to−Source Voltage − Continuous VGS $20 V Rating Drain Current Continuous @ TA = 25°C (Note 1) Continuous @ TA = 25°C (Note 2) Continuous @ TA = 25°C (Note 3) Single Pulse (tp = 10 ms) Total Power Dissipation TA = 25°C (Note 1) TA = 25°C (Note 2) TA = 25°C (Note 3) Operating and Storage Temperature Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 V, VGS = 10 V, IL = 12.2 A, L = 1.0 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds ID IDM 14 12 9.0 40 MARKING DIAGRAM & PIN ASSIGNMENT D W 8 −55 to 150 °C SOIC−8 CASE 751 STYLE 12 75 mJ 2.5 1.66 0.93 EAS TL 260 °C Symbol Value Unit Thermal Resistance Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Junction−to−Ambient (Note 3) March, 2007 − Rev. 2 D D 4503N AYWW G G 1 S 4503N A Y WW G S S G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) RqJA °C/W 50 75 135 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using minimum recommended pad size (Cu area 0.412 in sq), t < 10 s. 2. Surface−mounted on FR4 board using 1″ pad size (Cu area 1.127 in sq) steady state. 3. Surface−mounted on FR4 board using minimum recommended pad size (Cu area 0.412 in sq), steady state. © Semiconductor Components Industries, LLC, 2007 D 8 1 THERMAL RESISTANCE RATINGS Rating S A PD TJ, Tstg G 1 ORDERING INFORMATION Device Package Shipping† NTMS4503NR2 SOIC−8 2500/Tape & Reel SOIC−8 (Pb−Free) 2500/Tape & Reel NTMS4503NR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTMS4503N/D NTMS4503N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 28 31 − V Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ − − 22 − mV/°C TJ = 25°C − − 1.0 mA TJ = 100°C − − 25 − $100 OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VGS = 0 V, VDS = 24 V IGSS VDS = 0 V, VGS = $20 V − nA ON CHARACTERISTICS (Note 4) VGS(TH) VGS = VDS, ID = 250 mA 1.0 − 2.0 V VGS(TH)/TJ − − −5.0 − mV/°C RDS(on) VGS = 10 V, ID = 14 A − 7.0 8.0 mW VGS = 4.5 V, ID = 10 A − 8.8 9.8 VDS = 10 V, ID = 14 A − 30 − S pF Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance gFS CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS − 2400 − Output Capacitance COSS − 1000 − Reverse Transfer Capacitance CRSS − 375 − Total Gate Charge QG(TOT) − 23 − Threshold Gate Charge QG(TH) − 2.0 − − 5.0 − − 12 − − 18.5 − − 70 − − 21 − − 23 − TJ = 25°C − 0.82 1.2 TJ = 125°C − 0.65 − − 48 − − 23 − − 25 − − 25 − Gate−to−Source Charge QGS Gate−to−Drain Charge QGD VGS = 0 V, f = 1.0 MHz, VDS = 16 V VGS = 4.5 V, VDS = 16 V, ID = 10 A nC SWITCHING CHARACTERISTICS, VGS = V (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) VGS = 4.5 V, VDD = 16 V, ID = 10 A, RG = 2.0 W tf ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time Ta Discharge Time Tb Reverse Recovery Charge VGS = 0 V, IS = 10 A VGS = 0 V, dISD/dt = 100 A/ms, IS = 14 A QRR 4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 V ns nC NTMS4503N TYPICAL PERFORMANCE CURVES 35 TJ = 25°C 3V VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) VGS = 10, 3.6, 3.2 V 25 2.8 V 20 15 2.6 V 10 5 2.4 V 2.2 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 1 2 3 4 6 5 7 8 9 30 25 20 15 10 5 TJ = −55°C TJ = 100°C 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 3 3.5 1.5 2 2.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.011 ID = 14 A TJ = 25°C 0.010 0.009 0.008 0.007 0.006 1 9 7 11 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 3 5 4 0.012 TJ = 25°C 0.011 0.010 VGS = 4.5 V 0.009 0.008 VGS = 10 V 0.007 0.006 0.005 0.004 4 8 12 16 20 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Gate Voltage Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.6 10000 VGS = 0 V ID = 14 A VGS = 4.5 V TJ = 150°C 1.4 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = 25°C 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 30 1000 1.2 1 100 TJ = 100°C 0.8 0.6 −50 10 −25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTMS4503N C, CAPACITANCE (pF) 3600 TJ = 25°C Ciss 3000 2400 Crss Ciss 1800 1200 Coss 600 0 10 VDS = 0 V 5 VGS = 0 V 0 VGS 5 Crss 10 15 5 20 QT 4 QGS 12 QGD 8 4 1 ID = 10 A TJ = 25°C 0 0 20 5 VDS 15 10 20 QG, TOTAL GATE CHARGE (nC) 0 25 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 10 VDD = 16 V ID = 10 A VGS = 4.5 V IS, SOURCE CURRENT (AMPS) 1000 t, TIME (ns) VGS 2 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) tr tf td(off) td(on) 100 10 1 16 VDS 3 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4200 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation vs. Gate Resistance VGS = 0 V TJ = 25°C 9 8 7 6 5 4 3 2 1 0 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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