NTMS4916N

NTMS4916N Power MOSFET Features 30 V, 11.6 A, N−Channel, SO−8 • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Optimized for 5 V, 12 V Gate Drives These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com V(BR)DSS 30 V RDS(ON) MAX 9 mW @ 10 V 12 mW @ 4.5 V N−Channel ID MAX 11.6 A Applications • DC−DC Converters • Printers MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJA, t v 10 s (Note 1) Power Dissipation RqJA, t v 10 s(Note 1) Pulsed Drain Current Steady State Steady State Steady State Steady State Steady State TA = 25°C TA = 70°C TA = 25°C TA = 25°C TA = 70°C TA = 25°C TA = 25°C TA = 70°C TA = 25°C PD IDM TJ, Tstg IS EAS PD ID PD ID Symbol VDSS VGS ID Value 30 ±20 9.4 7.5 1.30 7.8 6.2 0.89 11.6 9.3 1.98 145 −55 to 150 2.5 40.5 W A °C A mJ W A W Unit V V A D G S A MARKING DIAGRAM/ PIN ASSIGNMENT 1 SO−8 CASE 751 STYLE 12 Source Source Source Gate 1 4916N AYWWG G Top View 8 Drain Drain Drain Drain TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 9 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 4916N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION TL 260 °C Device NTMS4916NR2G Package SO−8 (Pb−Free) Shipping† 2500/Tape & Reel Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – t v 10 s (Note 1) Junction−to−Foot (Drain) Junction−to−Ambient – Steady State (Note 2) Symbol RqJA RqJA RqJF RqJA Value 96 63 24.5 141 Unit °C/W †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. Surfacemounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surfacemounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 0 1 Publication Order Number: NTMS4916N/D NTMS4916N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) gFS Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) td(on) tr td(off) tf VSD tRR ta tb QRR LS LD LG RG TA = 25°C VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A TJ = 25°C TJ = 125°C VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W VGS = 10 V, VDS = 15 V, ID = 7.5 A VGS = 4.5 V, VDS = 15 V, ID = 7.5 A VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 10 V, ID = 12 A VGS = 4.5 V, ID = 10 A Forward Transconductance VDS = 1.5 V, ID = 7.5 A CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Total Gate Charge 1376 401 205 15 2.44 4 6.5 28 nC nC pF TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 30 16 1.0 10 ±100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit VGS = 0 V, VDS = 30 V Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VDS = 0 V, VGS = ±20 V VGS = VDS, ID = 250 mA 1.0 1.7 5 6.75 9.0 23 2.5 V mV/°C 9.0 12 mW S SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time 9.4 7.4 32 15.6 ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VGS = 0 V, IS = 2.0 A 0.740 0.570 30.7 14.3 16.4 20 nC ns 1.0 V Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance 0.66 0.2 1.5 0.77 nH W 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTMS4916N TYPICAL PERFORMANCE CURVES 25 20 15 10 5 0 2.2 V 3.0 V 2.6 V 2.5 V 2.4 V 2.3 V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 1.5 2 50 VDS ≥ 10 V ID, DRAIN CURRENT (A) 40 30 20 10 TJ = 125°C TJ = 25°C TJ = −55°C 2.5 3 3.5 4 4.5 10V 7V 4V TJ = 25°C 5V 2.8 V ID, DRAIN CURRENT (A) VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.030 0.025 0.020 0.015 0.010 0.005 0.000 TJ = 25°C ID = 12 A 0.01 TJ = 25°C 0.009 0.008 0.007 0.006 0.005 2 4 6 8 10 12 14 16 18 20 22 ID, DRAIN CURRENT (A) VGS = 10 V VGS = 4.5 V 3 4 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.70 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 −50 −25 0 25 50 75 100 125 150 10 ID = 12 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 10000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C 100 TJ = 100°C 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NTMS4916N TYPICAL PERFORMANCE CURVES 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 10 QT 8 6 4 2 0 QGS Q2 QGD Q1 ID = 7.5 A VGS = 10 V TJ = 25°C 0 5 10 15 20 25 QG, TOTAL GATE CHARGE (nC) VDS TJ = 25°C VGS = 0 V Ciss Coss Crss 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (V) 30 30 Figure 7. Capacitance Variation 1000 IS, SOURCE CURRENT (A) VDD = 15 V ID = 1 A VGS = 10 V t, TIME (ns) 100 td(off) tf tr td(on) 2 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C 1.5 1 10 0.5 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.5 0.55 0.6 0.65 0.7 0.75 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 0.8 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1000 100 10 1 0.1 0.01 0.01 10 ms SINGLE PULSE TC = 25°C 10 ms 100 ms 1 ms EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) 45 40 35 30 25 20 15 10 5 0 Figure 10. Diode Forward Voltage vs. Current ID = 9 A ID, DRAIN CURRENT (A) RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) dc 100 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) NTMS4916N PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. 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