NTMS5P02R2SG

NTMS5P02, NVMS5P02 MOSFET – Power, Single, P-Channel, Enhancement Mode, SOIC-8 -5.4 A, -20 V http://onsemi.com Features • High Density Power MOSFET with Ultra Low RDS(on) • • • • • • • VDSS Providing Higher Efficiency Miniature SOIC−8 Surface Mount Package − Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Drain−to−Source Avalanche Energy Specified Mounting Information for the SOIC−8 Package is Provided These Devices are Pb−Free and are RoHS Compliant NVMS Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable −20 V ID MAX 26 mW @ −4.5 V −5.4 A Single P−Channel D G S Applications MARKING DIAGRAM & PIN ASSIGNMENT • Power Management in Portable and Battery−Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones RDS(ON) TYP 8 1 8 D D E5P02x AYWW G G SOIC−8 CASE 751 STYLE 13 1 NC S E5P02 x A Y WW G D D S G = Specific Device Code = Blank or S = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NTMS5P02R2G SOIC−8 2500 / Tape & Reel (Pb−Free) NVMS5P02R2G SOIC−8 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D © Semiconductor Components Industries, LLC, 2012 June, 2019 − Rev. 3 1 Publication Order Number: NTMS5P02R2/D NTMS5P02, NVMS5P02 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS −20 V Drain−to−Gate Voltage (RGS = 1.0 mW) VDGR −20 V Gate−to−Source Voltage − Continuous VGS ±10 V Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 50 2.5 −7.05 −5.62 1.2 −4.85 −28 °C/W W A A W A A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 85 1.47 −5.40 −4.30 0.7 −3.72 −20 °C/W W A A W A A Thermal Resistance − Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4) RqJA PD ID ID PD ID IDM 159 0.79 −3.95 −3.15 0.38 −2.75 −12 °C/W W A A W A A Operating and Storage Temperature Range TJ, Tstg −55 to +150 °C EAS 360 mJ TL 260 °C Rating Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −20 Vdc, VGS = −5.0 Vdc, Peak IL = −8.5 Apk, L = 10 mH, RG = 25 W) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds. 2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state. 3. Minimum FR−4 or G−10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. http://onsemi.com 2 NTMS5P02, NVMS5P02 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 5) Symbol Characteristic Min Typ Max Unit −20 − − −15 − − − − − − − −0.2 −1.0 −10 − − − −100 − − 100 −0.65 − −0.9 2.9 −1.25 − − − 0.026 0.037 0.033 0.048 gFS − 15 − Mhos Ciss − 1375 1900 pF Coss − 510 900 Crss − 200 380 td(on) − 18 35 OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = −16 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = −16 Vdc, VGS = 0 Vdc, TJ = 125°C) (VDS = −20 Vdc, VGS = 0 Vdc, TJ = 25°C) IDSS Gate−Body Leakage Current (VGS = −10 Vdc, VDS = 0 Vdc) IGSS Gate−Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = −4.5 Vdc, ID = −5.4 Adc) (VGS = −2.5 Vdc, ID = −2.7 Adc) RDS(on) Forward Transconductance (VDS = −9.0 Vdc, ID = −5.4 Adc) Vdc mV/°C W DYNAMIC CHARACTERISTICS Input Capacitance (VDS = −16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6 & 7) Turn−On Delay Time (VDD = −16 Vdc, ID = −1.0 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = −16 Vdc, ID = −5.4 Adc, VGS = −4.5 Vdc, RG = 6.0 W) Rise Time Turn−Off Delay Time Fall Time Total Gate Charge (VDS = −16 Vdc, VGS = −4.5 Vdc, ID = −5.4 Adc) Gate−Source Charge Gate−Drain Charge ns tr − 25 50 td(off) − 70 125 tf − 55 100 td(on) − 22 − tr − 70 − td(off) − 65 − tf − 90 − Qtot − 20 35 Qgs − 4.0 − Qgd − 7.0 − VSD − − −0.95 −0.72 −1.25 − Vdc trr − 40 75 ns ta − 20 − tb − 20 − QRR − 0.03 − ns nC BODY−DRAIN DIODE RATINGS (Note 6) Diode Forward On−Voltage (IS = −5.4 Adc, VGS = 0 V) (IS = −5.4 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = −5.4 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 3 mC NTMS5P02, NVMS5P02 −8 V −2.3 V −4.5 V −3.7 V −3.1 V 10 8 −2.7 V −2.5 V 6 12 TJ = 25°C −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 12 −2.1 V −1.9 V 4 −1.7 V 2 0 VGS = −1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS ≥ −10 V 10 8 6 4 25°C 1 ID = −5.4 A TJ = 25°C 0.06 0.04 0.02 2 4 6 8 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.08 0 TJ = 25°C VGS = −2.5 V 0.04 VGS = −2.7 V 0.03 VGS = −4.5 V 0.02 0.01 2 4 8 10 6 −ID, DRAIN CURRENT (AMPS) 12 Figure 4. On-Resistance versus Drain Current and Gate Voltage 10,000 1.6 VGS = 0 V ID = −5.4 A VGS = −4.5 V 1.2 1 0.8 0.6 −50 3 0.05 Figure 3. On−Resistance versus Gate−To−Source Voltage 1.4 2.5 1.5 2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0 TJ = −55°C 2 0 2 100°C −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) TJ = 150°C 1000 TJ = 125°C 100 150 2 Figure 5. On−Resistance Variation with Temperature 4 8 14 16 18 6 10 12 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 4 C, CAPACITANCE (pF) 4000 VGS = 0 V Ciss TJ = 25°C 3000 Crss 2000 Ciss 1000 0 Coss Crss 10 5 0 5 10 15 20 −VGS −VDS 5 20 QT 4 −VGS −VDS 3 Q1 16 12 Q2 8 2 ID = −5.4 A TJ = 25°C 1 0 4 0 8 12 16 20 4 24 0 Qg, TOTAL GATE CHARGE (nC) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V −VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTMS5P02, NVMS5P02 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation t, TIME (ns) VDD = −16 V ID = −5.4 A VGS = −4.5 V −IS, SOURCE CURRENT (AMPS) 1000 td(off) tf tr 100 td(on) 10 1 10 5 4 3 2 1 0 100 VGS = 0 V TJ = 25°C 0.2 RG, GATE RESISTANCE (OHMS) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current DRAIN−TO−SOURCE DIODE CHARACTERISTICS ID , DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25°C 1 ms 10 di/dt IS 10 ms trr 1 0.1 ta RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 1 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) tb TIME 0.25 IS tp dc 10 100 IS VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Diode Reverse Recovery Waveform http://onsemi.com 5 NTMS5P02, NVMS5P02 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 0.01 0.001 D = 0.5 0.2 0.1 0.05 Normalized to qja at 10s. 0.02 0.01 Chip 0.0163 W 0.0652 W 0.1988 W 0.0307 F 0.1668 F 0.5541 F 0.6411 W 1.9437 F 0.9502 W 72.416 F SINGLE PULSE 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 t, TIME (s) Figure 13. Thermal Response http://onsemi.com 6 1.0E+01 1.0E+02 Ambient 1.0E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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