DATA SHEET
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Switching Regulator Automotive Buck
1
DFN8
CASE 506BY
1.2 A, 2 MHz
NCV890100
MARKING DIAGRAMS
The NCV890100 is a fixed−frequency, monolithic, Buck switching
regulator intended for Automotive, battery−connected applications
that must operate with up to a 36 V input supply. The regulator is
suitable for systems with low noise and small form factor
requirements often encountered in automotive driver information
systems. The NCV890100 is capable of converting the typical 4.5 V to
18 V automotive input voltage range to outputs as low as 3.3 V at a
constant switching frequency above the sensitive AM band,
eliminating the need for costly filters and EMI countermeasures. The
NCV890100 also provides several protection features expected in
Automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor − forming a
space−efficient switching regulator solution.
•
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Features
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•
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•
•
•
•
•
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V8901
00G
ALYWG
G
Internal N−Channel Power Switch
Low VIN Operation Down to 4.5 V
High VIN Operation to 36 V
Withstands Load Dump to 40 V
2 MHz Free−running Switching Frequency
Logic Level Enable Input Can be Directly Tied to Battery
1.4 A (min) Cycle−by−Cycle Peak Current Limit
Short Circuit Protection Enhanced by Frequency Foldback
±1.75% Output Voltage Tolerance
Output Voltage Adjustable Down to 0.8 V
1.4 Millisecond Internal Soft−Start
Thermal Shutdown (TSD)
Low Shutdown Current
Wettable Flanks DFN
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Applications
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Audio
Infotainment
Safety − Vision Systems
Instrumentation
© Semiconductor Components Industries, LLC, 2014
November, 2021 − Rev. 4
1
Publication Order Number:
NCV890100/D
NCV890100
CDRV
DBST
NCV890100
VIN
CIN
EN
L1
1 VIN
SW 8
2 DRV
BST 7
3 GND
FB 6
CBST
DFW
RFB1
COMP 5
4 EN
VOUT
COUT
RFB2
RCOMP
CCOMP
Figure 1. Typical Application
CDRV
VIN
VIN
CIN
DBST
SW
3V
Reg
L1
CBST
DRV
BST
PWM
LOGIC
ON OFF
Oscillator
1.2 A
+
+S
GND
+
−
TSD
+
−
Soft−Start
RESET
FB
+
COMP
VOLTAGES
MONITORS
Enable
RCOMP
EN
CCOMP
Figure 2. NCV890100 Block Diagram
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2
DFW
COUT
NCV890100
MAXIMUM RATINGS
Rating
Symbol
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
Min Voltage SW − 20ns
Value
Unit
−0.3 to 40
V
40
V
−0.7 to 40
V
−3.0
V
Min/Max Voltage BST
−0.3 to 40
Min/Max Voltage BST to SW
−0.3 to 3.6
V
Min/Max Voltage on EN
−0.3 to 40
V
Min/Max Voltage COMP
−0.3 to 2
V
Min/Max Voltage FB
−0.3 to 18
V
Min/Max Voltage DRV
−0.3 to 3.6
V
Thermal Resistance, 3x3 DFN Junction−to−Ambient*
RqJA
50
°C/W
Thermal Resistance, SOIC−8 EP Junction−to−Ambient*
RqJA
40
°C/W
Storage Temperature range
−55 to +150
°C
TJ
−40 to +150
°C
VESD
2.0
200
>1.0
kV
V
kV
Moisture Sensitivity, DFN8
MSL
Level 1
Moisture Sensitivity, SOIC−8 EP
MSL
Level 2
Operating Junction Temperature Range
ESD withstand Voltage
Human Body Model
Machine Model
Charge Device Model
Peak Reflow Soldering Temperature
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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3
NCV890100
VIN
1
8
SW
DRV
2
7
BST
GND
3
6
FB
EN
4
5
COMP
(Top View)
Figure 3. Pin Connections
PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
1
VIN
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
2
DRV
Output voltage to provide a regulated voltage to the Power Switch gate driver.
3
GND
Battery return, and output voltage ground reference.
4
EN
5
COMP
6
FB
Feedback input pin to program output voltage, and detect pre−charged or shorted output conditions.
7
BST
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for optimum
switch RDS(on) and highest efficiency.
8
SW
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Exposed
Pad
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
Error Amplifier output, for tailoring transient response with external compensation components.
Connect to Pin 3 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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4
NCV890100
ELECTRICAL CHARACTERISTICS (VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid
for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
Quiescent Current, shutdown
IqSD
Quiescent Current, enabled
Min
Typ
Max
Unit
VIN = 13.2 V, VEN = 0 V, TJ = 25°C
5
mA
IqEN
VIN = 13.2 V
3
mA
UVLO Start Threshold
VUVLSTT
VIN rising
4.1
4.5
V
UVLO Stop Threshold
VUVLSTP
VIN falling
3.9
4.4
V
UVLO Hysteresis
VUVLOHY
0.1
0.2
V
Logic Low
VENLO
0.8
Logic High
VENHI
QUIESCENT CURRENT
UNDERVOLTAGE LOCKOUT − VIN (UVLO)
ENABLE (EN)
Input Current
IEN
8
tSS
0.8
V
2
V
30
mA
1.4
2.0
ms
0.8
0.814
V
1
mA
SOFT−START (SS)
Soft−Start Completion Time
VOLTAGE REFERENCE
FB Pin Voltage during regulation
VFBR
COMP shorted to FB
0.786
IFBBIAS
VFB = 0.8 V
0.25
gm
VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
0.6
0.3
ERROR AMPLIFIER
FB Bias Current
Transconductance
gm(HV)
Output Resistance
COMP Source Current Limit
ROUT
1
0.5
1.5
0.75
1.4
ISOURCE
VFB = 0.63 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
75
40
COMP Sink Current Limit
ISINK
VFB = 0.97 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V
75
40
Minimum COMP voltage
VCMPMIN
VFB = 0.97 V
0.2
FSW
FSW(HV)
4.5 < VIN < 18 V
20 V < VIN < 28 V
1.8
0.9
mmho
MW
mA
mA
0.7
V
2.2
1.1
MHz
OSCILLATOR
Frequency
2.0
1.0
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
VIN rising
VIN falling
VFLDUP
VFLDDN
Frequency Foldback Hysteresis
VFLDHY
VFB = 0.63 V
18.4
18
0.2
20
19.8
0.3
V
0.4
V
1.3
0.6
A/ms
SLOPE COMPENSATION
Ramp Slope (Note 1)
(With respect to switch current)
Sramp
Sramp(HV)
4.5 < VIN < 18 V
20 V < VIN < 28 V
1. Not tested in production. Limits are guaranteed by design.
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5
0.7
0.25
NCV890100
ELECTRICAL CHARACTERISTICS (VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid
for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
ON Resistance
RDSON
Leakage current VIN to SW
Min
Typ
Max
Unit
VBST = VSW + 3.0 V
650
mW
ILKSW
VEN = 0 V, VSW = 0, VIN = 18 V
10
mA
Minimum ON Time
tONMIN
Measured at SW pin
70
ns
Minimum OFF Time
tOFFMIN
Measured at SW pin
At FSW = 2 MHz (normal)
At FSW = 500 kHz (max duty cycle)
POWER SWITCH
45
ns
30
30
50
70
1.4
1.55
1.7
A
400
200
24
500
250
32
600
300
40
kHz
VDRV
3.1
3.3
3.5
V
DRV POR Start Threshold
VDRVSTT
2.7
2.9
3.05
V
DRV POR Stop Threshold
VDRVSTP
2.5
2.8
3.0
V
45
mA
50
mV
PEAK CURRENT LIMIT
Current Limit Threshold
ILIM
SHORT CIRCUIT FREQUENCY FOLDBACK
Lowest Foldback Frequency
Lowest Foldback Frequency − High Vin
Hiccup Mode
FSWAF
FSWAFHV
FSWHIC
VFB = 0 V, 4.5 V < VIN < 18 V
VFB = 0 V, 20 V < VIN < 28 V
VFB = 0 V
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
DRV Current Limit
IDRVLIM
VDRV = 0 V
16
OUTPUT PRECHARGE DETECTOR
VSSEN
20
Activation Temperature (Note 1)
TSD
150
190
°C
Hysteresis (Note 1)
THYS
5
20
°C
Threshold Voltage
35
THERMAL SHUTDOWN
1. Not tested in production. Limits are guaranteed by design.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCV890100
VIN = 13.2 V
7
6
5
4
3
2
1
0
−50
−25
0
25
50
75
100
125
IqEN. ENABLED QUIESCENT CURRENT
(mA)
8
150
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
−50
25
50
75
100
125
Figure 5. Enabled Quiescent Current vs.
Junction Temperature
4.5
4.4
4.3
4.2
4.1
4.0
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
−50
−25
VFBR. FB REGULATION VOLTAGE (V)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0
25
50
75
100
125
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
Figure 7. UVLO Stop Threshold vs. Junction
Temperature
2.4
−25
150
4.6
Figure 6. UVLO Start Threshold vs. Junction
Temperature
tSS. SOFT−START DURATION (ms)
0
Figure 4. Shutdown Quiescent Current vs.
Junction Temperature
4.6
0.6
−50
−25
TJ. JUNCTION TEMPERATURE (°C)
4.7
3.9
−50
2.6
TJ. JUNCTION TEMPERATURE (°C)
VUVLSTP. UVLO STOP THRESHOLD (V)
VUVLSTT. UVLO START THRESHOLD (V)
IqSD. SHUTDOWN QUIESCENT CURRENT
(mA)
TYPICAL CHARACTERISTICS CURVES
150
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
TJ. JUNCTION TEMPERATURE (°C)
Figure 8. Soft−Start Duration vs. Junction
Temperature
Figure 9. FB Regulation Voltage vs. Junction
Temperature
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7
150
NCV890100
TYPICAL CHARACTERISTICS CURVES
100
ISOURCE. ERROR AMPLIFIER
SOURCING CURRENT (mA)
gm. ERROR AMPLIFIER
TRANSCONDUCTANCE (mS)
1.4
1.2
1.0
VIN = 4.5 V
0.8
0.6
VIN = 28 V
0.4
0.2
−50
−25
0
25
50
75
100
125
90
VIN = 4.5 V
80
70
60
50
VIN = 28 V
40
30
20
−50
150
−25
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
FSW. OSCILLATOR FREQENCY (MHz)
ISINK. ERROR AMPLIFIER SINKING
CURRENT (mA)
90
VIN = 4.5 V
70
60
50
VIN = 28 V
40
30
20
−50
−25
0
25
50
75
100
75
100
125
150
125
150
VIN = 13.2 V
2.0
1.8
1.6
1.4
1.2
VIN = 28 V
1.0
0.8
−50
−25
0
25
50
75
100
125
150
TJ. JUNCTION TEMPERATURE (°C)
Figure 12. Error Amplifier Max Sinking Current
vs. Junction Temperature
Figure 13. Oscillator Frequency vs. Junction
Temperature
19.6
900
19.4
19.2
RDS(on). POWER SWITCH ON
RESISTANCE (mW)
VFLDUP. VFLDDN, FREQ. FOLDBACK
THRESHOLD (V)
50
2.2
TJ. JUNCTION TEMPERATURE (°C)
VFLDUP
19.0
VFLDDN
18.8
18.6
18.4
18.2
−50
25
Figure 11. Error Amplifier Max Sourcing
Current vs. Junction Temperature
100
80
0
TJ. JUNCTION TEMPERATURE (°C)
TJ. JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
800
700
600
500
400
300
200
100
0
−50
Figure 14. Rising Frequency Foldback
Threshold vs. Junction Temperature
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 15. Power Switch RDS(on) vs. Junction
Temperature
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8
15 0
NCV890100
80
75
75
70
tOFFMIN. MINIMUM TIME (ns)
tONMIN. MINIMUM TIME (ns)
TYPICAL CHARACTERISTICS CURVES
70
65
60
55
50
45
40
−50
−25
0
25
50
75
100
125
65
60
55
50
45
40
35
−50
150
−25
TJ. JUNCTION TEMPERATURE (°C)
Figure 16. Minimum On Time vs. Junction
Temperature
FSWAF. FOLDBACK MODE
SWITCHING FREQUENCY (kHz)
ILIM. MINIMUM TIME (ns)
1.60
1.55
1.50
1.45
75
100
125
150
−25
0
25
50
75
100
125
VIN = 4.5 V
550
500
450
400
350
300
VIN = 28 V
250
200
−50
150
−25
TJ. JUNCTION TEMPERATURE (°C)
0
25
50
75
100
125
150
TJ. JUNCTION TEMPERATURE (°C)
Figure 18. Current Limit Threshold vs.
Junction Temperature
Figure 19. Short−Circuit Foldback Frequency
vs. Junction Temperature
40
3.50
38
3.45
VDRV. DRV VOLTAGE (V)
FSWHC. HICCUP MODE FREUQNCY
(kHz)
50
600
1.65
36
34
32
30
28
3.40
3.35
IDRV = 0 mA
3.30
IDRV = 16 mA
3.25
3.20
3.15
26
24
−50
25
Figure 17. Minimum Off Time vs. Junction
Temperature
1.70
1.40
−50
0
TJ. JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
3.10
−50
150
TJ. JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 20. Hiccup Mode Switching Frequency
vs. Junction Temperature
Figure 21. DRV Voltage vs. Junction
Temperature
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9
150
NCV890100
TYPICAL CHARACTERISTICS CURVES
IDRVLIM. DRV CURRENT LIMIT (mA)
30
3.0
2.9
VDRVSTT
2.8
VDRVSTP
2.7
2.6
2.5
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
150
29
28
27
26
25
24
23
22
21
−50
Figure 22. DRV Reset Threshold vs. Junction
Temperature
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 23. DRV Current Limit vs. Junction
Temperature
55
VSSEN. OUTPUT PRECHARGE
DETECTOR THRESHOLD (V)
VDRVSTT. VDRVSTP, DRV RESET
THRESHOLDS (V)
3.1
50
45
40
35
30
25
20
−50
−25
0
25
50
75
100
125
TJ. JUNCTION TEMPERATURE (°C)
Figure 24. Output Precharge Detector
Threshold vs. Junction Temperature
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10
150
150
NCV890100
GENERAL INFORMATION
INPUT VOLTAGE
SLOPE COMPENSATION
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft−start circuit
if there is insufficient voltage for proper regulation. The
NCV890100 can regulate a 3.3 V output with input voltages
above 4.5 V and a 5.0 V output with an input above 6.5 V.
The NCV890100 withstands input voltages up to 40 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
factor of 2 when the input voltage exceeds the VIN
Frequency Foldback threshold VFLDUP (see Figure 25).
Frequency reduction is automatically terminated when the
input voltage drops back below the VIN Frequency Foldback
threshold VFLDDN.
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 mH.
SHORT CIRCUIT FREQUENCY FOLDBACK
During severe output overloads or short circuits, the
NCV890100 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz, the regulator
enters an auto−recovery burst mode that further reduces the
dissipated power.
Fsw
(MHz)
2
CURRENT LIMITING
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 26 shows − for a
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV890100 can deliver to a load.
1
4
18 20
36
VIN (V)
1.4
MINIMUM CURRENT LIMIT (A)
Figure 25. NCV890100 Switching Frequency
Reduction at High Input Voltage
ENABLE
The NCV890100 is designed to accept either a logic level
signal or battery voltage as an Enable signal. EN low induces
a ’sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of mA typically (IqSD) by
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft−start of the
switching regulator output.
1.3
1.1
(5 VOUT)
1.0
0.9
0.8
0.7
0.6
SOFT−START
(3.3 VOUT)
1.2
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation.
Figure 26. NCV890100 Load Current Capability
with 4.7 mH Inductor
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11
NCV890100
BOOTSTRAP
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890100 skips switching
cycles to ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
Practically, this means that the NCV890100 needs a
minimum load to operate correctly. Figure 27 shows the
minimum current requirements for different input and
output voltages.
At the DRV pin an internal regulator provides a
ground−referenced voltage to an external capacitor (CDRV),
to allow fast recharge of the external bootstrap capacitor
(CBST) used to supply power to the power switch gate driver.
If the voltage at the DRV pin goes below the DRV UVLO
Threshold VDRVSTP, switching is inhibited and the
Soft−start circuit is reset, until the DRV pin voltage goes
back up above VDRVSTT.
16
MINIMUM OUTPUT CURRENT (mA)
MINIMUM OUTPUT CURRENT (mA)
50
40
L = 2.2 mH
30
20
L = 4.7 mH
10
0
4.2
5.2
6.2
7.2
8.2
9.2
8
6
4
L = 2.2 mH
2
0
4.2
4.7
5.2
5.7
6.2
Minimum Load 5 V Out
Minimum Load 3.3 V Out
6.7
50
MINIMUM OUTPUT CURRENT (mA)
MINIMUM OUTPUT CURRENT (mA)
L = 4.7 mH
10
INPUT VOLTAGE (V)
18
16
14
12
10
L = 2.2 mH
8
L = 4.7 mH
4
2
0
12
INPUT VOLTAGE (V)
20
6
14
4.2
4.7
5.2
5.7
6.2
6.7
7.2
45
40
L = 2.2 mH
35
30
25
20
L = 4.7 mH
15
10
5
0
4.2
6.2
8.2
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Minimum Load 3.7 V Out
Minimum Load 5.5 V Out
Figure 27. Minimum Load Current with Different Input and Output Voltages
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12
10.2
7.2
NCV890100
OUTPUT PRECHARGE DETECTION
EXPOSED PAD
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
bootstrap capacitor (CBST). If the FB pin is higher than
VSSEN, restart is delayed until the output has discharged.
Figure 28 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise−free operation.
DESIGN METHODOLOGY
The NCV890100 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890100 page
that helps with the calculation.
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
EN
Time
FB
C OUT min +
VSSEN
DI L
8 @ DV OUT @ F SW
With
Time
− DIL the inductor ripple current:
SW
ǒ
V OUT @ 1 *
DI L +
Figure 28. Output Voltage Detection
(eq. 1)
Time
V
Ǔ
OUT
V
IN
(eq. 2)
L @ F SW
− DVOUT the desired voltage ripple.
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed RESRmax:
THERMAL SHUTDOWN
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
R ESR max +
DV OUT @ L @ F SW
ǒ
V OUT 1 *
V
Ǔ
OUT
V
IN
(eq. 3)
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890100 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (tOFFmin) to periodically re−fuel
the bootstrap capacitor CBST. This imposes a maximum duty
ratio DMAX = 1 − tOFFmin.FSW(min), with the switching
frequency being folded back down to FSW(min) = 500 kHz to
keep regulating at the lowest input voltage possible.
The drop due to the on−state resistance is simply the
voltage drop across the Switch resistance RDSON at the
given output current: VSWdrop = IOUT.RDSon.
Which leads to the maximum output voltage in low Vin
condition: VOUT = DMAX.VIN(min) − VSWdrop
I OUTac +
DI L
2 Ǹ3
(eq. 4)
Typically, with the recommended 4.7 mH inductor, two
ceramic capacitors of 10 mF each in parallel give very good
results.
Freewheeling diode:
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some margin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
NCV890100, ILIM.
The power dissipated in the diode is PDloss:
ǒ
P Dloss + I OUT @ 1 *
www.onsemi.com
13
Ǔ
V OUT
V IN
@ V F ) I DRMS @ R D (eq. 5)
NCV890100
with:
− IOUT the average (dc) output current
− VF the forward voltage of the diode
− IDRMS the RMS current in the diode:
I DRMS +
Ǹ
ǒ
(1 * D) I OUT 2 )
DI L
12
Ǔ
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
2
(eq. 6)
− RD the dynamic resistance of the diode (extracted from
the V/I curve of the diode in its datasheet).
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
Error Amplifier and Loop Transfer Function
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
Figure 29 shows the error amplifier with the
compensation components and the voltage feedback divider.
Input capacitor:
The input capacitor must sustain the RMS input ripple
current IINac:
I INac +
DI L
2
ǸD3
(eq. 7)
VOUT
RFB1
VCOMP
VFB
V
RCOMP
RFB2
Cp
gm * V
RO
CCOMP
Vref
Figure 29. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
RFB2
Gdivider(s) +
RFB1 ) RFB2
s
1 ) wz
Gerr amp(s) + gm @ Ro @
1) s
1) s
wpl
wph
ǒ
Ǔǒ
Ǔ
(eq. 8)
wz +
1
RCOMP @ CCOMP
wpl +
1
Ro @ CCOMP
wph +
1
RCOMP @ Cp
(eq. 10)
(eq. 11)
(eq. 12)
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
The power stage transfer function (from Vcomp to output)
is shown below:
(eq. 9)
s
1 ) wz
1
(eq. 13)
Gps(s) + Rload @
@
s @ Fh(s)
Ri
1 ) Rload@Tsw @ [Mc @ (1 * D) * 0.5] 1 ) wp
L
www.onsemi.com
14
wp +
1
Resr @ Cout
wp +
Mc @ (1 * D) * 0.5
1
(eq. 15)
)
L @ Cout @ Fsw
Rload @ Cout
(eq. 14)
NCV890100
where
Mc + 1 ) Se
Sn
(eq. 16)
Sn + Vin * Vout @ Ri
L
(eq. 17)
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Design of the Compensation Network
Ri represents the equivalent sensing resistor which has a
value of 0.29 W, Se is the compensation slope which is
291.9 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling effect from the
current loop which has two poles at one half of the switching
frequency:
1
2
s
) s
1)
wn@Qp wn 2
wn + p @ Fsw
Fh(s) +
Qp +
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890100 page that helps with the calculation.
The design steps will be introduced through an example.
Example:
Vin = 15.5 V, Vout = 3.3 V, Rload = 2.75 W, Iout = 1.2 A,
L = 4.7 mH, Cout = 20 mF (Resr = 7 mW)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
From the specification, the power stage transfer function can
be plotted as below:
(eq. 18)
1
p @ [Mc @ (1 * D) * 0.5]
(eq. 19)
The total loop transfer function is the product of power
stage and feedback compensation network.
(dB)
Gloop(s) + Gdivider(s) @ Gerr amp(s) @ Gps(s) (eq. 20)
20‧ log⎣ Gps ⎣f ( m )
⎦
90
180
45
90
0
0
− 45
− 90
100
arg(Gps (f m ))‧
180
p
− 90
3
4
1⋅ 10
− 180
6
1⋅ 10
5
1⋅ 10
1⋅ 10
fm
(Hz)
Figure 30. Power Stage Bode Plots
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −8 dB (0.398) from
calculation. Then the gain of the feedback compensation
network must be 8 dB. Next is to decide the locations of one
zero and one pole of the compensator. The zero is to provide
phase boost at the crossover frequency and the pole is to
reject the noise of high frequency. In this example, a zero is
placed at 1/10 of the crossover frequency and a pole is placed
at 1/5 of the switching frequency (Fsw = 2 MHz):
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
RCOMP +
Fp @ gm
@ Vout @
(Fp * Fz) @ |Gps(Fc)| Vref
CCOMP +
Cp +
Ǹ
ǒ Ǔ
1 ) Fc
Fp
Ǹ
1
2p @ Fz @ RCOMP
1
2p @ Fp @ RCOMP
(eq. 21)
ǒ Ǔ
1 ) Fz
Fc
2
2
(eq. 22)
(eq. 23)
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 31
shows Cp is split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.
www.onsemi.com
15
NCV890100
From the calculation:
So the feedback compensation network is as below:
RCOMP = 10.6 KW, CCOMP = 2 nF, Cp = 37 pF
VOUT
RFB1
100 W
VCOMP
VFB
V
RFB2
31.6 W
gm*V
Vref
0.8 V
RCOMP
10 KW
18 pF
Cint
RO
CCOMP
19 pF
Cext
2 nF
Figure 31. Example of the Feedback Compensation Network
(dB)
Figure 32 shows the bode plot of the OTA compensator
20 ‧ log⎣ Gerr_amp ⎣f ( m )⎦
90
180
45
90
⎦
0
− 45
− 90
100
arg(Gerr_amp (f m ))‧
0
180
p
− 90
1 ⋅ 10
3
1 ⋅ 10
4
1 ⋅ 10
5
− 180
6
1 ⋅ 10
fm
(Hz)
Figure 32. Bode Plot of the OTA Compensator
(dB)
The total loop bode plot is as below:
20‧ log⎣ Gloop ⎣f ( m )⎦
90
180
45
90
⎦ 0
0
− 45
− 90
− 90
100
1⋅ 10
3
1⋅ 10
4
1⋅ 10
5
fm
(Hz)
Figure 33. Bode Plot of the Total Loop
The crossover frequency is at 70 KHz and phase margin is 75 degrees.
www.onsemi.com
16
− 180
6
1⋅ 10
arg(Gloop (f m ))‧
180
p
NCV890100
PCB LAYOUT RECOMMENDATION
Freewheeling diode ³ inductor ³ Output capacitor
³ return through ground
− Minimize the length of high impedance signals, and
route them far away from the power loops:
♦ Feedback trace
♦ Comp trace
As with any switching power supplies, there are some
guidelines to follow to optimize the layout of the printed
circuit board for the NCV890100. However, because of the
high switching frequency extra care has to be taken.
− Minimize the area of the power current loops:
♦ Input capacitor ³ NCV890100 switch ³ Inductor
³ output capacitor ³ return through Ground
♦
ORDERING INFORMATION
Device
NCV890100MWTXG
Package
Shipping†
DFN8 with wettable flanks
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506BY
ISSUE A
1
SCALE 2:1
A
B
D
DATE 23 MAY 2012
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L
L1
PIN ONE
REFERENCE
2X
0.10 C
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÉÉÉ
ÉÉÉ
ÇÇÇ
EXPOSED Cu
TOP VIEW
A
(A3)
DETAIL B
0.05 C
MOLD CMPD
A1
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.05 C
NOTE 4
SIDE VIEW
C
SEATING
PLANE
1
4
1
L
E2
8X
K
e/2
8
5
8X
0.10 C A B
0.05 C
BOTTOM VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
ÇÇÇÇÇÇ
ÇÇ
ÇÇÇÇ
2.46
1
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
0.65
PITCH
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
3.00 BSC
2.20
2.40
3.00 BSC
1.40
1.60
0.65 BSC
0.20
−−−
0.20
0.40
0.00
0.15
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
b
e
1.66
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
D2
DETAIL A
8X
A1
ÉÉ
ÇÇ
ÇÇ
A3
8X
0.53
3.30
8X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56369E
DFN8, 3X3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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