NVD4856NT4G

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Other names and brands may be claimed as the property of others. NTD4856N, NVD4856N Power MOSFET 25 V, 89 A, Single N−Channel, DPAK/IPAK Features • • • • • • Trench Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 4.7 mW @ 10 V 25 V 89 A 6.8 mW @ 4.5 V D Applications • VCORE Applications • DC−DC Converters • Low Side Switching N−Channel G S MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Unit 25 V VGS ±20 V ID 16.8 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 2.14 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 13.3 A Power Dissipation RqJA (Note 2) TA = 85°C Steady State 13.0 TA = 85°C PD 1.33 W Continuous Drain Current RqJC (Note 1) TC = 25°C ID 89 A Power Dissipation RqJC (Note 1) TC = 25°C PD 60 W TA = 25°C IDM 179 A TA = 25°C IDmaxPkg 45 A TJ, TSTG −55 to +175 °C TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) 69 IS 50 A Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 19 Apk, L = 1.0 mH, RG = 25 W) EAS 180.5 mJ TL 260 °C Lead Temperature for Soldering Purposes (1/8” from case for 10 s) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2014 April, 2017 − Rev. 4 1 2 1 3 DPAK CASE 369AA (Bent Lead) STYLE 2 1 2 3 3 IPAK CASE 369AC (Straight Lead) 1 2 3 IPAK CASE 369D (Straight Lead DPAK) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 10.3 TA = 25°C Pulsed Drain Current 4 4 Drain 4 Drain 4 Drain AYWW 48 56NG Value VDSS AYWW 48 56NG Gate−to−Source Voltage Symbol AYWW 48 56NG Parameter Drain−to−Source Voltage 4 4 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source A Y WW 4856N G = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location Code (A) is front side optional. In cases where the Assembly Location is stamped in the package bottom (molding ejecter pin), the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: NTD4856N/D NTD4856N, NVD4856N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 2.5 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient – Steady State (Note 1) RqJA 70 Junction−to−Ambient – Steady State (Note 2) RqJA 113 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 23 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 1.45 5.9 mV/°C VGS = 10 V ID = 30 A 3.9 4.7 VGS = 4.5 V ID = 30 A 5.3 6.8 VDS = 1.5 V, ID = 15 A 73 mW S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 279 Total Gate Charge QG(TOT) 18 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge 2241 VGS = 0 V, f = 1.0 MHz, VDS = 12 V VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 567 3.4 6.7 pF 27 nC 6.6 VGS = 10 V, VDS = 15 V, ID = 30 A 38 nC SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 15.7 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 22.5 18.6 ns 7.5 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NTD4856N, NVD4856N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 8.7 VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 17.5 ns 27.2 4.0 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.87 TJ = 125°C 0.72 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 30 A 1.2 V 18.7 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 9.3 ns 9.4 QRR 8.0 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.6 PACKAGE PARASITIC VALUES TA = 25°C 1.88 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 3 NTD4856N, NVD4856N TYPICAL PERFORMANCE CURVES ID, DRAIN CURRENT (AMPS) 4V 3.8 V 80 4.2 V TJ = 25°C 3.6 V 70 3.4 V 60 50 40 3.2 V 30 20 2.8 V 10 2.6 V 0 1 2 3 4 5 TJ = 25°C TJ = −55°C 0 1 2 3 4 5 Figure 2. Transfer Characteristics 0.03 0.02 0.01 2 4 6 8 10 0.008 0.0075 TJ = 25°C 0.007 0.0065 0.006 VGS = 4.5 V 0.0055 0.005 0.0045 VGS = 11.5 V 0.004 0.0035 0.003 0.0025 0.002 20 30 40 50 60 70 80 90 100 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.8 10000 VGS = 0 V ID = 30 A VGS = 10 V TJ = 150°C IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = 125°C Figure 1. On−Region Characteristics ID = 30 A TJ = 25°C 1.6 VDS ≥ 10 V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.04 0 130 120 110 100 90 80 70 60 50 40 30 20 10 0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 10 V 90 ID, DRAIN CURRENT (AMPS) 100 1.4 1.2 1.0 1000 TJ = 125°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 100 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage www.onsemi.com 4 25 NTD4856N, NVD4856N 3000 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) TYPICAL PERFORMANCE CURVES VGS = 0 V TJ = 25°C Ciss Coss Crss 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 12 8 Q1 4 2 0 0 IS, SOURCE CURRENT (AMPS) td(off) tf 100 tr td(on) 10 10 RG, GATE RESISTANCE (OHMS) 8 12 16 20 24 28 32 36 40 VGS = 0 V 25 20 15 10 5 100 ms 1 ms VGS = 20 V SINGLE PULSE TC = 25°C 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.8 0.6 1.0 Figure 10. Diode Forward Voltage vs. Current 10 ms 10 0.4 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 100 TJ = 25°C 0 0.2 100 1000 I D, DRAIN CURRENT (AMPS) 4 QG, TOTAL GATE CHARGE (nC) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 0.1 0.1 ID = 30 A TJ = 25°C 30 VDD = 15 V ID = 30 A VGS = 11.5 V 1 Q2 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 t, TIME (ns) VGS 6 Figure 7. Capacitance Variation 1 1 QT 10 200 ID = 19 A 180 160 140 120 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature www.onsemi.com 5 175 NTD4856N, NVD4856N r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) TYPICAL PERFORMANCE CURVES 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E-01 1.0E+00 1.0E+01 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NTD4856NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4856N−1G IPAK (Pb−Free) 75 Units / Rail NTD4856N−35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) 75 Units / Rail NVD4856NT4G* DPAK (Pb−Free) 2500 / Tape & Reel NVD4856NT4G−VF01 DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. www.onsemi.com 6 NTD4856N, NVD4856N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4856N, NVD4856N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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