NVMFD5485NLWFT1G

NVMFD5485NL MOSFET – Power, Dual N-Channel 60 V, 44 mW, 20 A Features • • • • • • • Small Footprint (5x6 mm) for Compact Designs Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses 175°C Operating Temperature NVMFD5485NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device www.onsemi.com V(BR)DSS RDS(on) MAX ID MAX 44 m @ 10 V 60 V 20 A 60 m @ 4.5 V Dual N−Channel D2 D1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS "20 V ID 19.5 A Parameter Continuous Drain Current RJC (Notes 1, 2, 4) TC = 25°C Power Dissipation RJC (Notes 1, 2) Continuous Drain Current RJA (Notes 1, 3 & 4) Steady State TC = 100°C TC = 25°C Power Dissipation RJA (Notes 1 & 3) Pulsed Drain Current PD Steady State 19.2 3.8 PD TA = 25°C, tp = 10 s Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 25 A, L = 0.1 mH, RG = 25 ) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) W 2.9 TA = 100°C Operating Junction and Storage Temperature A 5.3 TA = 100°C TA = 25°C MARKING DIAGRAM W 38.5 ID 1.4 IDM 113 A TJ, Tstg −55 to 175 °C IS 37 A EAS 31 mJ TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Parameter Symbol Value Unit °C/W Junction−to−Case − Steady State (Note 2) RJC 3.9 Junction−to−Ambient − Steady State (Note 3) RJA 52 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted to an ideal (infinite) heat sink. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. © Semiconductor Components Industries, LLC, 2015 July, 2019 − Rev. 3 S2 S1 13.8 TC = 100°C TA = 25°C G2 G1 1 1 DFN8 5x6 (SO8FL) CASE 506BT D1 D1 S1 G1 S2 G2 XXXXXX AYWZZ D1 D1 D2 D2 D2 D2 XXXXXX = 5485NL XXXXXX = (NVMFD5485NL) or XXXXXX = 5485LW XXXXXX = (NVMFD5485NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION Device Package Shipping† NVMFD5485NLT1G DFN8 1500/ (Pb−Free) Tape & Reel NVMFD5485NLT3G DFN8 5000/ (Pb−Free) Tape & Reel NVMFD5485NLWFT1G DFN8 1500/ (Pb−Free) Tape & Reel NVMFD5485NLWFT3G DFN8 5000/ (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NVMFD5485NL/D NVMFD5485NL 4. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. www.onsemi.com 2 NVMFD5485NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 A 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Reference to 25°C ID = 250 A Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VGS = 0 V, VDS = 60 V V 67 mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V ±100 A nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH) VGS = VDS, ID = 250 A VGS(TH)/TJ Reference to 25°C ID = 250 A 1.5 −4.86 2.5 RDS(on) VGS = 10 V, ID = 15 A 33 44 VGS = 4.5 V, ID = 10 A 42 60 V mV/°C m CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 560 VGS = 0 V, f = 1.0 MHz, VDS = 25 V pF 126 58 Total Gate Charge QG(TOT) 20 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS VGS = 10 V, VDS = 48 V, ID = 10 A 0.52 Gate−to−Drain Charge QGD VGS = 4.5 V, VDS = 48 V, ID = 10 A 11.5 nC td(on) 9.5 ns tr VGS = 4.5 V, VDS = 48 V, ID = 10 A, RG = 2.5  26.6 Total Gate Charge QG(TOT) nC 1.9 7.9 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) tf 27.8 23.7 DRAIN−SOURCE DIODE CHARACTERISTICS TJ = 25°C 0.93 TJ = 125°C 0.83 Forward Diode Voltage VSD Reverse Recovery Time tRR 28.9 Charge Time ta 23.2 Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 15 A VGS = 0 V, dIS/dt = 100 A/s, IS = 10 A 1.2 V ns 5.6 QRR 35.5 nC LS 0.93 nH PACKAGE PARASITIC VALUES Source Inductance Drain Inductance LD Gate Inductance LG Gate Resistance RG TA = 25°C 0.005 1.84 12 5. Pulse Test: pulse width = 300 s, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 3  NVMFD5485NL TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 4.1 V 20 3.9 V 15 3.7 V 3.5 V 10 3.3 V 3.1 V 2.9 V 5 2.7 V 0 1 2 3 4 5 10 TJ = 25°C 5 TJ = 125°C 1 TJ = −55°C 2 3 4 5 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 10 A TJ = 25°C 0.06 0.05 0.04 0.03 2.4 2.2 2.0 15 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.07 2 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.08 0.02 25 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (m) RDS(on), DRAIN−TO−SOURCE RESISTANCE (m) VDS = 10 V 4.5 V 5.5 V 25 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 30 VGS = 10 to 6.5 V 3 4 5 6 7 8 9 10 0.07 0.06 TJ = 25°C VGS = 4.5 V 0.05 0.04 VGS = 10 V 0.03 0.02 0.01 0 2 6 10 14 18 22 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. VGS Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.0E−04 ID = 10 A VGS = 10 V TJ = 150°C 1.0E−05 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 −50 −25 30 26 VGS, GATE−TO−SOURCE VOLTAGE (V) IDSS, LEAKAGE (A) ID, DRAIN CURRENT (A) 30 1.0E−06 TJ = 125°C 1.0E−07 1.0E−08 1.0E−09 1.0E−10 TJ = 25°C 1.0E−11 0 25 50 75 100 125 150 1.0E−12 175 5 10 15 20 25 30 35 40 45 50 55 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 4 NVMFD5485NL 1000 TJ = 25°C VGS = 0 V 800 700 Ciss 600 500 400 300 Coss 200 0 1000 10 20 30 40 50 60 8 TJ = 25°C 6 Qgs 4 Qgd VDD = 48 V ID = 10 A 2 0 0 2 4 6 8 10 12 14 16 18 Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge td(off) tr 20 10 9 100 1 QT 10 Qg, TOTAL GATE CHARGE (nC) VDD = 48 V VGS = 4.5 V ID = 10 A 10 12 VDS, DRAIN−TO−SOURCE VOLTAGE (V) IS, SOURCE CURRENT (A) 100 0 Crss tf td(on) 1 10 7 6 5 4 3 2 1 0 100 TJ = 25°C VGS = 0 V 8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE () VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 ID, DRAIN CURRENT (A) C, CAPACITANCE (pF) 900 t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 100 TC = 25°C VGS = 10 V Single Pulse 10 s 100 s 1 ms 10 ms 10 dc 1 RDS(on) Limit Thermal Limit Package Limit 0.1 0.01 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 5 100 NVMFD5485NL TYPICAL CHARACTERISTICS 100 R(t) (°C/W) 10 1 50% Duty Cycle 20% 10% 5% 2% 1% 0.1 Single Pulse 0.01 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) Figure 12. Thermal Response www.onsemi.com 6 1 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual) CASE 506BT ISSUE F 1 2X SCALE 2:1 0.20 C D A B D1 8 7 6 ÉÉ ÉÉ ÉÉ PIN ONE IDENTIFIER NOTE 7 1 2 2X 0.20 C 5 DATE 23 NOV 2021 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. E1 E 4X h 3 4 c TOP VIEW A1 0.10 C A DETAIL B 0.10 C NOTE 4 C SIDE VIEW DETAIL A D2 D3 4X e 1 SEATING PLANE NOTE 6 ALTERNATE CONSTRUCTION DETAIL A L K 4 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N MILLIMETERS NOM MIN MAX −−− 0.90 1.10 −−− −−− 0.05 0.33 0.42 0.51 0.33 0.42 0.51 0.20 −−− 0.33 5.15 BSC 4.70 4.90 5.10 3.90 4.10 4.30 1.50 1.70 1.90 6.15 BSC 5.70 5.90 6.10 3.90 4.15 4.40 1.27 BSC 0.45 0.55 0.65 −−− −−− 12 _ 0.51 −−− −−− 0.56 −−− −−− 0.48 0.61 0.71 3.25 3.50 3.75 1.80 2.00 2.20 SOLDERING FOOTPRINT* DETAIL B 4.56 M 4X b1 N 4X 8 G 5 8X 2X 2X 2.08 8X E2 0.75 0.56 b K1 BOTTOM VIEW 0.10 C A B 0.05 C GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ NOTE 3 4.84 4X 6.59 3.70 0.70 4X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 1.40 2.30 1.00 1.27 PITCH 5.55 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON50417E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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