NVMFD5853NLWFT1G

NVMFD5853NL Power MOSFET 40 V, 10 mW, 34 A, Dual N−Channel Logic Level, Dual SO−8FL Features • • • • • • Small Footprint (5x6 mm) for Compact Designs Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses NVMFD5853NLWF − Wettable Flanks Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device http://onsemi.com V(BR)DSS Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RYJ−mb (Notes 1, 2, 3, 4) Power Dissipation RYJ−mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3 & 4) Power Dissipation RqJA (Notes 1 & 3) Pulsed Drain Current Tmb = 25°C Steady State 10 mW @ 10 V 34 A 15 mW @ 4.5 V Dual N−Channel Symbol Value Unit VDSS 40 V VGS "20 V ID 34 A Tmb = 100°C Tmb = 25°C Steady State 24 PD Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VGS = 10 V, IL(pk) = 28.3 A, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) D1 D1 8.5 1 PD 3.0 IDM 165 A TJ, Tstg −55 to 175 °C IS 34 A EAS 40 mJ TL 260 °C W 1.5 THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Junction−to−Mounting Board (top) − Steady State (Notes 2, 3) Junction−to−Ambient − Steady State (min footprint) Value RYJ−mb 6.2 Unit °C/W 51 RqJA 162 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Continuous DC current rating. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 4 DFN8 5x6 (SO8FL) CASE 506BT 1 S1 G1 S2 G2 5853xx AYWZZ D1 D1 D2 D2 D2 D2 5853NL = Specific Device Code for NVMFD5853NL 5853LW = Specific Device Code for NVMFD5853NLWF A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION Device Symbol Junction−to−Ambient − Steady State (Note 3) MARKING DIAGRAM A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Parameter S2 S1 W 12 TA = 100°C TA = 25°C, tp = 10 ms G2 G1 12 ID TA = 100°C TA = 25°C D2 D1 24 Tmb = 100°C TA = 25°C ID MAX 40 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter RDS(on) MAX Package Shipping† NVMFD5853NLT1G DFN8 1500 / Tape & (Pb−Free) Reel NVMFD5853NLWFT1G DFN8 1500 / Tape & (Pb−Free) Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NVMFD5853NL/D NVMFD5853NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 40 V mV/°C TJ = 25°C 1.0 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA Gate−to−Source Leakage Current V 37.1 ±100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 1.4 2.4 5.9 V mV/°C VGS = 10 V, ID = 15 A 8.4 10 VGS = 4.5 V, ID = 15 A 12.7 15 VDS = 5 V, ID = 5 A 22 S pF mW CHARGES AND CAPACITANCES Input Capacitance Ciss 1100 Output Capacitance Coss 152 Reverse Transfer Capacitance Crss 100 Total Gate Charge QG(TOT) 12.8 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 32 V, ID = 15 A nC 1.0 3.7 7.0 VGS = 10 V, VDS = 32 V, ID = 15 A 23 nC td(on) 10 ns tr 53 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) VGS = 4.5 V, VDS = 20 V, ID = 15 A, RG = 2.5 W 17 tf 30 td(on) 9.0 tr td(off) VGS = 10 V, VDS = 20 V, ID = 15 A, RG = 2.5 W tf ns 23 22 4.3 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.84 TJ = 125°C 0.69 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 20 A 20 VGS = 0 V, dIS/dt = 100 A/ms, IS = 15 A QRR http://onsemi.com 2 V ns 12 8.1 12.1 5. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. 1.1 nC NVMFD5853NL TYPICAL CHARACTERISTICS 70 70 10 V TJ = 25°C 4.5 V 7.5 V ID, DRAIN CURRENT (A) 50 3.8 V 40 30 3.4 V 20 10 1.0 2.0 3.0 4.0 40 30 TJ = 25°C 20 3.0 3.5 4.0 4.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.025 0.020 0.015 0.010 0.005 3 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 0.0200 TJ = 25°C 0.0175 0.0150 VGS = 4.5 V 0.0125 0.0100 VGS = 10 V 0.0075 0.0050 0 5 10 15 20 25 30 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. VGS Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 2.2 VGS = 0 V ID = 15 A VGS = 10 V TJ = 150°C 1.8 IDDS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) ID = 15 A TJ = 25°C 2.0 TJ = −55°C TJ = 125°C 0 2.0 5.0 0.030 2 50 10 3.0 V 0 0.0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS ≥ 10 V 60 4.2 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 60 1.6 1.4 1.2 1.0 TJ = 125°C 1000 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 100 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 40 NVMFD5853NL TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) VGS = 0 V TJ = 25°C Ciss 1250 VGS, GATE−TO−SOURCE VOLTAGE (V) 1500 1000 750 500 Coss 250 Crss 0 0 10 20 30 40 QT 8 6 Qgs 4 Qgd TJ = 25°C VDS = 32 V ID = 15 A 2 0 0 5 10 15 20 25 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 70 VDS = 20 V ID = 15 A VGS = 4.5 V IS, SOURCE CURRENT (A) 1000 tr 100 td(on) tf td(off) 10 1 1 10 100 60 VGS = 0 V TJ = 25°C 50 40 30 20 10 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 ID, DRAIN CURRENT (A) t, TIME (ns) 10 10 ms 10 100 ms 1 0.1 VGS = 10 V Single Pulse TC = 25°C RDS(on) Limit Thermal Limit Package Limit 0.1 1 ms 10 ms dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 NVMFD5853NL TYPICAL CHARACTERISTICS 100 Duty Cycle = 50% RqJA (°C/W) 10 1 20% 10% 5% 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) Figure 12. Thermal Response http://onsemi.com 5 1 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual) CASE 506BT ISSUE F 1 2X SCALE 2:1 0.20 C D A B D1 8 7 6 ÉÉ ÉÉ ÉÉ PIN ONE IDENTIFIER NOTE 7 1 2 2X 0.20 C 5 DATE 23 NOV 2021 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. E1 E 4X h 3 4 c TOP VIEW A1 0.10 C A DETAIL B 0.10 C NOTE 4 C SIDE VIEW DETAIL A D2 D3 4X e 1 SEATING PLANE NOTE 6 ALTERNATE CONSTRUCTION DETAIL A L K 4 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N MILLIMETERS NOM MIN MAX −−− 0.90 1.10 −−− −−− 0.05 0.33 0.42 0.51 0.33 0.42 0.51 0.20 −−− 0.33 5.15 BSC 4.70 4.90 5.10 3.90 4.10 4.30 1.50 1.70 1.90 6.15 BSC 5.70 5.90 6.10 3.90 4.15 4.40 1.27 BSC 0.45 0.55 0.65 −−− −−− 12 _ 0.51 −−− −−− 0.56 −−− −−− 0.48 0.61 0.71 3.25 3.50 3.75 1.80 2.00 2.20 SOLDERING FOOTPRINT* DETAIL B 4.56 M 4X b1 N 4X 8 G 5 8X 2X 2X 2.08 8X E2 0.75 0.56 b K1 BOTTOM VIEW 0.10 C A B 0.05 C GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ NOTE 3 4.84 4X 6.59 3.70 0.70 4X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 1.40 2.30 1.00 1.27 PITCH 5.55 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON50417E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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