P3I2005AG-08SR

P3I2005A General Purpose Peak EMI Reduction IC Product Description P3I2005A is a versatile, 3.3 V / 5 V, 1x spread spectrum frequency modulator designed to reduce electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The device allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. P3I2005A modulates the output of a PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. P3I2005A accepts an input from an external reference clock and locks to a 1x modulated clock output. Two logic pins S0 and D_C enable selecting one of the 4 different frequency deviations. Refer Deviation Selection table. Frequency Range Selection pin enables operation in one of the two frequency ranges. P3I2005A operates over a supply voltage range of 5 V / 3.3 V. P3I2005A is available in 8 Pin SOIC Package. Features • • • • • • • • 1x, LVCMOS Peak EMI Reduction Input Clock Frequency : 10 MHz − 100 MHz Output Clock Frequency : 10 MHz − 100 MHz Four different Frequency Deviation selection Frequency range Selection Supply voltage: 5 V $ 0.5 V 3.3 V $ 0.3 V 8 Pin SOIC Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com MARKING DIAGRAM 8 8 1 SOIC−8 CASE 751 AFG A L Y W G 1 AFG ALYWX G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONFIGURATION CLKIN/XIN 1 XOUT 2 8 VDD P3I2005A 7 ModOUT D_C 3 6 FRS GND 4 5 S0 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Application • P3I2005A is targeted for use in a broad range of notebook and desktop PCs and consumer electronic applications. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 1 1 Publication Order Number: P3I2005A/D P3I2005A FRS CLKIN/XIN XOUT S0 D_C VDD ModOUT Crystal Oscillator PLL GND Figure 1. Block Diagram PIN DESCRIPTION Pin# Pin Name Type 1 CLKIN / XIN I External reference Clock input or Crystal connection. Description 2 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. 3 D_C I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection table 4 GND P Ground connection. 5 S0 I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection table 6 FRS I Frequency Range Selection. Has an internal pull−up resistor 7 ModOUT O Buffered Modulated Clock Output. 8 VDD P Power supply for the entire chip(3.3 V/5 V) FREQUENCY RANGE SELECTION TABLE FRS Frequency(MHz) 0 10 − 30 1 30 − 100 DEVIATION SELECTION TABLE Deviation (%) FS = 0 FS = 1 D_C S0 10 MHz 20 MHz 30 MHz 30 MHz 80 MHz 100 MHz 0 0 −4.5 −3.6 −1.7 −4.8 −3.6 −2.6 0 1 −2.6 −2 −1 −2.7 −2 −1.5 1 0 $2.6 $2 $1 $2.75 $2 $1.5 1 1 $1.7 $1.25 $0.7 $1.8 $1.25 $1 http://onsemi.com 2 P3I2005A OPERATING CONDITIONS Min Max Unit VDD(5V) Symbol Supply Voltage Parameter 4.5 5.5 V VDD(3.3V) Supply Voltage 3 3.6 V −40 +85 °C TA Operating Temperature CL Load Capacitance 15 pF CIN Input Capacitance 7 pF ABSOLUTE MAXIMUM RATINGS Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any input pin with respect to Ground −0.5 to +7.0 V Storage temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. DC ELECTRICAL CHARACTERISTICS FOR VDD = 5 V $ 0.5 V Symbol Parameter Min Typ Max Unit 5.0 5.5 V VDD Operating voltage 4.5 VIL Input low voltage GND – 0.3 0.8 V VIH Input high voltage 2.0 VDD + 0.3 V IIL Input low current 100 mA IIH Input high current 100 mA VOL Output low voltage (IOL = 12 mA) 0.4 V VOH Output high voltage (IOH = −12 mA) ICC Static supply current (CLKIN/XIN pulled to GND) IDD Dynamic supply current (Unloaded Output) ZOUT 2.5 V 12 mA FS = 0 (@ 30 MHz) 34 mA FS = 1 (@ 100 MHz) 40 Output impedance 30 http://onsemi.com 3 W P3I2005A AC ELECTRICAL CHARACTERISTICS FOR VDD = 5 V$ 0.5 V Symbol CLKIN/XIN MODOUT Parameter Min Input Clock Frequency Output Clock Frequency Max Unit FRS = 0 10 Typ 30 MHz FRS = 1 30 100 FRS = 0 10 30 FRS = 1 30 100 MHz tLH (Notes 1 & 2) Output Rise time (measured between 20% to 80%) 1.6 2 nS tHL (Notes 1 & 2) Output Fall time (measured between 80% to 20%) 1.2 1.6 nS tD (Notes 1 & 2) Output duty cycle 50 55 % $250 $350 pS 3 mS tJC (Note 2) tON (Notes 1 & 2) 45 Jitter (cycle to cycle) @ FS = 0, 24 MHz and FS = 1, 80 MHz PLL lock time (Stable VDD, valid Clock presented on CLKIN/XIN) 1. All parameters are specified with 15 pF loaded output. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production DC ELECTRICAL CHARACTERISTICS FOR VDD = 3.3 V $ 0.3 V Symbol Parameter Min Typ Max Unit 3.3 3.6 V VDD Operating voltage 3 VIL Input low voltage GND − 0.3 0.8 V VIH Input high voltage 2.0 VDD + 0.3 V IIL Input low current 100 mA IIH Input high current 100 mA VOL Output low voltage (IOL = 12 mA) 0.4 V VOH Output high voltage (IOH = −12 mA) ICC Static supply current (CLKIN/XIN pulled to GND) 11 mA IDD Dynamic supply current (Unloaded Output) FS = 0 (@ 30 MHz) 26 mA FS = 1 (@ 100 MHz) 32 ZOUT 2.5 Output impedance V 40 http://onsemi.com 4 W P3I2005A AC ELECTRICAL CHARACTERISTICS FOR VDD = 3.3 V $ 0.3 V Symbol CLKIN/XIN MODOUT Parameter Min Input Clock Frequency Output Clock Frequency Max Unit FRS = 0 10 Typ 30 MHz FRS = 1 30 100 FRS = 0 10 30 FRS = 1 30 100 MHz tLH (Notes 3 & 4) Output Rise time (measured between 20% to 80%) 1.9 2.5 nS tHL (Notes 3 & 4) Output Fall time (measured between 80% to 20%) 1.5 2 nS tD (Notes 3 & 4) Output duty cycle 50 55 % $250 $350 pS 3 mS tJC (Note 4) tON (Notes 3 & 4) 45 Jitter (cycle to cycle) @ FS=0, 24MHz & FS=1, 80 MHz PLL lock time (Stable VDD, valid Clock presented on CLKIN/XIN) 3. All parameters are specified with 15 pF loaded output. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production ORDERING INFORMATION Part Number P3I2005AG−08SR Marking Package Temperature Shipping† AFG 8−PIN SOIC (Pb−Free) −40°C to +85°C Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 5 P3I2005A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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