P3P8163AG-08SR

P3P8163A 3.3V, LVCMOS Spread Spectrum Peak EMI Reduction Device Product Description P3P8163A is a 3.3 V, spread spectrum frequency modulator that generates a 1x, LVCMOS low EMI spread spectrum clock and two reference clock outputs. The P3P8163A reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. It allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass EMI regulations. The P3P8163A can generate an EMI reduced clock from a fundamental Crystal or from an external reference clock. P3P8163A has a SEL pin to turn off CLK2 when ‘1’. Refer Output Table. P3P8163A operates over 3.3 V ±5% supply voltage range and is available in 8 pin SOIC package. http://onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 xx A L Y W G Features • Input Clock: 12 MHz from Fundamental XTAL or External • • • • • • • • 8 1 1 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Reference Clock Output Clocks: CLK0: 12 MHz ±0.4% CLK1, CLK2: 12 MHz (REFOUT) SEL Pin to Turn Off CLK2 Low Inherent Cycle−to−Cycle Jitter Supply Voltage: 3.3 V ±5% LVCMOS Input and Output Operating Temperature Range: 0°C to 70°C 8−pin SOIC Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Application • The P3P8163A is targeted towards EMI management in consumer electronics applications including MFPs. 7 XOUT 8 1 VDD PLL + Frequency Modulator Crystal Oscillator CLK0 2 CLK1 5 XIN/CLKIN CLK2 6 4 3 GND SEL Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2011 September, 2011 − Rev. 0 1 Publication Order Number: P3P8163A/D P3P8163A XIN/CLKIN 1 8 XOUT CLK0 2 7 VDD SEL 3 6 CLK2 GND 4 5 CLK1 Figure 2. Pin Configuration Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 XIN / CLKIN Input 2 CLK0 Output 3 SEL Input 4 GND Power Ground to entire chip. 5 CLK1 Output Reference clock Output. 6 CLK2 Output Reference clock Output. Has a Pull−down resistor when OFF. 7 VDD Power Power supply for the entire chip 8 XOUT Output Crystal connection. If using an external reference, this pin must be left unconnected. Crystal connection or External Clock input. Spread Spectrum Clock output. 2 level logic input. When ‘0’ CLK2 is enabled. When ‘1’ CLK2 is turned off. Has a Pull−down resistor. Table 2. OUTPUT TABLE SEL CLK0 CLK1 CLK2 0 Spread Spectrum Clock output Reference clock Output Reference clock Output 1 Spread Spectrum Clock output Reference clock Output OFF Table 3. OPERATING CONDITIONS Symbol VDD Description Voltage on any pin with respect to GND Min Max Unit 3.135 3.465 V 0 +70 °C TA Operating temperature CL Load Capacitance 15 pF CIN Input Capacitance 7 pF http://onsemi.com 2 P3P8163A Table 4. MAXIMUM RATINGS Symbol VDD, VIN TSTG Rating Unit Voltage on any pin with respect to Ground Parameter −0.5 to +4.6 V Storage temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage(As per JEDEC STD 22− A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 5. DC ELECTRICAL CHARACTERISTICS (NOTE − Unless otherwise stated VDD = 3.3 V ± 5%, CL = 15 pF and Ambient Temperature range 0°C to +70°C) Parameter Symbol Min Typ Max Unit 3.135 3.3 3.465 V 17 mA VDD Supply Voltage IDD Dynamic supply current (CL = 15 pF, VDD = 3.465 V, Temp = +70°C) VIL Input low voltage (XIN/CLKIN, SEL Inputs) 0 0.8 V VIH Input high voltage (XIN/CLKIN, SEL Inputs) 0.9 * VDD VDD V VOL Output low voltage (CLK[0:2]) IOL = 12 mA 0.4 V VOH Output high voltage (CLK[0:2]) IOH = −12 mA CIN1 Input Capacitance (XIN/CLKIN and XOUT) CIN2 Input capacitance (SEL Input) RPD Internal Pull down Resistor (CLK2) 200 kW Output Impedance 25 W Z0 NOTE: 2.4 V 6 pF 7 The voltage on any input or I/O pin cannot exceed the power pin during power up. http://onsemi.com 3 pF P3P8163A Table 6. AC ELECTRICAL CHARACTERISTICS (NOTE − Unless otherwise stated VDD = 3.3 V ± 5%, CL = 15 pF and Ambient Temperature range 0°C to +70°C) Parameter Symbol fIN fOUT Min Typ Max Unit Input Clock frequency 12 MHz CLK0, Modulated output Clock, ±0.4% 12 MHz CLK1, CLK2 Reference clock output 12 tLH, tHL (Notes 1 and 2) CLK0, Rise and Fall time (Measured between 20% to 80%) 1.25 2.0 ns tLH, tHL (Notes 1 and 2) CLK1, CLK2, Rise and Fall time (Measured between 20% to 80%) 1.25 2.0 ns TDCOUT (Notes 1 and 2) Output Clock Duty Cycle 50 55 % 45 TJC (Note 2) Cycle−Cycle Jitter, Peak (1000 cycles) (For CLK0) 150 pS TJP (Note 2) Period Jitter, Peak (10000 cycles) (For CLK1, CLK2) 125 pS tON (Notes 1 and 2) fdvar Power Up Time (Stable power supply, valid input clock to valid clock on CLK0). Frequency Deviation (CLK0) ±0.4 1. Parameters are specified with 15 pF loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production R Rx Crystal CL CL CL = 2*(CP – CS), Where CP = Load capacitance of crystal specified in a Crystal Datasheet CS = Stray capacitance due to CIN, PCB, Trace etc CL =Load capacitance to be used Rx is used to reduce power dissipation in the Crystal Figure 3. Typical Crystal Interface Circuit http://onsemi.com 4 4 ms ±0.52 % P3P8163A VDD C4, 2.2 mF 7 C1 1 XIN C3, 0.1 mF VDD Y1 C2 Rs 2 CLK0 8 VDD 3 XOUT SEL Rs CLK1 5 CLK2 6 P3P8163A Rs GND 4 Rs = Trace Impedance of PCB − Output Impedance of Device (Z0) Figure 4. Typical Application Schematic ORDERING INFORMATION Device P3P8163AG−08SR Top Marking Temperature Package Shipping† CUL 0°C to +70°C SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 P3P8163A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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