Programmable Precision
References
NCP431A, SC431A,
NCP431B, SC431B,
NCP432B, SC432B Series
The NCP431/NCP432 integrated circuits are three−terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
programmable from Vref to 36 V using two external resistors. These
devices exhibit a wide operating current range of 40 mA to 100 mA
with a typical dynamic impedance of 0.22 W. The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain a
stable reference from 5.0 V logic supplies, and since the NCP431/
NCP432 operates as a shunt regulator, it can be used as either a
positive or negative voltage reference. Low minimum operating
current makes this device an ideal choice for secondary regulators in
SMPS adapters with extremely low no−load consumption.
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Pin 1. Reference
2. Anode
3. Cathode
3
STRAIGHT LEAD
BULK PACK
12
TO−92
LP SUFFIX
CASE 29−10
Features
• Programmable Output Voltage to 36 V
• Low Minimum Operating Current: 40 mA, Typ @ 25°C
• Voltage Reference Tolerance: ±0.5%, Typ @ 25°C
•
•
•
•
•
•
•
•
•
•
•
Voltage Adapters
Switching Power Supply
Precision Voltage Reference
Charger
Instrumentation
© Semiconductor Components Industries, LLC, 2011
April, 2021 − Rev. 17
3
BENT LEAD
TAPE & REEL
AMMO PACK
SOIC−8 NB
D SUFFIX
CASE 751
1
1
Cathode
Reference
Anode
Anode
Anode
Anode
NC
NC
(Top View)
3
1
SOT−23
SN SUFFIX
CASE 318
2
NCP431/SC431
Pin 1. Reference
2. Cathode
3. Anode
Typical Applications
2
TO−92
LPRA SUFFIX
CASE 29−10
8
(NCP431B/NCP432B)
Low Dynamic Output Impedance, 0.22 W Typical
Sink Current Capability of 40 mA to 100 mA
Equivalent Full−Range Temperature Coefficient of 50 ppm/°C
Typical
Temperature Compensated for Operation over Full Rated Operating
Temperature Range
SC Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q100 Qualified and
PPAP Capable
These are Pb−Free Devices
1
NCP432/SC432
Pin 1. Cathode
2. Reference
3. Anode
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
1
Publication Order Number:
NCP431/D
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
Reference
(R)
Cathode
(K)
Reference
(R)
Cathode
(K)
2.5 V ref
Anode
(A)
Anode
(A)
Figure 1. Symbol
Figure 2. Representative Block diagram
This device contains 20 active transistors
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted)
Symbol
VKA
Rating
Value
Unit
37
V
−100 to +150
mA
−5 to +10
mA
150
°C
Cathode to Anode Voltage
IK
Cathode Current Range, Continuous
Iref
Reference Input Current Range, Continuous
TJ
Operating Junction Temperature
TA
Operating Ambient Temperature Range
−40 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
PD
Total Power Dissipation @ TA = 25°C
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package
SN1 Suffix Plastic Package
PD
HBM
CDM
W
0.70
0.52
Total Power Dissipation @ TC = 25°C
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package
1.5
ESD Rating (Note 1)
Human Body Model per JEDEC JESD22−A114F
Charged Device Model per JEDEC JESD22−C101E
W
V
>2000
>1000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds ±100 mA per JEDEC standard JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VKA
IK
Min
Max
Unit
Cathode to Anode Voltage
Condition
Vref
36
V
Cathode Current
0.04
100
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Symbol
Characteristic
LP Suffix Package
(50 mm2 x 35 mm Cu)
D Suffix Package
(50 mm2 x 35 mm Cu)
SN Suffix Package
(10 mm2 x 35 mm Cu)
Unit
RQJA
Thermal Resistance,
Junction−to−Ambient
176
210
255
°C/W
RQJL
Thermal Resistance,
Junction−to−Lead (Lead 3)
75
68
80
°C/W
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2
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
NCP431AC
Symbol
Vref
Min
Characteristic
Reference Input Voltage
VKA = Vref, IK = 1 mA
TA = 25°C
TA = Tlow to Thigh (Figure 3, Note 2)
2.475 2.500 2.525
2.475 2.500 2.525
Reference Input Voltage Deviation Over Temperature Range (Figure 3, Notes 3, 4)
VKA= Vref, IK = 1 mA
DVref
DVKA
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
IK = 1 mA (Figure 4),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
DIrefT
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
DVrefT
Iref
Typ
NCP431AV/
SC431AV
NCP431AI
−
−
−
2.475 2.500 2.525 2.475 2.500 2.525
2.465 2.500 2.525 2.460 2.500 2.525
−
5.0
10
−
10
15
mV
mV/
V
−
−
−1.85
−0.80
−3.1
−1.8
−
−
−1.85
−0.80
−3.1
−1.8
−
−
−1.85
−0.80
−3.1
−1.8
Reference Input Current (Figure 4)
IK = 1 mA, R1 = 220 k, R2 = R
TA = −40°C to +125°C
−
81
190
−
81
190
−
81
190
Reference Input Current Deviation Over Temperature Range (Figure 4, Note 3)
IK = 1 mA, R1 = 10 k, R2 = R
−
22
55
−
22
55
−
22
55
nA
nA
Imin
Minimum Cathode Current For Regulation
VKA = Vref (Figure 3)
−
40
60
−
40
60
−
40
60
mA
Ioff
Off−State Cathode Current (Figure 5)
VKA = 36 V, Vref = 0 V
−
180
1000
−
180
1000
−
180
1000
nA
Dynamic Impedance (Figure 3, Note 5)
VKA = Vref, DIK = 1.0 mA to 100 mA
f v 1.0 kHz
−
0.22
0.5
−
0.22
0.5
−
0.22
0.5
W
|ZKA|
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Tlow = −40°C for NCP431AI, NCP431AV, SC431AV
= 0°C for NCP431AC
Thigh = 70°C for NCP431AC
= 85°C for NCP431AI
= 125°C for NCP431AV, SC431AV
3. Guaranteed by design
4. The deviation parameter DVrefT is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
ǒ
The average temperature coefficient of the reference input voltage, Vref is defined as:
V
ppm
ref ° C
+
DV
V
ref
@25° C
ref
DT
Ǔ
106
+
A
DV
DT
ref
10 6
ǒVref@25° CǓ
A
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature.
Example: DVrefT = 17 mV and slope is positive
Vref = 2.5 V, DTA = 165°C (from −40°C to +125°C)
aV
ref
+
0.017 @ 10 6
165 @ 2.5
+ 41.2 ppmń° C
5. The dynamic impedance ZKA is defined as: (|ZKA| = (DVKA/DIK). When the device is programmed with two external resistors, R1 and R2,
the total dynamic impedance of the circuit is defined as: |ZKA’| [ |ZKA| (1 + (R1/R2)).
6. SC431AVSNT1G − Tlow = −40°C, Thigh = 125°C. Guaranteed by design. SC Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
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3
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
NCP431BC
NCP432BC
Symbol
Vref
Reference Input Voltage
VKA = Vref, IK = 1 mA
TA = 25°C
TA = Tlow to Thigh (Figure 3, Note 7)
DVrefT
Reference Input Voltage Deviation Over Temperature Range (Figure 3, Notes 8, 9)
VKA= Vref, IK = 1 mA
DVref
DVKA
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
IK = 1 mA (Figure 4),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
Iref
DIrefT
Min
Characteristic
Typ
NCP431BI
NCP432BI
Max
Min
Typ
NCP/SC431BV
NCP/SC432BV
Max
Min
Typ
Max
Unit
V
2.4875 2.500 2.5125 2.4875 2.500 2.5125 2.4875 2.500 2.5125
2.4875 2.500 2.5125 2.4775 2.500 2.5125 2.4725 2.500 2.5125
−
−
−
−
−
−
−
5.0
10
1−
−
−
10
15
15
mV
mV/
V
−
−
−1.85
−0.80
−3.1
−1.8
−
−
−1.85
−0.80
−3.1
−1.8
−
−
−1.85
−0.80
−3.1
−1.8
Reference Input Current (Figure 4)
IK = 1 mA, R1 = 220 k, R2 = R
TA = −40°C to +125°C
−
81
190
−
81
190
−
81
190
Reference Input Current Deviation Over Temperature Range (Figure 4, Note 8)
IK = 1 mA, R1 = 10 k, R2 = R
−
22
55
−
22
55
−
22
55
nA
nA
Imin
Minimum Cathode Current For Regulation
VKA = Vref (Figure 3)
−
40
60
−
40
60
−
40
60
mA
Ioff
Off−State Cathode Current (Figure 5)
VKA = 36 V, Vref = 0 V
−
180
1000
−
180
1000
−
180
1000
nA
Dynamic Impedance (Figure 3, Note 10)
VKA = Vref, DIK = 1.0 mA to 100 mA
f v 1.0 kHz
−
0.22
0.5
−
0.22
0.5
−
0.22
0.5
W
|ZKA|
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Tlow = −40°C for NCP431BI, NCP431BV, NCP432BI, NCP432BV, SC431B, SC432B
= 0°C for NCP431BC, NCP432BC
Thigh = 70°C for NCP431BC, NCP432BC
= 85°C for NCP431BI, NCP432BI
= 125°C for NCP431BV, NCP432BV, SC431BV, SC432BV
8. Guaranteed by design
9. The deviation parameter DVrefT is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
ǒ
The average temperature coefficient of the reference input voltage, Vref is defined as:
V
ppm
ref ° C
+
DV
V
ref
@25° C
ref
DT
Ǔ
106
+
A
DV
DT
ref
10 6
ǒVref@25° CǓ
A
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature.
Example: DVrefT = 17 mV and slope is positive
Vref = 2.5 V, DTA = 165°C (from −40°C to +125°C)
aV
ref
+
0.017 @ 10 6
165 @ 2.5
+ 41.2 ppmń° C
10. The dynamic impedance ZKA is defined as: (|ZKA| = (DVKA/DIK). When the device is programmed with two external resistors, R1 and R2,
the total dynamic impedance of the circuit is defined as: |ZKA’| [ |ZKA| (1 + (R1/R2))
11. SC431BVSNT1G, SC432BVSNT1G − Tlow = −40°C, Thigh = 125°C. Guaranteed by design. SC Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
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4
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
Input
Input
VKA
V KA
Input
IK
V KA
Ioff
R1
Iref
IK
Vref
R2
Figure 3. Test Circuit for VKA = Vref
Vref
V
ǒ1 ) R1
Ǔ ) Iref @ R1
R2
ref
60.0
Input
IK, CATHODE CURRENT (mA)
VKA = Vref
TA = 25°C
VKA
IK
50.0
0.0
−50.0
−100.0
−1.0
Figure 5. Test Circuit for Ioff
VKA = Vref
TA = 25°C
Input
40.0
VKA
IMin
IK
20.0
0.0
−20.0
−40.0
0.0
1.0
2.0
3.0
−60.0
−1.0
0.0
1.0
Figure 6. Cathode Current versus Cathode
Voltage
Figure 7. Cathode Current versus Cathode
Voltage
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
−50
−25
2.0
VKA, CATHODE VOLTAGE (V)
VKA, CATHODE VOLTAGE (V)
IMIN, (mA)
IK, CATHODE CURRENT (mA)
+V
Figure 4. Test Circuit for VKA > Vref
150.0
100.0
KA
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
Figure 8. Minimum Cathode Current Regulation
versus Ambient Temperature
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5
3.0
VKA = Vref
IK = 1 mA
VKA
Input
2530
Iref, REFERENCE INPUT CURRENT (nA)
2540
IK
2520
Vref
2510
2500
2490
2480
2470
2460
−50
−25
0
25
50
75
100
125
Input
110
100
220k
IK = 1 mA
VKA
IK
Iref
90
80
70
60
50
40
−50
−25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Input Current versus
Ambient temperature
0
Input
VKA
IK
R1
−10
R2
Vref
−20
−30
VKA = Vref
IK = 1 mA
−40
0
10
20
30
40
100
Input
VKA = 36V
V ref = 0V
VKA
Ioff
10
1
−50
−25
0
25
50
75
100
125
VKA, CATHODE VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 11. Change in Reference Input Voltage
versus Cathode Voltage
Figure 12. Off−State Cathode Current versus
Ambient Temperature
10
0.320
1.0k
Output
|ZKA|, DYNAMIC IMPEDANCE (W)
|ZKA|, DYNAMIC IMPEDANCE (W)
120
Figure 9. Reference Input Voltage versus
Ambient temperature
Ioff, OFF−STATE CATHODE CURRENT (nA)
DVref, REFERENCE INPUT VOLTAGE (mV)
Vref, REFERENCE INPUT VOLTAGE (mV)
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
IK
50
GND
1
DIK = 1 mA to 100 mA
TA = 25°C
0.1
0.001
0.01
0.1
1
f, FREQUENCY (MHz)
10
0.300
0.280
0.260
VKA = V ref
DI K = 1.0 mA to 100mA
f Vref
[2.0 V
ref
Figure 31. Single−Supply Comparator with
Temperature−Compensated Threshold
ǓVref
ǓVref
Figure 30. Voltage Monitoring
150 mH @ 2.0 A
Vin = 10 to 20 V
TIP115
VOUT = 5.0 V
IOUT = 1.0 A
1.0k
1N5823
4.7 k
4.7k
100k
MPSA20
2200 mF
0.1 mF
470 mF
0.01 mF
4.7k
2.2k
51k
10
Figure 32. Step−Down Switching Converter
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10
NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
APPLICATIONS INFORMATION
The NCP431/NCP432 is a programmable precision
reference which is used in a variety of ways. It serves as a
reference voltage in circuits where a non−standard reference
voltage is needed. Other uses include feedback control for
driving an optocoupler in power supplies, voltage monitor,
constant current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 18. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
A simplified model of the NCP431/NCP432 is shown in
Figure 33. When tested for stability boundaries, the load
resistance is 150 W. The model reference input consists of an
input transistor and a dc emitter resistance connected to the
device anode. A dependent current source, Gm, develops a
current whose amplitude is determined by the difference
between the 1.78 V internal reference voltage source and the
input transistor emitter voltage. A portion of Gm flows
through compensation capacitance, CP2. The voltage across
CP2 drives the output dependent current source, Go, which
is connected across the device cathode and anode.
Model component values are:
Vref = 1.78 V
Gm = 0.3 + 2.7 exp (−IC/26 mA)
where IC is the device cathode current and Gm is in mhos
Go = 1.25 (Vcp2) mmhos.
Resistor and capacitor typical values are shown on the
model. Process tolerances are ±20% for resistors, ±10% for
capacitors, and ±40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
P1 +
P2 +
Z1 +
1
1
+
+ 7.96 kHz
2pR GMC P1
2p @ 1.0M @ 20 pF
1
2pR P2C P2
+
1
2p @ 10M @ 0.265 pF
+ 60 kHz
1
1
+
+ 500 kHz
2pR Z1C P1
2p @ 15.9k @ 20 pF
In addition, there is an external circuit pole defined by the
load:
PL +
1
2pR LC L
Also, the transfer dc voltage gain of the NCP431 is:
G + G MR GMGoR L
Example 1:
IC=10 mA, RL= 230 W,CL= 0. Define the transfer gain.
The DC gain is:
G + G MR GMGoR L + (2.138)(1.0M)(1.25m)(230)
+ 615 + 56 dB
Loop gain + G
8.25k
8.25k ) 15k
+ 218 + 47 dB
The resulting transfer function Bode plot is shown in
Figure 34. The asymptotic plot may be expressed as the
following equation:
Av + 615
ǒ1 )
ǒ1 )
jf
8.0 kHz
jf
500 kHz
Ǔ
Ǔǒ1 )
jf
60 kHz
Ǔ
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9°. This model matches the
Open−Loop Bode Plot of Figure 15. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44°.
Figure 33. Simplified NCP431/NCP432 Device Model
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NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
NCP431/NCP432 OPEN−LOOP VOLTAGE GAIN
VERSUS FREQUENCY
NCP431/NCP432 OPEN−LOOP BODE PLOT WITH
LOAD CAP
Figure 35. Example 2 Circuit Open Loop Gain Plot
Figure 34. Example 1 Circuit Open Loop Gain Plot
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very large
value to provide noise filtering and a dominant pole rolloff
of the system.
Example 2.
IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 18) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
G + G MR GMGoR L + (2.138)(1.0M)(1.25m)(230)
+ 6389 + 76 dB
The NCP431/NCP432 is often used as a regulator in
secondary side of a switch mode power supply (SMPS).
The benefit of this reference is high and stable gain under
low bias currents. Figure 36 shows dependence of the gain
(dynamic impedance) on the bias current. Value of
minimum cathode current that is needed to assure stable gain
is 80 mA maximum.
The resulting open loop Bode plot is shown in Figure 35.
The asymptotic plot may be expressed as the following
equation:
Av + 615
ǒ1 )
jf
8.0 kHz
ǒ1 )
500 kHz
Ǔǒ1 )
60 kHz
jf
jf
Ǔ
Ǔǒ1 )
jf
7.2 kHz
Ǔ
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about −46°. Therefore,
instability of this circuit is likely.
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NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
Figure 37. SMPS Secondary Side and Feedback
Connection on Primary Side
Figure 36. Knee of Reference
Regulator with TL431 or other references in secondary
side of a SMPS needs bias resistor to increase cathode
current to reach high and stable gain (refer to Figure 37).
This bias resistor does not have to be used in regulator with
NCP431/NCP432 thanks to its low minimum cathode
current.
The NCP431/NCP432 operates with very low leakage
and reference input current. Sum of these currents is lower
than 100 nA. Regulator with the NCP431/NCP432
minimizes parasitic power consumption.
The best way to achieve extremely low no−load
consumption in SMPS applications is to use
NCP431/NCP432 as regulator on the secondary side. The
consumption is reduced by minimum parasitic consumption
and very low bias current of NCP431/NCP432.
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NCP431A, SC431A, NCP431B, SC431B, NCP432B, SC432B Series
MARKING DIAGRAMS
NCP43
1xxxx
ALYW
8
1
N431xx
ALYW
G
xxx MG
G
1
xx, xxx, xxx = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
M
= Date Code
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Operating
Temperature Range
Package
Shipping†
1%
SOIC−8
(Pb−Free)
2500 / Tape & Reel
VRF
1%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP431BCSNT1G
VRJ
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP432BCSNT1G
VRM
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
ACLP
1%
TO−92 (TO−226)
(Pb−Free)
2000 / Tape & Reel
NCP431AIDR2G
AI
1%
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP431AISNT1G
VRG
1%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP431BISNT1G
VRK
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP432BISNT1G
VRN
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP431AILPRAG
AILP
1%
TO−92 (TO−226)
(Pb−Free)
2000 / Tape & Reel
NCP431AVDR2G
AV
1%
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP431AVSNT1G /
SC431AVSNT1G*
VRH
1%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP431AVLPRAG
AVLP
1%
TO−92 (TO−226)
(Pb−Free)
2000 / Tape & Reel
NCP431AVLPG
AVLP
1%
TO−92 (TO−226)
(Pb−Free)
2000 Units / Bag
NCP431BVSNT1G /
SC431BVSNT1G*
VRL
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
NCP432BVSNT1G /
SC432BVSNT1G*
VRP
0.5%
SOT−23−3
(Pb−Free)
3000 / Tape & Reel
Device
Marking
Tolerance
NCP431ACDR2G
AC
NCP431ACSNT1G
NCP431ACLPRAG
0°C to 70°C
−40°C to 85°C
−40°C to 125°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SC Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
SCALE 1:1
12
3
STRAIGHT LEAD
1
DATE 05 MAR 2021
2
3
BENT LEAD
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1.
2.
3.
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
VCC
GROUND 2
OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AS
DATE 30 JAN 2018
SCALE 4:1
D
0.25
3
E
1
2
T
HE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
DIM
A
A1
b
c
D
E
e
L
L1
HE
T
L
3X b
L1
VIEW C
e
TOP VIEW
A
A1
SIDE VIEW
SEE VIEW C
c
MIN
0.89
0.01
0.37
0.08
2.80
1.20
1.78
0.30
0.35
2.10
0°
MILLIMETERS
NOM
MAX
1.00
1.11
0.06
0.10
0.44
0.50
0.14
0.20
2.90
3.04
1.30
1.40
1.90
2.04
0.43
0.55
0.54
0.69
2.40
2.64
−−−
10 °
MIN
0.035
0.000
0.015
0.003
0.110
0.047
0.070
0.012
0.014
0.083
0°
INCHES
NOM
0.039
0.002
0.017
0.006
0.114
0.051
0.075
0.017
0.021
0.094
−−−
MAX
0.044
0.004
0.020
0.008
0.120
0.055
0.080
0.022
0.027
0.104
10°
GENERIC
MARKING DIAGRAM*
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXMG
G
1
3X
2.90
3X
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
0.90
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.95
PITCH
0.80
DIMENSIONS: MILLIMETERS
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 11:
STYLE 12:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. CATHODE
3. CATHODE−ANODE
3. ANODE
STYLE 15:
PIN 1. GATE
2. CATHODE
3. ANODE
STYLE 16:
PIN 1. ANODE
2. CATHODE
3. CATHODE
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
3. CATHODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. NO CONNECTION PIN 1. CATHODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
2. ANODE
3. GATE
3. ANODE
3. CATHODE−ANODE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 22:
PIN 1. RETURN
2. OUTPUT
3. INPUT
STYLE 23:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 24:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 27:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
STYLE 28:
PIN 1. ANODE
2. ANODE
3. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
STYLE 8:
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
STYLE 13:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 25:
PIN 1. ANODE
2. CATHODE
3. GATE
STYLE 14:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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